#include <op_encodings.hh>

Inheritance diagram for gem5::VegaISA::Inst_MUBUF:

Public Member Functions
	Inst_MUBUF (InFmt_MUBUF *, const std::string &opcode)

	~Inst_MUBUF ()

int	instSize () const override

void	generateDisassembly () override

void	initOperandInfo () override

Public Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
	VEGAGPUStaticInst (const std::string &opcode)

	~VEGAGPUStaticInst ()

void	generateDisassembly () override

bool	isFlatScratchRegister (int opIdx) override

bool	isExecMaskRegister (int opIdx) override

void	initOperandInfo () override

int	getOperandSize (int opIdx) override

int	coalescerTokenCount () const override
	Return the number of tokens needed by the coalescer.

ScalarRegU32	srcLiteral () const override

Public Member Functions inherited from gem5::GPUStaticInst
	GPUStaticInst (const std::string &opcode)

virtual	~GPUStaticInst ()

void	instAddr (int inst_addr)

int	instAddr () const

int	nextInstAddr () const

void	instNum (int num)

int	instNum ()

void	ipdInstNum (int num)

int	ipdInstNum () const

void	initDynOperandInfo (Wavefront wf, ComputeUnit cu)

virtual void	execute (GPUDynInstPtr gpuDynInst)=0

const std::string &	disassemble ()

virtual int	getNumOperands ()=0

virtual int	numDstRegOperands ()=0

virtual int	numSrcRegOperands ()=0

int	numSrcVecOperands ()

int	numDstVecOperands ()

int	numSrcVecDWords ()

int	numDstVecDWords ()

int	numSrcScalarOperands ()

int	numDstScalarOperands ()

int	numSrcScalarDWords ()

int	numDstScalarDWords ()

int	maxOperandSize ()

bool	isALU () const

bool	isBranch () const

bool	isCondBranch () const

bool	isNop () const

bool	isReturn () const

bool	isEndOfKernel () const

bool	isKernelLaunch () const

bool	isSDWAInst () const

bool	isDPPInst () const

bool	isUnconditionalJump () const

bool	isSpecialOp () const

bool	isWaitcnt () const

bool	isSleep () const

bool	isBarrier () const

bool	isMemSync () const

bool	isMemRef () const

bool	isFlat () const

bool	isFlatGlobal () const

bool	isFlatScratch () const

bool	isLoad () const

bool	isStore () const

bool	isAtomic () const

bool	isAtomicNoRet () const

bool	isAtomicRet () const

bool	isScalar () const

bool	readsSCC () const

bool	writesSCC () const

bool	readsVCC () const

bool	writesVCC () const

bool	readsEXEC () const

bool	writesEXEC () const

bool	readsMode () const

bool	writesMode () const

bool	ignoreExec () const

bool	isAtomicAnd () const

bool	isAtomicOr () const

bool	isAtomicXor () const

bool	isAtomicCAS () const

bool	isAtomicExch () const

bool	isAtomicAdd () const

bool	isAtomicSub () const

bool	isAtomicInc () const

bool	isAtomicDec () const

bool	isAtomicMax () const

bool	isAtomicMin () const

bool	isArgLoad () const

bool	isGlobalMem () const

bool	isLocalMem () const

bool	isArgSeg () const

bool	isGlobalSeg () const

bool	isGroupSeg () const

bool	isKernArgSeg () const

bool	isPrivateSeg () const

bool	isReadOnlySeg () const

bool	isSpillSeg () const

bool	isGloballyCoherent () const
	Coherence domain of a memory instruction.

bool	isSystemCoherent () const

bool	isI8 () const

bool	isF16 () const

bool	isF32 () const

bool	isF64 () const

bool	isFMA () const

bool	isMAC () const

bool	isMAD () const

bool	isMFMA () const

virtual void	initiateAcc (GPUDynInstPtr gpuDynInst)

virtual void	completeAcc (GPUDynInstPtr gpuDynInst)

virtual uint32_t	getTargetPc ()

void	setFlag (Flags flag)

const std::string &	opcode () const

const std::vector< OperandInfo > &	srcOperands () const

const std::vector< OperandInfo > &	dstOperands () const

const std::vector< OperandInfo > &	srcVecRegOperands () const

const std::vector< OperandInfo > &	dstVecRegOperands () const

const std::vector< OperandInfo > &	srcScalarRegOperands () const

const std::vector< OperandInfo > &	dstScalarRegOperands () const

Protected Member Functions
template<typename T >
void	initMemRead (GPUDynInstPtr gpuDynInst)

template<int N>
void	initMemRead (GPUDynInstPtr gpuDynInst)

template<typename T >
void	initMemWrite (GPUDynInstPtr gpuDynInst)

template<int N>
void	initMemWrite (GPUDynInstPtr gpuDynInst)

template<typename T >
void	initAtomicAccess (GPUDynInstPtr gpuDynInst)

void	injectGlobalMemFence (GPUDynInstPtr gpuDynInst)

template<typename VOFF , typename VIDX , typename SRSRC , typename SOFF >
void	calcAddr (GPUDynInstPtr gpuDynInst, VOFF v_off, VIDX v_idx, SRSRC s_rsrc_desc, SOFF s_offset, int inst_offset)
	MUBUF insructions calculate their addresses as follows:

Protected Member Functions inherited from gem5::VegaISA::VEGAGPUStaticInst
void	panicUnimplemented () const

Protected Attributes
InFmt_MUBUF	instData

InFmt_MUBUF_1	extData

VectorMask	oobMask

Protected Attributes inherited from gem5::VegaISA::VEGAGPUStaticInst
ScalarRegU32	_srcLiteral
	if the instruction has a src literal - an immediate value that is part of the instruction stream - we store that here

Protected Attributes inherited from gem5::GPUStaticInst
const std::string	_opcode

std::string	disassembly

int	_instNum

int	_instAddr

std::vector< OperandInfo >	srcOps

std::vector< OperandInfo >	dstOps

Additional Inherited Members
Public Types inherited from gem5::GPUStaticInst
enum	OpType { SRC_VEC , SRC_SCALAR , DST_VEC , DST_SCALAR }

typedef int(RegisterManager::*	MapRegFn) (Wavefront *, int)

Public Attributes inherited from gem5::GPUStaticInst
enums::StorageClassType	executed_as

Static Public Attributes inherited from gem5::GPUStaticInst
static uint64_t	dynamic_id_count

Detailed Description

Definition at line 867 of file op_encodings.hh.

Constructor & Destructor Documentation

◆ Inst_MUBUF()

gem5::VegaISA::Inst_MUBUF::Inst_MUBUF	(	InFmt_MUBUF *	iFmt,
		const std::string &	opcode )

Definition at line 1415 of file op_encodings.cc.

References gem5::VegaISA::VEGAGPUStaticInst::_srcLiteral, extData, gem5::VegaISA::InFmt_MUBUF::GLC, instData, gem5::GPUStaticInst::setFlag(), and gem5::VegaISA::InFmt_MUBUF::SLC.

◆ ~Inst_MUBUF()

gem5::VegaISA::Inst_MUBUF::~Inst_MUBUF ( )

Definition at line 1431 of file op_encodings.cc.

Member Function Documentation

◆ calcAddr()

template<typename VOFF , typename VIDX , typename SRSRC , typename SOFF >

void gem5::VegaISA::Inst_MUBUF::calcAddr	(	GPUDynInstPtr	gpuDynInst,
		VOFF	v_off,
		VIDX	v_idx,
		SRSRC	s_rsrc_desc,
		SOFF	s_offset,
		int	inst_offset )

inlineprotected

MUBUF insructions calculate their addresses as follows:

index = (IDXEN ? vgpr_idx : 0) + (const_add_tid_en ? TID : 0) offset = (OFFEN ? vgpr_off : 0) + inst_off

/ ====================== LINEAR ADDRESSING ====================== / VADDR = base + sgpr_off + offset + stride * index

/ ===================== SWIZZLED ADDRESSING ===================== / index_msb = index / const_index_stride index_lsb = index % const_index_stride offset_msb = offset / const_element_size offset_lsb = offset % const_element_size buffer_offset = ((index_msb * stride + offset_msb * const_element_size) * const_index_stride + index_lsb * const_element_size + offset_lsb)

VADDR = base + sgpr_off + buffer_offset

first we calculate the buffer's index and offset. these will be used for either linear or swizzled buffers.

Range check behavior causes out of range accesses to to be treated differently. Out of range accesses return 0 for loads and are ignored for stores. For non-formatted accesses, this is done on a per-lane basis.

Definition at line 982 of file op_encodings.hh.

References gem5::VegaISA::BufferRsrcDescriptor::addTidEn, gem5::VegaISA::BufferRsrcDescriptor::baseAddr, gem5::VegaISA::BufferRsrcDescriptor::dataFmt, DPRINTF, gem5::VegaISA::BufferRsrcDescriptor::elemSize, gem5::VegaISA::BufferRsrcDescriptor::idxStride, gem5::VegaISA::BufferRsrcDescriptor::numRecords, gem5::ArmISA::NumVecElemPerVecReg, oobMask, gem5::ArmISA::stride, gem5::VegaISA::BufferRsrcDescriptor::stride, gem5::VegaISA::BufferRsrcDescriptor::swizzleEn, and gem5::MipsISA::vaddr.