gem5 v24.0.0.0
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Classes | Public Types | Public Member Functions | Public Attributes | Protected Attributes | Private Member Functions | Private Attributes | List of all members
gem5::ComputeUnit Class Reference

#include <compute_unit.hh>

Inheritance diagram for gem5::ComputeUnit:
gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named

Classes

struct  ComputeUnitStats
 
class  DataPort
 Data access Port. More...
 
class  DTLBPort
 Data TLB port. More...
 
class  GMTokenPort
 
class  ITLBPort
 
class  LDSPort
 the port intended to communicate between the CU and its LDS More...
 
class  ScalarDataPort
 
class  ScalarDTLBPort
 
class  SQCPort
 

Public Types

typedef ComputeUnitParams Params
 
typedef std::unordered_map< Addr, std::pair< int, int > > pageDataStruct
 
- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject.
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 

Public Member Functions

int numExeUnits () const
 
int firstMemUnit () const
 
int lastMemUnit () const
 
int mapWaveToScalarAlu (Wavefront *w) const
 
int mapWaveToScalarAluGlobalIdx (Wavefront *w) const
 
int mapWaveToGlobalMem (Wavefront *w) const
 
int mapWaveToLocalMem (Wavefront *w) const
 
int mapWaveToScalarMem (Wavefront *w) const
 
void insertInPipeMap (Wavefront *w)
 
void deleteFromPipeMap (Wavefront *w)
 
 ComputeUnit (const Params &p)
 
 ~ComputeUnit ()
 
int oprNetPipeLength () const
 
int simdUnitWidth () const
 
int spBypassLength () const
 
int dpBypassLength () const
 
int rfcLength () const
 
int scalarPipeLength () const
 
int storeBusLength () const
 
int loadBusLength () const
 
int wfSize () const
 
void exec ()
 
void initiateFetch (Wavefront *wavefront)
 
void fetch (PacketPtr pkt, Wavefront *wavefront)
 
void fillKernelState (Wavefront *w, HSAQueueEntry *task)
 
void startWavefront (Wavefront *w, int waveId, LdsChunk *ldsChunk, HSAQueueEntry *task, int bar_id, bool fetchContext=false)
 
void doInvalidate (RequestPtr req, int kernId)
 trigger invalidate operation in the CU
 
void doFlush (GPUDynInstPtr gpuDynInst)
 trigger flush operation in the cu
 
void doSQCInvalidate (RequestPtr req, int kernId)
 trigger SQCinvalidate operation in the CU
 
void dispWorkgroup (HSAQueueEntry *task, int num_wfs_in_wg)
 
bool hasDispResources (HSAQueueEntry *task, int &num_wfs_in_wg)
 
int cacheLineSize () const
 
int getCacheLineBits () const
 
void resetRegisterPool ()
 
int numYetToReachBarrier (int bar_id)
 
bool allAtBarrier (int bar_id)
 
void incNumAtBarrier (int bar_id)
 
int numAtBarrier (int bar_id)
 
int maxBarrierCnt (int bar_id)
 
void resetBarrier (int bar_id)
 
void decMaxBarrierCnt (int bar_id)
 
void releaseBarrier (int bar_id)
 
void releaseWFsFromBarrier (int bar_id)
 
int numBarrierSlots () const
 
template<typename c0 , typename c1 >
void doSmReturn (GPUDynInstPtr gpuDynInst)
 
virtual void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected.
 
void sendRequest (GPUDynInstPtr gpuDynInst, PortID index, PacketPtr pkt)
 
void sendScalarRequest (GPUDynInstPtr gpuDynInst, PacketPtr pkt)
 
void injectGlobalMemFence (GPUDynInstPtr gpuDynInst, bool kernelMemSync, RequestPtr req=nullptr)
 
void handleMemPacket (PacketPtr pkt, int memport_index)
 
bool processTimingPacket (PacketPtr pkt)
 
void processFetchReturn (PacketPtr pkt)
 
void updatePageDivergenceDist (Addr addr)
 
RequestorID requestorId ()
 
RequestorID vramRequestorId ()
 Forward the VRAM requestor ID needed for device memory from shader.
 
bool isDone () const
 
bool isVectorAluIdle (uint32_t simdId) const
 
void handleSQCReturn (PacketPtr pkt)
 
void sendInvL2 (Addr paddr)
 
LdsState & getLds () const
 
int32_t getRefCounter (const uint32_t dispatchId, const uint32_t wgId) const
 
bool sendToLds (GPUDynInstPtr gpuDynInst)
 send a general request to the LDS make sure to look at the return value here as your request might be NACK'd and returning false means that you have to have some backup plan
 
void exitCallback ()
 
TokenManager * getTokenManager ()
 
Port & getPort (const std::string &if_name, PortID idx) override
 Get a port with a given name and index.
 
InstSeqNum getAndIncSeqNum ()
 
void updateInstStats (GPUDynInstPtr gpuDynInst)
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object.
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object.
 
- Public Member Functions inherited from gem5::SimObject
const Params & params () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint.
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint.
 
virtual void regProbePoints ()
 Register probe points for this object.
 
virtual void regProbeListeners ()
 Register probe listeners for this object.
 
ProbeManager * getProbeManager ()
 Get the probe manager for this object.
 
virtual void startup ()
 startup() is the final initialization call before simulation.
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining.
 
virtual void memWriteback ()
 Write back dirty buffers to memory using functional writes.
 
virtual void memInvalidate ()
 Invalidate the contents of memory buffers.
 
void serialize (CheckpointOut &cp) const override
 Serialize an object.
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object.
 
- Public Member Functions inherited from gem5::EventManager
EventQueue * eventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue.
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section.
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object.
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object.
 
virtual void notifyFork ()
 Notify a child process of a fork.
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group.
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters.
 
virtual void resetStats ()
 Callback to reset stats.
 
virtual void preDumpStats ()
 Callback before stats are dumped.
 
void addStat (statistics::Info *info)
 Register a stat with this group.
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object.
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object.
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block.
 
const Info * resolveStat (std::string name) const
 Resolve a stat by its name within this group.
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block.
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Group & operator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick.
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge.
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Public Attributes

int numVectorGlobalMemUnits
 
WaitClass glbMemToVrfBus
 
WaitClass vrfToGlobalMemPipeBus
 
WaitClass vectorGlobalMemUnit
 
int numVectorSharedMemUnits
 
WaitClass locMemToVrfBus
 
WaitClass vrfToLocalMemPipeBus
 
WaitClass vectorSharedMemUnit
 
int numScalarMemUnits
 
WaitClass scalarMemToSrfBus
 
WaitClass srfToScalarMemPipeBus
 
WaitClass scalarMemUnit
 
int numVectorALUs
 
std::vector< WaitClass > vectorALUs
 
int numScalarALUs
 
std::vector< WaitClass > scalarALUs
 
int vrfToCoalescerBusWidth
 
int coalescerToVrfBusWidth
 
int numCyclesPerStoreTransfer
 
int numCyclesPerLoadTransfer
 
std::unordered_set< uint64_t > pipeMap
 
RegisterManager * registerManager
 
FetchStage fetchStage
 
ScoreboardCheckStage scoreboardCheckStage
 
ScheduleStage scheduleStage
 
ExecStage execStage
 
GlobalMemPipeline globalMemoryPipe
 
LocalMemPipeline localMemoryPipe
 
ScalarMemPipeline scalarMemoryPipe
 
EventFunctionWrapper tickEvent
 
std::vector< std::vector< Wavefront * > > wfList
 
int cu_id
 
std::vector< VectorRegisterFile * > vrf
 
std::vector< ScalarRegisterFile * > srf
 
std::vector< RegisterFileCache * > rfc
 
int simdWidth
 
int spBypassPipeLength
 
int dpBypassPipeLength
 
int rfcPipeLength
 
int scalarPipeStages
 
int operandNetworkLength
 
Cycles issuePeriod
 
Cycles vrf_gm_bus_latency
 
Cycles srf_scm_bus_latency
 
Cycles vrf_lm_bus_latency
 
std::vector< uint64_t > lastExecCycle
 
std::vector< uint64_t > instExecPerSimd
 
bool perLaneTLB
 
int prefetchDepth
 
int prefetchStride
 
std::vector< Addr > lastVaddrCU
 
std::vector< std::vector< Addr > > lastVaddrSimd
 
std::vector< std::vector< std::vector< Addr > > > lastVaddrWF
 
enums::PrefetchType prefetchType
 
EXEC_POLICY exec_policy
 
bool debugSegFault
 
Tick idleCUTimeout
 
int idleWfs
 
bool functionalTLB
 
bool localMemBarrier
 
bool countPages
 
Shader * shader
 
Tick req_tick_latency
 
Tick resp_tick_latency
 
Tick scalar_req_tick_latency
 
Tick scalar_resp_tick_latency
 
std::vector< int > numWfsToSched
 Number of WFs to schedule to each SIMD.
 
std::vector< int > vectorRegsReserved
 
std::vector< int > scalarRegsReserved
 
int numVecRegsPerSimd
 
int numScalarRegsPerSimd
 
std::map< Addr, int > pagesTouched
 
pageDataStruct pageAccesses
 
TokenManager * memPortTokens
 
GMTokenPort gmTokenPort
 
LDSPort ldsPort
 The port to access the Local Data Store Can be connected to a LDS object.
 
std::vector< DataPort > memPort
 The memory port for SIMD data accesses.
 
std::vector< DTLBPort > tlbPort
 
ScalarDataPort scalarDataPort
 
ScalarDTLBPort scalarDTLBPort
 
SQCPort sqcPort
 
ITLBPort sqcTLBPort
 
int activeWaves
 
gem5::ComputeUnit::ComputeUnitStats stats
 
- Public Attributes inherited from gem5::ClockedObject
PowerState * powerState
 

Protected Attributes

RequestorID _requestorId
 
LdsState & lds
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters.
 
- Protected Attributes inherited from gem5::EventManager
EventQueue * eventq
 A pointer to this object's event queue.
 

Private Member Functions

WFBarrier & barrierSlot (int bar_id)
 
int getFreeBarrierId ()
 

Private Attributes

const int _cacheLineSize
 
const int _numBarrierSlots
 
int cacheLineBits
 
InstSeqNum globalSeqNum
 
int wavefrontSize
 
ScoreboardCheckToSchedule scoreboardCheckToSchedule
 TODO: Update these comments once the pipe stage interface has been fully refactored.
 
ScheduleToExecute scheduleToExecute
 
std::vector< WFBarrier > wfBarrierSlots
 The barrier slots for this CU.
 
std::unordered_set< int > freeBarrierIds
 A set used to easily retrieve a free barrier ID.
 
std::unordered_map< GPUDynInstPtr, Tick > headTailMap
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system.
 
static SimObject * find (const char *name)
 Find the SimObject with the given name and return a pointer to it.
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
 
static SimObjectResolver * getSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section.
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it.
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain.
 
void signalDrainDone () const
 Signal that an object is drained.
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters.
 
 Clocked (Clocked &)=delete
 
Clocked & operator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance.
 
void resetClock () const
 Reset the object's clock using the current global tick value.
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.
 

Detailed Description

Definition at line 202 of file compute_unit.hh.

Member Typedef Documentation

◆ pageDataStruct

typedef std::unordered_map<Addr, std::pair<int, int> > gem5::ComputeUnit::pageDataStruct

Definition at line 496 of file compute_unit.hh.

◆ Params

typedef ComputeUnitParams gem5::ComputeUnit::Params

Definition at line 291 of file compute_unit.hh.

Constructor & Destructor Documentation

◆ ComputeUnit()

gem5::ComputeUnit::ComputeUnit ( const Params & p)

This check is necessary because std::bitset only provides conversion to unsigned long or unsigned long long via to_ulong() or to_ullong(). there are a few places in the code where to_ullong() is used, however if wavefrontSize is larger than a value the host can support then bitset will throw a runtime exception. We should remove all use of to_long() or to_ullong() so we can have wavefrontSize greater than 64b, however until that is done this assert is required.

Definition at line 66 of file compute_unit.cc.

References exec().

◆ ~ComputeUnit()

gem5::ComputeUnit::~ComputeUnit ( )

Definition at line 233 of file compute_unit.cc.

References gem5::ArmISA::i, lastVaddrCU, lastVaddrSimd, gem5::Shader::n_wf, numVectorALUs, shader, and wfList.

Member Function Documentation

◆ allAtBarrier()

bool gem5::ComputeUnit::allAtBarrier ( int bar_id)

Definition at line 696 of file compute_unit.cc.

References barrierSlot().

Referenced by gem5::ScoreboardCheckStage::ready().

◆ barrierSlot()

WFBarrier & gem5::ComputeUnit::barrierSlot ( int bar_id)
inlineprivate

Definition at line 427 of file compute_unit.hh.

References gem5::WFBarrier::InvalidID, and wfBarrierSlots.

Referenced by allAtBarrier(), decMaxBarrierCnt(), dispWorkgroup(), incNumAtBarrier(), maxBarrierCnt(), numAtBarrier(), numYetToReachBarrier(), releaseBarrier(), and resetBarrier().

◆ cacheLineSize()

int gem5::ComputeUnit::cacheLineSize ( ) const
inline

Definition at line 420 of file compute_unit.hh.

References _cacheLineSize.

Referenced by gem5::FetchUnit::init(), and gem5::FetchUnit::initiateFetch().

◆ decMaxBarrierCnt()

void gem5::ComputeUnit::decMaxBarrierCnt ( int bar_id)

Definition at line 731 of file compute_unit.cc.

References barrierSlot().

Referenced by gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute().

◆ deleteFromPipeMap()

void gem5::ComputeUnit::deleteFromPipeMap ( Wavefront * w)

Definition at line 549 of file compute_unit.cc.

References panic_if, pipeMap, and gem5::MipsISA::w.

Referenced by gem5::Wavefront::exec().

◆ dispWorkgroup()

void gem5::ComputeUnit::dispWorkgroup ( HSAQueueEntry * task,
int num_wfs_in_wg )

If this WG only has one WF it will not consume any barrier resources because it has no need of them.

Find a free barrier slot for this WG. Each WF in the WG will receive the same barrier ID.

Definition at line 462 of file compute_unit.cc.

References gem5::RegisterManager::allocateRegisters(), barrierSlot(), cu_id, gem5::HSAQueueEntry::dispatchId(), DPRINTF, fillKernelState(), getFreeBarrierId(), gem5::HSAQueueEntry::globalWgId(), gem5::ArmISA::i, gem5::WFBarrier::InvalidID, gem5::HSAQueueEntry::isInvDone(), lds, gem5::HSAQueueEntry::ldsSize(), gem5::Shader::n_wf, gem5::Clocked::nextCycle(), gem5::HSAQueueEntry::numScalarRegs(), numVectorALUs, gem5::HSAQueueEntry::numVectorRegs(), numWfsToSched, panic_if, registerManager, gem5::LdsState::reserveSpace(), gem5::Wavefront::S_STOPPED, gem5::EventManager::schedule(), gem5::Event::scheduled(), shader, startWavefront(), tickEvent, gem5::MipsISA::w, and wfList.

◆ doFlush()

void gem5::ComputeUnit::doFlush ( GPUDynInstPtr gpuDynInst)

trigger flush operation in the cu

gpuDynInst: inst passed to the request

Definition at line 424 of file compute_unit.cc.

References injectGlobalMemFence().

◆ doInvalidate()

void gem5::ComputeUnit::doInvalidate ( RequestPtr req,
int kernId )

trigger invalidate operation in the CU

req: request initialized in shader, carrying the invalidate flags

Definition at line 405 of file compute_unit.cc.

References getAndIncSeqNum(), and injectGlobalMemFence().

◆ doSmReturn()

template<typename c0 , typename c1 >
void gem5::ComputeUnit::doSmReturn ( GPUDynInstPtr gpuDynInst)

◆ doSQCInvalidate()

void gem5::ComputeUnit::doSQCInvalidate ( RequestPtr req,
int kernId )

trigger SQCinvalidate operation in the CU

req: request initialized in shader, carrying the invalidate flags

Definition at line 434 of file compute_unit.cc.

References getAndIncSeqNum(), gem5::ScalarMemPipeline::injectScalarMemFence(), and scalarMemoryPipe.

◆ dpBypassLength()

int gem5::ComputeUnit::dpBypassLength ( ) const
inline

Definition at line 397 of file compute_unit.hh.

References dpBypassPipeLength.

Referenced by gem5::VectorRegisterFile::waveExecuteInst().

◆ exec()

void gem5::ComputeUnit::exec ( )

Definition at line 761 of file compute_unit.cc.

References cu_id, DPRINTF, gem5::ExecStage::exec(), gem5::FetchStage::exec(), gem5::GlobalMemPipeline::exec(), gem5::LocalMemPipeline::exec(), gem5::ScalarMemPipeline::exec(), gem5::ScheduleStage::exec(), gem5::ScoreboardCheckStage::exec(), execStage, fetchStage, globalMemoryPipe, isDone(), localMemoryPipe, gem5::Clocked::nextCycle(), gem5::Shader::notifyCuSleep(), scalarMemoryPipe, gem5::EventManager::schedule(), scheduleStage, scoreboardCheckStage, shader, srf, stats, tickEvent, gem5::ComputeUnit::ComputeUnitStats::totalCycles, and vrf.

Referenced by ComputeUnit().

◆ exitCallback()

void gem5::ComputeUnit::exitCallback ( )

Definition at line 2114 of file compute_unit.cc.

References countPages, gem5::OutputDirectory::create(), gem5::Named::name(), pageAccesses, gem5::simout, and gem5::OutputStream::stream().

◆ fetch()

void gem5::ComputeUnit::fetch ( PacketPtr pkt,
Wavefront * wavefront )

◆ fillKernelState()

void gem5::ComputeUnit::fillKernelState ( Wavefront * w,
HSAQueueEntry * task )

Definition at line 310 of file compute_unit.cc.

References gem5::HSAQueueEntry::gridSize(), gem5::HSAQueueEntry::numScalarRegs(), gem5::HSAQueueEntry::numVectorRegs(), gem5::MipsISA::w, and gem5::HSAQueueEntry::wgSize().

Referenced by dispWorkgroup().

◆ firstMemUnit()

int gem5::ComputeUnit::firstMemUnit ( ) const

Definition at line 254 of file compute_unit.cc.

References numScalarALUs, and numVectorALUs.

Referenced by gem5::ScheduleStage::arbitrateVrfToLdsBus(), and gem5::ScheduleStage::exec().

◆ getAndIncSeqNum()

InstSeqNum gem5::ComputeUnit::getAndIncSeqNum ( )
inline

Definition at line 967 of file compute_unit.hh.

References globalSeqNum.

Referenced by doInvalidate(), and doSQCInvalidate().

◆ getCacheLineBits()

int gem5::ComputeUnit::getCacheLineBits ( ) const
inline

Definition at line 421 of file compute_unit.hh.

References cacheLineBits.

Referenced by gem5::FetchUnit::initiateFetch().

◆ getFreeBarrierId()

int gem5::ComputeUnit::getFreeBarrierId ( )
inlineprivate

Definition at line 434 of file compute_unit.hh.

References freeBarrierIds.

Referenced by dispWorkgroup().

◆ getLds()

LdsState & gem5::ComputeUnit::getLds ( ) const
inline

Definition at line 486 of file compute_unit.hh.

References lds.

Referenced by gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), and gem5::GPUDynInst::resolveFlatSegment().

◆ getPort()

Port & gem5::ComputeUnit::getPort ( const std::string & if_name,
PortID idx )
inlineoverridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters
if_namePort name
idxIndex in the case of a VectorPort
Returns
A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 944 of file compute_unit.hh.

References gem5::SimObject::getPort(), gmTokenPort, ldsPort, memPort, scalarDataPort, scalarDTLBPort, sqcPort, sqcTLBPort, and tlbPort.

◆ getRefCounter()

int32_t gem5::ComputeUnit::getRefCounter ( const uint32_t dispatchId,
const uint32_t wgId ) const

Definition at line 2161 of file compute_unit.cc.

References gem5::LdsState::getRefCounter(), and lds.

◆ getTokenManager()

TokenManager * gem5::ComputeUnit::getTokenManager ( )
inline

Definition at line 923 of file compute_unit.hh.

References memPortTokens.

Referenced by gem5::GlobalMemPipeline::exec(), gem5::LocalMemPipeline::exec(), and gem5::Wavefront::exec().

◆ handleMemPacket()

void gem5::ComputeUnit::handleMemPacket ( PacketPtr pkt,
int memport_index )

◆ handleSQCReturn()

void gem5::ComputeUnit::handleSQCReturn ( PacketPtr pkt)

Definition at line 1078 of file compute_unit.cc.

References fetchStage, and gem5::FetchStage::processFetchReturn().

◆ hasDispResources()

bool gem5::ComputeUnit::hasDispResources ( HSAQueueEntry * task,
int & num_wfs_in_wg )

Definition at line 561 of file compute_unit.cc.

References gem5::RegisterManager::canAllocateSgprs(), gem5::RegisterManager::canAllocateVgprs(), gem5::LdsState::canReserve(), gem5::ArmISA::d, DPRINTF, freeBarrierIds, gem5::HSAQueueEntry::gridSize(), gem5::ArmISA::i, lds, gem5::HSAQueueEntry::ldsSize(), gem5::HSAQueueEntry::MAX_DIM, gem5::Shader::n_wf, gem5::HSAQueueEntry::numScalarRegs(), numScalarRegsPerSimd, gem5::ComputeUnit::ComputeUnitStats::numTimesWgBlockedDueSgprAlloc, gem5::ComputeUnit::ComputeUnitStats::numTimesWgBlockedDueVgprAlloc, numVecRegsPerSimd, numVectorALUs, gem5::HSAQueueEntry::numVectorRegs(), numWfsToSched, panic_if, registerManager, gem5::Wavefront::S_STOPPED, shader, stats, wfList, wfSize(), gem5::ComputeUnit::ComputeUnitStats::wgBlockedDueBarrierAllocation, gem5::ComputeUnit::ComputeUnitStats::wgBlockedDueLdsAllocation, gem5::HSAQueueEntry::wgId(), and gem5::HSAQueueEntry::wgSize().

◆ incNumAtBarrier()

void gem5::ComputeUnit::incNumAtBarrier ( int bar_id)

Definition at line 703 of file compute_unit.cc.

References barrierSlot().

Referenced by gem5::VegaISA::Inst_SOPP__S_BARRIER::execute().

◆ init()

void gem5::ComputeUnit::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 794 of file compute_unit.cc.

References gem5::Clocked::clockPeriod(), execStage, fatal_if, fetchStage, glbMemToVrfBus, globalMemoryPipe, gmTokenPort, gem5::ArmISA::i, gem5::ExecStage::init(), gem5::FetchStage::init(), gem5::GlobalMemPipeline::init(), gem5::ScheduleStage::init(), gem5::WaitClass::init(), locMemToVrfBus, memPortTokens, numScalarALUs, numScalarMemUnits, numVectorALUs, numVectorGlobalMemUnits, numVectorSharedMemUnits, scalarALUs, scalarMemToSrfBus, scalarMemUnit, scalarRegsReserved, scheduleStage, gem5::TokenRequestPort::setTokenManager(), srfToScalarMemPipeBus, vectorALUs, vectorGlobalMemUnit, vectorRegsReserved, vectorSharedMemUnit, vrfToGlobalMemPipeBus, and vrfToLocalMemPipeBus.

◆ initiateFetch()

void gem5::ComputeUnit::initiateFetch ( Wavefront * wavefront)

◆ injectGlobalMemFence()

void gem5::ComputeUnit::injectGlobalMemFence ( GPUDynInstPtr gpuDynInst,
bool kernelMemSync,
RequestPtr req = nullptr )

Definition at line 1355 of file compute_unit.cc.

References cu_id, gem5::curTick(), DPRINTF, gem5::Request::FLUSH_L2, gem5::Shader::impl_kern_end_rel, gem5::Request::INV_L1, gem5::Request::KERNEL, memPort, gem5::MemCmd::MemSyncReq, gem5::Packet::pushSenderState(), gem5::Packet::req, req_tick_latency, gem5::EventManager::schedule(), shader, and vramRequestorId().

Referenced by doFlush(), and doInvalidate().

◆ insertInPipeMap()

void gem5::ComputeUnit::insertInPipeMap ( Wavefront * w)

Definition at line 540 of file compute_unit.cc.

References panic_if, pipeMap, and gem5::MipsISA::w.

Referenced by gem5::ScheduleStage::addToSchList().

◆ isDone()

bool gem5::ComputeUnit::isDone ( ) const

Definition at line 2131 of file compute_unit.cc.

References glbMemToVrfBus, globalMemoryPipe, gem5::ArmISA::i, gem5::GlobalMemPipeline::isGMReqFIFOWrRdy(), gem5::LocalMemPipeline::isLMReqFIFOWrRdy(), gem5::LocalMemPipeline::isLMRespFIFOWrRdy(), isVectorAluIdle(), localMemoryPipe, locMemToVrfBus, numVectorALUs, gem5::WaitClass::rdy(), scalarMemToSrfBus, srfToScalarMemPipeBus, vrfToGlobalMemPipeBus, and vrfToLocalMemPipeBus.

Referenced by exec().

◆ isVectorAluIdle()

bool gem5::ComputeUnit::isVectorAluIdle ( uint32_t simdId) const

Definition at line 2168 of file compute_unit.cc.

References gem5::Shader::n_wf, numVectorALUs, gem5::Wavefront::S_STOPPED, shader, and wfList.

Referenced by isDone().

◆ lastMemUnit()

int gem5::ComputeUnit::lastMemUnit ( ) const

Definition at line 261 of file compute_unit.cc.

References numExeUnits().

Referenced by gem5::ScheduleStage::exec().

◆ loadBusLength()

int gem5::ComputeUnit::loadBusLength ( ) const
inline

Definition at line 401 of file compute_unit.hh.

References numCyclesPerLoadTransfer.

Referenced by gem5::LdsState::processPacket().

◆ mapWaveToGlobalMem()

int gem5::ComputeUnit::mapWaveToGlobalMem ( Wavefront * w) const

Definition at line 286 of file compute_unit.cc.

References numScalarALUs, and numVectorALUs.

Referenced by gem5::Wavefront::init().

◆ mapWaveToLocalMem()

int gem5::ComputeUnit::mapWaveToLocalMem ( Wavefront * w) const

Definition at line 294 of file compute_unit.cc.

References numScalarALUs, numVectorALUs, and numVectorGlobalMemUnits.

Referenced by gem5::Wavefront::init().

◆ mapWaveToScalarAlu()

int gem5::ComputeUnit::mapWaveToScalarAlu ( Wavefront * w) const

Definition at line 268 of file compute_unit.cc.

References numScalarALUs, and gem5::MipsISA::w.

Referenced by gem5::Wavefront::init(), and mapWaveToScalarAluGlobalIdx().

◆ mapWaveToScalarAluGlobalIdx()

int gem5::ComputeUnit::mapWaveToScalarAluGlobalIdx ( Wavefront * w) const

Definition at line 279 of file compute_unit.cc.

References mapWaveToScalarAlu(), numVectorALUs, and gem5::MipsISA::w.

Referenced by gem5::Wavefront::init().

◆ mapWaveToScalarMem()

int gem5::ComputeUnit::mapWaveToScalarMem ( Wavefront * w) const

Definition at line 302 of file compute_unit.cc.

References numScalarALUs, numVectorALUs, numVectorGlobalMemUnits, and numVectorSharedMemUnits.

Referenced by gem5::Wavefront::init().

◆ maxBarrierCnt()

int gem5::ComputeUnit::maxBarrierCnt ( int bar_id)

Definition at line 717 of file compute_unit.cc.

References barrierSlot().

Referenced by gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute().

◆ numAtBarrier()

int gem5::ComputeUnit::numAtBarrier ( int bar_id)

Definition at line 710 of file compute_unit.cc.

References barrierSlot().

Referenced by gem5::VegaISA::Inst_SOPP__S_BARRIER::execute().

◆ numBarrierSlots()

int gem5::ComputeUnit::numBarrierSlots ( ) const
inline

Definition at line 453 of file compute_unit.hh.

References _numBarrierSlots.

◆ numExeUnits()

int gem5::ComputeUnit::numExeUnits ( ) const

Definition at line 246 of file compute_unit.cc.

References numScalarALUs, numScalarMemUnits, numVectorALUs, numVectorGlobalMemUnits, and numVectorSharedMemUnits.

Referenced by gem5::ScheduleStage::checkRfOperandReadComplete(), gem5::ExecStage::dumpDispList(), gem5::ExecStage::exec(), gem5::ScheduleStage::exec(), gem5::ExecStage::ExecStageStats::ExecStageStats(), gem5::ScheduleStage::fillDispatchList(), gem5::ScheduleStage::init(), lastMemUnit(), gem5::ScoreboardCheckStage::mapWaveToExeUnit(), gem5::ScheduleStage::reserveResources(), gem5::ScheduleStage::scheduleRfDestOperands(), and gem5::ScheduleStage::ScheduleStage().

◆ numYetToReachBarrier()

int gem5::ComputeUnit::numYetToReachBarrier ( int bar_id)

Definition at line 689 of file compute_unit.cc.

References barrierSlot().

Referenced by gem5::VegaISA::Inst_SOPP__S_BARRIER::execute().

◆ oprNetPipeLength()

int gem5::ComputeUnit::oprNetPipeLength ( ) const
inline

Definition at line 394 of file compute_unit.hh.

References operandNetworkLength.

◆ processFetchReturn()

void gem5::ComputeUnit::processFetchReturn ( PacketPtr pkt)

◆ processTimingPacket()

bool gem5::ComputeUnit::processTimingPacket ( PacketPtr pkt)

◆ releaseBarrier()

void gem5::ComputeUnit::releaseBarrier ( int bar_id)

Definition at line 738 of file compute_unit.cc.

References barrierSlot(), and freeBarrierIds.

Referenced by gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute().

◆ releaseWFsFromBarrier()

void gem5::ComputeUnit::releaseWFsFromBarrier ( int bar_id)

Definition at line 746 of file compute_unit.cc.

References gem5::Wavefront::barrierId(), gem5::Wavefront::getStatus(), gem5::ArmISA::i, gem5::Shader::n_wf, numVectorALUs, gem5::Wavefront::S_BARRIER, gem5::Wavefront::S_RUNNING, gem5::Wavefront::setStatus(), shader, and wfList.

Referenced by gem5::ScoreboardCheckStage::ready().

◆ requestorId()

RequestorID gem5::ComputeUnit::requestorId ( )
inline

Definition at line 469 of file compute_unit.hh.

References _requestorId.

Referenced by gem5::FetchUnit::initiateFetch(), gem5::ScalarMemPipeline::injectScalarMemFence(), and vramRequestorId().

◆ resetBarrier()

void gem5::ComputeUnit::resetBarrier ( int bar_id)

Definition at line 724 of file compute_unit.cc.

References barrierSlot().

Referenced by gem5::ScoreboardCheckStage::ready().

◆ resetRegisterPool()

void gem5::ComputeUnit::resetRegisterPool ( )

Definition at line 452 of file compute_unit.cc.

References gem5::ArmISA::i, numScalarRegsPerSimd, numVecRegsPerSimd, numVectorALUs, registerManager, gem5::RegisterManager::srfPoolMgrs, and gem5::RegisterManager::vrfPoolMgrs.

◆ rfcLength()

int gem5::ComputeUnit::rfcLength ( ) const
inline

Definition at line 398 of file compute_unit.hh.

References rfcPipeLength.

Referenced by gem5::RegisterFileCache::waveExecuteInst().

◆ scalarPipeLength()

int gem5::ComputeUnit::scalarPipeLength ( ) const
inline

Definition at line 399 of file compute_unit.hh.

References scalarPipeStages.

Referenced by gem5::ScalarRegisterFile::waveExecuteInst().

◆ sendInvL2()

void gem5::ComputeUnit::sendInvL2 ( Addr paddr)

Definition at line 1437 of file compute_unit.cc.

References gem5::curTick(), gem5::Request::GL2_CACHE_INV, gem5::Shader::incNumOutstandingInvL2s(), memPort, gem5::MemCmd::MemSyncReq, req_tick_latency, gem5::EventManager::schedule(), shader, and vramRequestorId().

◆ sendRequest()

void gem5::ComputeUnit::sendRequest ( GPUDynInstPtr gpuDynInst,
PortID index,
PacketPtr pkt )

Definition at line 1127 of file compute_unit.cc.

References gem5::Packet::cmd, cu_id, gem5::curTick(), gem5::Packet::dataStatic(), debugSegFault, DPRINTF, gem5::GPUCommandProcessor::driver(), fatal, gem5::FullSystem, functionalTLB, gem5::Packet::getAddr(), gem5::ThreadContext::getProcessPtr(), gem5::Packet::getPtr(), gem5::Packet::getSize(), gem5::Shader::gpuCmdProc, gem5::Shader::gpuTc, gem5::GpuTranslationState::hitLevel, gem5::ComputeUnit::ComputeUnitStats::hitsPerTLBLevel, gem5::MipsISA::index, gem5::Packet::isRead(), gem5::Packet::isWrite(), memPort, gem5::MemCmd::MemSyncReq, gem5::MipsISA::p, panic, perLaneTLB, gem5::BaseMMU::Read, gem5::Packet::req, req_tick_latency, gem5::safe_cast(), gem5::GpuTranslationState::saved, gem5::EventManager::schedule(), gem5::Packet::senderState, gem5::GPUComputeDriver::setMtype(), shader, stats, gem5::Shader::timingSim, gem5::ComputeUnit::ComputeUnitStats::tlbCycles, gem5::GpuTranslationState::tlbEntry, tlbPort, gem5::ComputeUnit::ComputeUnitStats::tlbRequests, updatePageDivergenceDist(), gem5::MipsISA::vaddr, and gem5::BaseMMU::Write.

◆ sendScalarRequest()

void gem5::ComputeUnit::sendScalarRequest ( GPUDynInstPtr gpuDynInst,
PacketPtr pkt )

Definition at line 1328 of file compute_unit.cc.

References DPRINTF, gem5::Shader::gpuTc, gem5::Packet::isRead(), gem5::ComputeUnit::ScalarDTLBPort::isStalled(), gem5::Packet::isWrite(), gem5::BaseMMU::Read, gem5::Packet::req, gem5::ComputeUnit::ScalarDTLBPort::retries, scalarDTLBPort, gem5::Packet::senderState, gem5::RequestPort::sendTimingReq(), shader, gem5::ComputeUnit::ScalarDTLBPort::stallPort(), and gem5::BaseMMU::Write.

◆ sendToLds()

bool gem5::ComputeUnit::sendToLds ( GPUDynInstPtr gpuDynInst)
nodiscard

send a general request to the LDS make sure to look at the return value here as your request might be NACK'd and returning false means that you have to have some backup plan

Definition at line 2187 of file compute_unit.cc.

References ldsPort, gem5::MemCmd::ReadReq, gem5::Packet::senderState, and gem5::ComputeUnit::LDSPort::sendTimingReq().

Referenced by gem5::LocalMemPipeline::exec().

◆ simdUnitWidth()

int gem5::ComputeUnit::simdUnitWidth ( ) const
inline

Definition at line 395 of file compute_unit.hh.

References simdWidth.

◆ spBypassLength()

int gem5::ComputeUnit::spBypassLength ( ) const
inline

Definition at line 396 of file compute_unit.hh.

References spBypassPipeLength.

◆ startWavefront()

void gem5::ComputeUnit::startWavefront ( Wavefront * w,
int waveId,
LdsChunk * ldsChunk,
HSAQueueEntry * task,
int bar_id,
bool fetchContext = false )

Definition at line 324 of file compute_unit.cc.

References activeWaves, gem5::HSAQueueEntry::codeAddr(), cu_id, gem5::HSAQueueEntry::dispatchId(), DPRINTF, gem5::HSAQueueEntry::globalWgId(), gem5::LdsState::increaseRefCounter(), gem5::WFBarrier::InvalidID, gem5::MipsISA::k, lds, gem5::HSAQueueEntry::numWg(), panic_if, gem5::statistics::DistBase< Derived, Stor >::sample(), stats, gem5::MipsISA::w, gem5::ComputeUnit::ComputeUnitStats::waveLevelParallelism, and wfSize().

Referenced by dispWorkgroup().

◆ storeBusLength()

int gem5::ComputeUnit::storeBusLength ( ) const
inline

Definition at line 400 of file compute_unit.hh.

References numCyclesPerStoreTransfer.

Referenced by gem5::LdsState::processPacket().

◆ updateInstStats()

void gem5::ComputeUnit::updateInstStats ( GPUDynInstPtr gpuDynInst)

this case can occur for flat mem insts who execute with EXEC = 0

this case can occur for flat mem insts who execute with EXEC = 0

Definition at line 1993 of file compute_unit.cc.

References gem5::ComputeUnit::ComputeUnitStats::argReads, gem5::ComputeUnit::ComputeUnitStats::argWrites, gem5::exitSimLoop(), fatal, gem5::ComputeUnit::ComputeUnitStats::flatLDSInsts, gem5::ComputeUnit::ComputeUnitStats::flatVMemInsts, gem5::ComputeUnit::ComputeUnitStats::globalReads, gem5::ComputeUnit::ComputeUnitStats::globalWrites, gem5::ComputeUnit::ComputeUnitStats::groupReads, gem5::ComputeUnit::ComputeUnitStats::groupWrites, gem5::ComputeUnit::ComputeUnitStats::instCyclesSALU, gem5::ComputeUnit::ComputeUnitStats::instCyclesVALU, gem5::ComputeUnit::ComputeUnitStats::kernargReads, gem5::ComputeUnit::ComputeUnitStats::kernargWrites, gem5::ComputeUnit::ComputeUnitStats::ldsNoFlatInsts, gem5::Shader::max_valu_insts, gem5::ComputeUnit::ComputeUnitStats::privReads, gem5::ComputeUnit::ComputeUnitStats::privWrites, gem5::ComputeUnit::ComputeUnitStats::readonlyReads, gem5::ComputeUnit::ComputeUnitStats::readonlyWrites, gem5::ComputeUnit::ComputeUnitStats::sALUInsts, gem5::ComputeUnit::ComputeUnitStats::scalarMemReads, gem5::ComputeUnit::ComputeUnitStats::scalarMemWrites, shader, gem5::ComputeUnit::ComputeUnitStats::spillReads, gem5::ComputeUnit::ComputeUnitStats::spillWrites, stats, gem5::ComputeUnit::ComputeUnitStats::threadCyclesVALU, gem5::Shader::total_valu_insts, gem5::ComputeUnit::ComputeUnitStats::vALUInsts, gem5::ComputeUnit::ComputeUnitStats::vectorMemReads, and gem5::ComputeUnit::ComputeUnitStats::vectorMemWrites.

Referenced by gem5::Wavefront::exec().

◆ updatePageDivergenceDist()

void gem5::ComputeUnit::updatePageDivergenceDist ( Addr addr)

Definition at line 2103 of file compute_unit.cc.

References gem5::X86ISA::addr, gem5::X86ISA::PageBytes, pagesTouched, and gem5::roundDown().

Referenced by sendRequest().

◆ vramRequestorId()

RequestorID gem5::ComputeUnit::vramRequestorId ( )

Forward the VRAM requestor ID needed for device memory from shader.

Definition at line 2207 of file compute_unit.cc.

References gem5::FullSystem, requestorId(), shader, and gem5::Shader::vramRequestorId().

Referenced by gem5::FetchUnit::fetch(), gem5::FetchUnit::initiateFetch(), injectGlobalMemFence(), and sendInvL2().

◆ wfSize()

int gem5::ComputeUnit::wfSize ( ) const
inline

Definition at line 402 of file compute_unit.hh.

References wavefrontSize.

Referenced by gem5::ComputeUnit::ComputeUnitStats::ComputeUnitStats(), gem5::LdsState::countBankConflicts(), gem5::GPUDynInst::doApertureCheck(), gem5::GPUDynInst::GPUDynInst(), hasDispResources(), gem5::Wavefront::initRegState(), gem5::GPUDynInst::resolveFlatSegment(), and startWavefront().

Member Data Documentation

◆ _cacheLineSize

const int gem5::ComputeUnit::_cacheLineSize
private

Definition at line 970 of file compute_unit.hh.

Referenced by cacheLineSize().

◆ _numBarrierSlots

const int gem5::ComputeUnit::_numBarrierSlots
private

Definition at line 971 of file compute_unit.hh.

Referenced by numBarrierSlots().

◆ _requestorId

RequestorID gem5::ComputeUnit::_requestorId
protected

Definition at line 480 of file compute_unit.hh.

Referenced by requestorId().

◆ activeWaves

int gem5::ComputeUnit::activeWaves

Definition at line 1027 of file compute_unit.hh.

Referenced by gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), and startWavefront().

◆ cacheLineBits

int gem5::ComputeUnit::cacheLineBits
private

Definition at line 972 of file compute_unit.hh.

Referenced by getCacheLineBits().

◆ coalescerToVrfBusWidth

int gem5::ComputeUnit::coalescerToVrfBusWidth

Definition at line 270 of file compute_unit.hh.

◆ countPages

bool gem5::ComputeUnit::countPages

Definition at line 356 of file compute_unit.hh.

Referenced by exitCallback().

◆ cu_id

int gem5::ComputeUnit::cu_id

Definition at line 293 of file compute_unit.hh.

Referenced by gem5::GPUDynInst::completeAcc(), dispWorkgroup(), exec(), gem5::GlobalMemPipeline::exec(), gem5::ScalarMemPipeline::exec(), gem5::Wavefront::exec(), gem5::VegaISA::Inst_SOPP__S_BARRIER::execute(), gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), gem5::FetchUnit::fetch(), gem5::GPUDynInst::GPUDynInst(), gem5::GPUDynInst::initiateAcc(), gem5::FetchUnit::initiateFetch(), gem5::Wavefront::initRegState(), injectGlobalMemFence(), gem5::GPUDispatcher::notifyWgCompl(), gem5::ComputeUnit::ScalarDataPort::MemReqEvent::process(), gem5::FetchUnit::processFetchReturn(), gem5::ComputeUnit::DataPort::processMemReqEvent(), gem5::ComputeUnit::DataPort::processMemRespEvent(), gem5::ScoreboardCheckStage::ready(), sendRequest(), gem5::Wavefront::setStatus(), and startWavefront().

◆ debugSegFault

bool gem5::ComputeUnit::debugSegFault

Definition at line 346 of file compute_unit.hh.

Referenced by sendRequest().

◆ dpBypassPipeLength

int gem5::ComputeUnit::dpBypassPipeLength

Definition at line 310 of file compute_unit.hh.

Referenced by dpBypassLength().

◆ exec_policy

EXEC_POLICY gem5::ComputeUnit::exec_policy

Definition at line 344 of file compute_unit.hh.

◆ execStage

ExecStage gem5::ComputeUnit::execStage

Definition at line 284 of file compute_unit.hh.

Referenced by exec(), and init().

◆ fetchStage

FetchStage gem5::ComputeUnit::fetchStage

Definition at line 281 of file compute_unit.hh.

Referenced by gem5::Wavefront::discardFetch(), exec(), gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), handleSQCReturn(), and init().

◆ freeBarrierIds

std::unordered_set<int> gem5::ComputeUnit::freeBarrierIds
private

A set used to easily retrieve a free barrier ID.

Definition at line 1018 of file compute_unit.hh.

Referenced by getFreeBarrierId(), hasDispResources(), and releaseBarrier().

◆ functionalTLB

bool gem5::ComputeUnit::functionalTLB

Definition at line 350 of file compute_unit.hh.

Referenced by sendRequest().

◆ glbMemToVrfBus

WaitClass gem5::ComputeUnit::glbMemToVrfBus

Definition at line 222 of file compute_unit.hh.

Referenced by gem5::GlobalMemPipeline::exec(), init(), and isDone().

◆ globalMemoryPipe

GlobalMemPipeline gem5::ComputeUnit::globalMemoryPipe

Definition at line 285 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::dispatchReady(), exec(), gem5::ScheduleStage::fillDispatchList(), init(), isDone(), and gem5::ComputeUnit::DataPort::processMemRespEvent().

◆ globalSeqNum

InstSeqNum gem5::ComputeUnit::globalSeqNum
private

Definition at line 973 of file compute_unit.hh.

Referenced by getAndIncSeqNum().

◆ gmTokenPort

GMTokenPort gem5::ComputeUnit::gmTokenPort

Definition at line 519 of file compute_unit.hh.

Referenced by getPort(), and init().

◆ headTailMap

std::unordered_map<GPUDynInstPtr, Tick> gem5::ComputeUnit::headTailMap
private

Definition at line 1023 of file compute_unit.hh.

Referenced by gem5::ComputeUnit::DataPort::processMemRespEvent().

◆ idleCUTimeout

Tick gem5::ComputeUnit::idleCUTimeout

Definition at line 348 of file compute_unit.hh.

Referenced by gem5::Wavefront::setStatus().

◆ idleWfs

int gem5::ComputeUnit::idleWfs

Definition at line 349 of file compute_unit.hh.

Referenced by gem5::Wavefront::setStatus().

◆ instExecPerSimd

std::vector<uint64_t> gem5::ComputeUnit::instExecPerSimd

Definition at line 331 of file compute_unit.hh.

Referenced by gem5::Wavefront::exec().

◆ issuePeriod

Cycles gem5::ComputeUnit::issuePeriod

Definition at line 318 of file compute_unit.hh.

Referenced by gem5::Wavefront::exec().

◆ lastExecCycle

std::vector<uint64_t> gem5::ComputeUnit::lastExecCycle

Definition at line 328 of file compute_unit.hh.

Referenced by gem5::Wavefront::exec().

◆ lastVaddrCU

std::vector<Addr> gem5::ComputeUnit::lastVaddrCU

Definition at line 340 of file compute_unit.hh.

Referenced by ~ComputeUnit().

◆ lastVaddrSimd

std::vector<std::vector<Addr> > gem5::ComputeUnit::lastVaddrSimd

Definition at line 341 of file compute_unit.hh.

Referenced by ~ComputeUnit().

◆ lastVaddrWF

std::vector<std::vector<std::vector<Addr> > > gem5::ComputeUnit::lastVaddrWF

Definition at line 342 of file compute_unit.hh.

◆ lds

LdsState& gem5::ComputeUnit::lds
protected

Definition at line 482 of file compute_unit.hh.

Referenced by dispWorkgroup(), getLds(), getRefCounter(), hasDispResources(), and startWavefront().

◆ ldsPort

LDSPort gem5::ComputeUnit::ldsPort

The port to access the Local Data Store Can be connected to a LDS object.

Definition at line 920 of file compute_unit.hh.

Referenced by getPort(), and sendToLds().

◆ localMemBarrier

bool gem5::ComputeUnit::localMemBarrier

Definition at line 351 of file compute_unit.hh.

◆ localMemoryPipe

LocalMemPipeline gem5::ComputeUnit::localMemoryPipe

Definition at line 286 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::dispatchReady(), exec(), and isDone().

◆ locMemToVrfBus

WaitClass gem5::ComputeUnit::locMemToVrfBus

Definition at line 230 of file compute_unit.hh.

Referenced by gem5::LocalMemPipeline::exec(), init(), and isDone().

◆ memPort

std::vector<DataPort> gem5::ComputeUnit::memPort

The memory port for SIMD data accesses.

Can be connected to PhysMem for Ruby for timing simulations

Definition at line 931 of file compute_unit.hh.

Referenced by getPort(), injectGlobalMemFence(), sendInvL2(), and sendRequest().

◆ memPortTokens

TokenManager* gem5::ComputeUnit::memPortTokens

Definition at line 518 of file compute_unit.hh.

Referenced by getTokenManager(), and init().

◆ numCyclesPerLoadTransfer

int gem5::ComputeUnit::numCyclesPerLoadTransfer

Definition at line 272 of file compute_unit.hh.

Referenced by loadBusLength().

◆ numCyclesPerStoreTransfer

int gem5::ComputeUnit::numCyclesPerStoreTransfer

Definition at line 271 of file compute_unit.hh.

Referenced by storeBusLength().

◆ numScalarALUs

int gem5::ComputeUnit::numScalarALUs

Definition at line 249 of file compute_unit.hh.

Referenced by gem5::ExecStage::ExecStageStats::ExecStageStats(), firstMemUnit(), init(), mapWaveToGlobalMem(), mapWaveToLocalMem(), mapWaveToScalarAlu(), mapWaveToScalarMem(), and numExeUnits().

◆ numScalarMemUnits

int gem5::ComputeUnit::numScalarMemUnits

Definition at line 236 of file compute_unit.hh.

Referenced by init(), and numExeUnits().

◆ numScalarRegsPerSimd

int gem5::ComputeUnit::numScalarRegsPerSimd

Definition at line 380 of file compute_unit.hh.

Referenced by gem5::StaticRegisterManagerPolicy::allocateRegisters(), hasDispResources(), and resetRegisterPool().

◆ numVecRegsPerSimd

int gem5::ComputeUnit::numVecRegsPerSimd

Definition at line 378 of file compute_unit.hh.

Referenced by gem5::StaticRegisterManagerPolicy::allocateRegisters(), hasDispResources(), and resetRegisterPool().

◆ numVectorALUs

int gem5::ComputeUnit::numVectorALUs

Definition at line 245 of file compute_unit.hh.

Referenced by gem5::ComputeUnit::ComputeUnitStats::ComputeUnitStats(), dispWorkgroup(), gem5::ScoreboardCheckStage::exec(), gem5::ExecStage::ExecStageStats::ExecStageStats(), firstMemUnit(), hasDispResources(), init(), isDone(), isVectorAluIdle(), mapWaveToGlobalMem(), mapWaveToLocalMem(), mapWaveToScalarAluGlobalIdx(), mapWaveToScalarMem(), numExeUnits(), releaseWFsFromBarrier(), resetRegisterPool(), gem5::Wavefront::setStatus(), and ~ComputeUnit().

◆ numVectorGlobalMemUnits

int gem5::ComputeUnit::numVectorGlobalMemUnits

Definition at line 220 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::arbitrateVrfToLdsBus(), init(), gem5::ScheduleStage::init(), mapWaveToLocalMem(), mapWaveToScalarMem(), and numExeUnits().

◆ numVectorSharedMemUnits

int gem5::ComputeUnit::numVectorSharedMemUnits

Definition at line 228 of file compute_unit.hh.

Referenced by init(), gem5::ScheduleStage::init(), mapWaveToScalarMem(), and numExeUnits().

◆ numWfsToSched

std::vector<int> gem5::ComputeUnit::numWfsToSched

Number of WFs to schedule to each SIMD.

This vector is populated by hasDispResources(), and consumed by the subsequent call to dispWorkgroup(), to schedule the specified number of WFs to the SIMD units. Entry I provides the number of WFs to schedule to SIMD I.

Definition at line 371 of file compute_unit.hh.

Referenced by dispWorkgroup(), and hasDispResources().

◆ operandNetworkLength

int gem5::ComputeUnit::operandNetworkLength

Definition at line 316 of file compute_unit.hh.

Referenced by oprNetPipeLength().

◆ pageAccesses

pageDataStruct gem5::ComputeUnit::pageAccesses

Definition at line 497 of file compute_unit.hh.

Referenced by exitCallback(), and gem5::GPUDynInst::updateStats().

◆ pagesTouched

std::map<Addr, int> gem5::ComputeUnit::pagesTouched

Definition at line 385 of file compute_unit.hh.

Referenced by updatePageDivergenceDist(), and gem5::GPUDynInst::updateStats().

◆ perLaneTLB

bool gem5::ComputeUnit::perLaneTLB

Definition at line 334 of file compute_unit.hh.

Referenced by sendRequest().

◆ pipeMap

std::unordered_set<uint64_t> gem5::ComputeUnit::pipeMap

Definition at line 277 of file compute_unit.hh.

Referenced by deleteFromPipeMap(), insertInPipeMap(), and gem5::Wavefront::nextInstr().

◆ prefetchDepth

int gem5::ComputeUnit::prefetchDepth

Definition at line 336 of file compute_unit.hh.

◆ prefetchStride

int gem5::ComputeUnit::prefetchStride

Definition at line 338 of file compute_unit.hh.

◆ prefetchType

enums::PrefetchType gem5::ComputeUnit::prefetchType

Definition at line 343 of file compute_unit.hh.

◆ registerManager

RegisterManager* gem5::ComputeUnit::registerManager

Definition at line 279 of file compute_unit.hh.

Referenced by gem5::StaticRegisterManagerPolicy::allocateRegisters(), gem5::StaticRegisterManagerPolicy::canAllocateSgprs(), gem5::StaticRegisterManagerPolicy::canAllocateVgprs(), dispWorkgroup(), gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), gem5::Wavefront::freeRegisterFile(), gem5::GPUStaticInst::generateVirtToPhysMap(), hasDispResources(), gem5::Wavefront::initRegState(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::read(), gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::regIdx(), resetRegisterPool(), gem5::GPUDynInst::resolveFlatSegment(), and gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::write().

◆ req_tick_latency

Tick gem5::ComputeUnit::req_tick_latency

Definition at line 360 of file compute_unit.hh.

Referenced by injectGlobalMemFence(), sendInvL2(), and sendRequest().

◆ resp_tick_latency

Tick gem5::ComputeUnit::resp_tick_latency

Definition at line 361 of file compute_unit.hh.

◆ rfc

std::vector<RegisterFileCache*> gem5::ComputeUnit::rfc

Definition at line 300 of file compute_unit.hh.

Referenced by gem5::Wavefront::exec(), gem5::VectorRegisterFile::operandsReady(), and gem5::VectorRegisterFile::waveExecuteInst().

◆ rfcPipeLength

int gem5::ComputeUnit::rfcPipeLength

Definition at line 312 of file compute_unit.hh.

Referenced by rfcLength().

◆ scalar_req_tick_latency

Tick gem5::ComputeUnit::scalar_req_tick_latency

Definition at line 362 of file compute_unit.hh.

Referenced by gem5::ScalarMemPipeline::injectScalarMemFence().

◆ scalar_resp_tick_latency

Tick gem5::ComputeUnit::scalar_resp_tick_latency

Definition at line 363 of file compute_unit.hh.

◆ scalarALUs

std::vector<WaitClass> gem5::ComputeUnit::scalarALUs

Definition at line 250 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::dispatchReady(), gem5::Wavefront::exec(), and init().

◆ scalarDataPort

ScalarDataPort gem5::ComputeUnit::scalarDataPort

Definition at line 935 of file compute_unit.hh.

Referenced by getPort(), gem5::ScalarMemPipeline::injectScalarMemFence(), and gem5::ComputeUnit::ScalarDataPort::MemReqEvent::process().

◆ scalarDTLBPort

ScalarDTLBPort gem5::ComputeUnit::scalarDTLBPort

Definition at line 937 of file compute_unit.hh.

Referenced by getPort(), and sendScalarRequest().

◆ scalarMemoryPipe

ScalarMemPipeline gem5::ComputeUnit::scalarMemoryPipe

Definition at line 287 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::dispatchReady(), doSQCInvalidate(), and exec().

◆ scalarMemToSrfBus

WaitClass gem5::ComputeUnit::scalarMemToSrfBus

Definition at line 238 of file compute_unit.hh.

Referenced by gem5::ScalarMemPipeline::exec(), init(), and isDone().

◆ scalarMemUnit

WaitClass gem5::ComputeUnit::scalarMemUnit

Definition at line 242 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::checkMemResources(), gem5::ScalarMemPipeline::exec(), gem5::Wavefront::exec(), and init().

◆ scalarPipeStages

int gem5::ComputeUnit::scalarPipeStages

Definition at line 314 of file compute_unit.hh.

Referenced by scalarPipeLength().

◆ scalarRegsReserved

std::vector<int> gem5::ComputeUnit::scalarRegsReserved

Definition at line 376 of file compute_unit.hh.

Referenced by gem5::StaticRegisterManagerPolicy::allocateRegisters(), and init().

◆ scheduleStage

ScheduleStage gem5::ComputeUnit::scheduleStage

Definition at line 283 of file compute_unit.hh.

Referenced by exec(), gem5::ExecStage::exec(), and init().

◆ scheduleToExecute

ScheduleToExecute gem5::ComputeUnit::scheduleToExecute
private

Definition at line 1009 of file compute_unit.hh.

◆ scoreboardCheckStage

ScoreboardCheckStage gem5::ComputeUnit::scoreboardCheckStage

Definition at line 282 of file compute_unit.hh.

Referenced by exec().

◆ scoreboardCheckToSchedule

ScoreboardCheckToSchedule gem5::ComputeUnit::scoreboardCheckToSchedule
private

TODO: Update these comments once the pipe stage interface has been fully refactored.

Pipeline stage interfaces.

Buffers used to communicate between various pipeline stages List of waves which will be dispatched to each execution resource. An EXREADY implies dispatch list is non-empty and execution unit has something to execute this cycle. Currently, the dispatch list of an execution resource can hold only one wave because an execution resource can execute only one wave in a cycle. dispatchList is used to communicate between schedule and exec stage

At a high level, the following intra-/inter-stage communication occurs: SCB to SCH: readyList provides per exec resource list of waves that passed dependency and readiness checks. If selected by scheduler, attempt to add wave to schList conditional on RF support. SCH: schList holds waves that are gathering operands or waiting for execution resource availability. Once ready, waves are placed on the dispatchList as candidates for execution. A wave may spend multiple cycles in SCH stage, on the schList due to RF access conflicts or execution resource contention. SCH to EX: dispatchList holds waves that are ready to be executed. LM/FLAT arbitration may remove an LM wave and place it back on the schList. RF model may also force a wave back to the schList if using the detailed model.

Definition at line 1008 of file compute_unit.hh.

◆ shader

Shader* gem5::ComputeUnit::shader

Definition at line 358 of file compute_unit.hh.

Referenced by dispWorkgroup(), gem5::GPUDynInst::doApertureCheck(), exec(), gem5::FetchUnit::exec(), gem5::GlobalMemPipeline::exec(), gem5::LocalMemPipeline::exec(), gem5::ScalarMemPipeline::exec(), gem5::ScoreboardCheckStage::exec(), gem5::Wavefront::exec(), gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), gem5::FetchUnit::fetch(), gem5::ComputeUnit::DataPort::handleResponse(), hasDispResources(), gem5::FetchUnit::init(), gem5::GlobalMemPipeline::init(), gem5::FetchUnit::initiateFetch(), gem5::Wavefront::initRegState(), injectGlobalMemFence(), isVectorAluIdle(), gem5::ComputeUnit::ScalarDataPort::MemReqEvent::process(), gem5::ComputeUnit::DataPort::processMemReqEvent(), gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::readSpecialVal(), releaseWFsFromBarrier(), gem5::GPUDynInst::resolveFlatSegment(), sendInvL2(), sendRequest(), sendScalarRequest(), gem5::Wavefront::setStatus(), updateInstStats(), vramRequestorId(), and ~ComputeUnit().

◆ simdWidth

int gem5::ComputeUnit::simdWidth

Definition at line 304 of file compute_unit.hh.

Referenced by simdUnitWidth().

◆ spBypassPipeLength

int gem5::ComputeUnit::spBypassPipeLength

Definition at line 307 of file compute_unit.hh.

Referenced by spBypassLength().

◆ sqcPort

SQCPort gem5::ComputeUnit::sqcPort

Definition at line 939 of file compute_unit.hh.

Referenced by gem5::FetchUnit::fetch(), getPort(), gem5::ScalarMemPipeline::injectScalarMemFence(), and gem5::ComputeUnit::SQCPort::MemReqEvent::process().

◆ sqcTLBPort

ITLBPort gem5::ComputeUnit::sqcTLBPort

Definition at line 941 of file compute_unit.hh.

Referenced by getPort(), and gem5::FetchUnit::initiateFetch().

◆ srf

std::vector<ScalarRegisterFile*> gem5::ComputeUnit::srf

Definition at line 298 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::addToSchList(), gem5::ScheduleStage::checkRfOperandReadComplete(), exec(), gem5::ScalarMemPipeline::exec(), gem5::Wavefront::exec(), gem5::Wavefront::initRegState(), gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::read(), gem5::ScoreboardCheckStage::ready(), gem5::ScheduleStage::reserveResources(), gem5::GPUDynInst::resolveFlatSegment(), gem5::ScheduleStage::schedRfWrites(), gem5::RegisterManager::setParent(), and gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::write().

◆ srf_scm_bus_latency

Cycles gem5::ComputeUnit::srf_scm_bus_latency

Definition at line 323 of file compute_unit.hh.

Referenced by gem5::Wavefront::exec().

◆ srfToScalarMemPipeBus

WaitClass gem5::ComputeUnit::srfToScalarMemPipeBus

Definition at line 240 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::checkMemResources(), gem5::Wavefront::exec(), init(), and isDone().

◆ stats

gem5::ComputeUnit::ComputeUnitStats gem5::ComputeUnit::stats

Referenced by exec(), gem5::Wavefront::exec(), gem5::AtomicOpCAS< T >::execute(), gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), hasDispResources(), gem5::ComputeUnit::DataPort::processMemRespEvent(), gem5::LdsState::processPacket(), sendRequest(), startWavefront(), updateInstStats(), and gem5::GPUDynInst::updateStats().

◆ tickEvent

EventFunctionWrapper gem5::ComputeUnit::tickEvent

Definition at line 289 of file compute_unit.hh.

Referenced by dispWorkgroup(), and exec().

◆ tlbPort

std::vector<DTLBPort> gem5::ComputeUnit::tlbPort

Definition at line 933 of file compute_unit.hh.

Referenced by getPort(), and sendRequest().

◆ vectorALUs

std::vector<WaitClass> gem5::ComputeUnit::vectorALUs

Definition at line 246 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::dispatchReady(), gem5::Wavefront::exec(), and init().

◆ vectorGlobalMemUnit

WaitClass gem5::ComputeUnit::vectorGlobalMemUnit

Definition at line 226 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::checkMemResources(), gem5::GlobalMemPipeline::exec(), gem5::Wavefront::exec(), and init().

◆ vectorRegsReserved

std::vector<int> gem5::ComputeUnit::vectorRegsReserved

Definition at line 374 of file compute_unit.hh.

Referenced by gem5::StaticRegisterManagerPolicy::allocateRegisters(), and init().

◆ vectorSharedMemUnit

WaitClass gem5::ComputeUnit::vectorSharedMemUnit

Definition at line 234 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::checkMemResources(), gem5::LocalMemPipeline::exec(), gem5::Wavefront::exec(), and init().

◆ vrf

std::vector<VectorRegisterFile*> gem5::ComputeUnit::vrf

Definition at line 296 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::addToSchList(), gem5::ScheduleStage::checkRfOperandReadComplete(), exec(), gem5::GlobalMemPipeline::exec(), gem5::LocalMemPipeline::exec(), gem5::Wavefront::exec(), gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_SWIZZLE_B32::execute(), gem5::Wavefront::freeRegisterFile(), gem5::Wavefront::initRegState(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::read(), gem5::ScoreboardCheckStage::ready(), gem5::ScheduleStage::reserveResources(), gem5::ScheduleStage::schedRfWrites(), gem5::RegisterManager::setParent(), and gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::write().

◆ vrf_gm_bus_latency

Cycles gem5::ComputeUnit::vrf_gm_bus_latency

Definition at line 321 of file compute_unit.hh.

Referenced by gem5::Wavefront::exec().

◆ vrf_lm_bus_latency

Cycles gem5::ComputeUnit::vrf_lm_bus_latency

Definition at line 325 of file compute_unit.hh.

Referenced by gem5::Wavefront::exec().

◆ vrfToCoalescerBusWidth

int gem5::ComputeUnit::vrfToCoalescerBusWidth

Definition at line 269 of file compute_unit.hh.

◆ vrfToGlobalMemPipeBus

WaitClass gem5::ComputeUnit::vrfToGlobalMemPipeBus

Definition at line 224 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::checkMemResources(), gem5::Wavefront::exec(), init(), and isDone().

◆ vrfToLocalMemPipeBus

WaitClass gem5::ComputeUnit::vrfToLocalMemPipeBus

Definition at line 232 of file compute_unit.hh.

Referenced by gem5::ScheduleStage::checkMemResources(), gem5::Wavefront::exec(), init(), and isDone().

◆ wavefrontSize

int gem5::ComputeUnit::wavefrontSize
private

Definition at line 974 of file compute_unit.hh.

Referenced by wfSize().

◆ wfBarrierSlots

std::vector<WFBarrier> gem5::ComputeUnit::wfBarrierSlots
private

The barrier slots for this CU.

Definition at line 1014 of file compute_unit.hh.

Referenced by barrierSlot().

◆ wfList

std::vector<std::vector<Wavefront*> > gem5::ComputeUnit::wfList

Definition at line 292 of file compute_unit.hh.

Referenced by dispWorkgroup(), gem5::ScoreboardCheckStage::exec(), hasDispResources(), gem5::FetchStage::init(), isVectorAluIdle(), releaseWFsFromBarrier(), and ~ComputeUnit().

The documentation for this class was generated from the following files:
Generated on Tue Jun 18 2024 16:24:10 for gem5 by doxygen 1.11.0