Public Member Functions | |
| Registers (const std::string &, Iris::BaseCPU *, CorePins *) | |
 Public Member Functions inherited from gem5::RegisterBank< ByteOrder::little > | |
| constexpr | RegisterBank (const std::string &new_name, Addr new_base) |
| virtual | ~RegisterBank () |
| void | addRegisters (std::initializer_list< std::reference_wrapper< RegisterBase >> regs) |
| void | addRegister (RegisterBase ®) |
| Addr | base () const |
| Addr | size () const |
| const std::string & | name () const |
| virtual void | read (Addr addr, void *buf, Addr bytes) |
| virtual void | write (Addr addr, const void *buf, Addr bytes) |
Private Attributes | |
| Iris::BaseCPU * | cpu |
| CorePins * | pins |
| Register64 | nsrvbar |
| Register64 | rvbar |
| Register32 | reset |
| Register32 | halt |
Additional Inherited Members | |
| Public Types inherited from gem5::RegisterBank< ByteOrder::little > | |
| using | Register8 = Register< uint8_t > |
| using | Register8LE = Register< uint8_t, ByteOrder::little > |
| using | Register8BE = Register< uint8_t, ByteOrder::big > |
| using | Register16 = Register< uint16_t > |
| using | Register16LE = Register< uint16_t, ByteOrder::little > |
| using | Register16BE = Register< uint16_t, ByteOrder::big > |
| using | Register32 = Register< uint32_t > |
| using | Register32LE = Register< uint32_t, ByteOrder::little > |
| using | Register32BE = Register< uint32_t, ByteOrder::big > |
| using | Register64 = Register< uint64_t > |
| using | Register64LE = Register< uint64_t, ByteOrder::little > |
| using | Register64BE = Register< uint64_t, ByteOrder::big > |
| Static Public Member Functions inherited from gem5::RegisterBank< ByteOrder::little > | |
| static constexpr Data | readWithMask (const Data &value, const Data &bitmask) |
| static constexpr Data | writeWithMask (const Data &old, const Data &value, const Data &bitmask) |
Detailed Description
Definition at line 58 of file example.hh.
Constructor & Destructor Documentation
◆ Registers()
| gem5::fastmodel::ResetControllerExample::Registers::Registers | ( | const std::string & | module_name, |
| Iris::BaseCPU * | c, | ||
| CorePins * | p | ||
| ) |
Definition at line 44 of file example.cc.
References gem5::RegisterBank< ByteOrder::little >::addRegisters(), cpu, gem5::fastmodel::ResetControllerExample::CorePins::halt, halt, gem5::Port::isConnected(), gem5::IntSourcePinBase::lower(), gem5::Port::name(), nsrvbar, panic_if, pins, gem5::IntSourcePinBase::raise(), gem5::X86ISA::reg, gem5::fastmodel::ResetControllerExample::CorePins::reset, reset, rvbar, gem5::Iris::BaseCPU::setResetAddr(), and gem5::X86ISA::val.
Member Data Documentation
◆ cpu
|
private |
Definition at line 61 of file example.hh.
Referenced by Registers().
◆ halt
|
private |
Definition at line 67 of file example.hh.
Referenced by Registers().
◆ nsrvbar
|
private |
Definition at line 64 of file example.hh.
Referenced by Registers().
◆ pins
|
private |
Definition at line 62 of file example.hh.
Referenced by Registers().
◆ reset
|
private |
Definition at line 66 of file example.hh.
Referenced by Registers().
◆ rvbar
|
private |
Definition at line 65 of file example.hh.
Referenced by Registers().
The documentation for this class was generated from the following files:
- arch/arm/fastmodel/reset_controller/example.hh
- arch/arm/fastmodel/reset_controller/example.cc