gem5 v24.0.0.0
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example.cc
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1/*
2 * Copyright 2021 Google, Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
29
30#include <algorithm>
31
32#include "base/logging.hh"
33
34namespace gem5
35{
36namespace fastmodel
37{
38
39ResetControllerExample::CorePins::CorePins(const std::string &module_name)
40 : reset(module_name + ".reset"),
41 halt(module_name + ".halt")
42{}
43
45 const std::string &module_name, Iris::BaseCPU *c, CorePins *p)
46 : RegisterBankLE(module_name, 0), cpu(c), pins(p),
47 nsrvbar(module_name + ".nsrvbar"),
48 rvbar(module_name + ".rvbar"),
49 reset(module_name + ".reset"),
50 halt(module_name + ".halt")
51{
52 panic_if(cpu == nullptr, "ResetControllerExample needs a target cpu.");
53 nsrvbar.writer(
54 [this] (auto &reg, auto val)
55 {
56 cpu->setResetAddr(val, false);
57 });
58 rvbar.writer(
59 [this] (auto &reg, auto val)
60 {
61 cpu->setResetAddr(val, true);
62 });
63 reset.writer(
64 [this] (auto &reg, auto val)
65 {
67 "%s is not connected.", pins->reset.name());
68 pins->reset.set(val);
69 });
70 halt.writer(
71 [this] (auto &reg, auto val)
72 {
74 "%s is not connected.", pins->halt.name());
75 pins->halt.set(val);
76 });
77
79 nsrvbar,
80 rvbar,
81 reset,
82 halt,
83 });
84}
85
87 : BasicPioDevice(p, 0x20),
88 pins(p.name + ".pins"),
89 registers(p.name + ".registers", p.cpu, &pins)
90{}
91
92Tick
94{
95 pkt->makeResponse();
96 auto data = pkt->getPtr<uint8_t>();
97 auto size = pkt->getSize();
98 std::fill(data, data + size, 0);
99 return pioDelay;
100}
101
102Tick
104{
105 pkt->makeResponse();
106 size_t size = pkt->getSize();
107 if (size != 4 && size != 8) {
108 pkt->setBadAddress();
109 } else {
110 auto addr = pkt->getAddr() - pioAddr;
111 registers.write(addr, pkt->getPtr<void>(), size);
112 }
113 return pioDelay;
114}
115
116Port &
117ResetControllerExample::getPort(const std::string &if_name, PortID idx)
118{
119 if (if_name == "reset")
120 return pins.reset;
121 else if (if_name == "halt")
122 return pins.halt;
123
124 return BasicPioDevice::getPort(if_name, idx);
125}
126
127} // namespace fastmodel
128} // namespace gem5
const char data[]
Addr pioAddr
Address that the device listens to.
Definition io_device.hh:151
Tick pioDelay
Delay that the device experinces on an access.
Definition io_device.hh:157
virtual void setResetAddr(Addr addr, bool secure=false)
Definition cpu.hh:90
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
void setBadAddress()
Definition packet.hh:786
Addr getAddr() const
Definition packet.hh:807
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition packet.hh:1062
T * getPtr()
get a pointer to the data ptr.
Definition packet.hh:1225
unsigned getSize() const
Definition packet.hh:817
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition io_device.cc:67
Ports are used to interface objects to each other.
Definition port.hh:62
bool isConnected() const
Is this port currently connected to a peer?
Definition port.hh:133
const std::string name() const
Return port name (for DPRINTF).
Definition port.hh:111
void addRegisters(std::initializer_list< RegisterAdder > adders)
Definition reg_bank.hh:956
virtual void write(Addr addr, const void *buf, Addr bytes)
Definition reg_bank.hh:1075
void set(const State &new_state, const bool bypass_on_change=false)
Definition signal.hh:121
Registers(const std::string &, Iris::BaseCPU *, CorePins *)
Definition example.cc:44
Port & getPort(const std::string &, PortID=InvalidPortID) override
Get a port with a given name and index.
Definition example.cc:117
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition example.cc:103
FastModelResetControllerExampleParams Params
Definition example.hh:76
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition example.cc:93
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
Bitfield< 29 > c
Definition misc_types.hh:53
Bitfield< 0 > p
Bitfield< 5, 3 > reg
Definition types.hh:92
Bitfield< 63 > val
Definition misc.hh:804
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58

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