utility.hh File Reference

#include <cmath>
#include <cstdint>
#include <sstream>
#include <string>
#include "arch/riscv/regs/float.hh"
#include "arch/riscv/regs/int.hh"
#include "arch/riscv/regs/vector.hh"
#include "base/types.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "enums/RiscvType.hh"
#include "rvk.hh"

Go to the source code of this file.

Classes
struct	gem5::RiscvISA::double_width< uint8_t >
struct	gem5::RiscvISA::double_width< uint16_t >
struct	gem5::RiscvISA::double_width< uint32_t >
struct	gem5::RiscvISA::double_width< uint64_t >
struct	gem5::RiscvISA::double_width< int8_t >
struct	gem5::RiscvISA::double_width< int16_t >
struct	gem5::RiscvISA::double_width< int32_t >
struct	gem5::RiscvISA::double_width< int64_t >
struct	gem5::RiscvISA::double_width< float32_t >
struct	gem5::RiscvISA::double_width< float16_t >
struct	gem5::RiscvISA::double_width< float8_t >
struct	gem5::RiscvISA::double_widthf< uint32_t >
struct	gem5::RiscvISA::double_widthf< int32_t >
struct	gem5::RiscvISA::double_widthf< uint16_t >
struct	gem5::RiscvISA::double_widthf< int16_t >
struct	gem5::RiscvISA::double_widthf< uint8_t >
struct	gem5::RiscvISA::double_widthf< int8_t >

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::RiscvISA

Functions
template<typename T >
bool	gem5::RiscvISA::isquietnan (T val)
template<>
bool	gem5::RiscvISA::isquietnan< float > (float val)
template<>
bool	gem5::RiscvISA::isquietnan< double > (double val)
template<typename T >
bool	gem5::RiscvISA::issignalingnan (T val)
template<>
bool	gem5::RiscvISA::issignalingnan< float > (float val)
template<>
bool	gem5::RiscvISA::issignalingnan< double > (double val)
std::string	gem5::RiscvISA::registerName (RegId reg)
template<typename T >
std::make_unsigned_t< T >	gem5::RiscvISA::mulhu (std::make_unsigned_t< T > rs1, std::make_unsigned_t< T > rs2)
template<typename T >
std::make_signed_t< T >	gem5::RiscvISA::mulh (std::make_signed_t< T > rs1, std::make_signed_t< T > rs2)
template<typename T >
std::make_signed_t< T >	gem5::RiscvISA::mulhsu (std::make_signed_t< T > rs1, std::make_unsigned_t< T > rs2)
template<typename T >
T	gem5::RiscvISA::div (T rs1, T rs2)
template<typename T >
T	gem5::RiscvISA::divu (T rs1, T rs2)
template<typename T >
T	gem5::RiscvISA::rem (T rs1, T rs2)
template<typename T >
T	gem5::RiscvISA::remu (T rs1, T rs2)
uint64_t	gem5::RiscvISA::vtype_SEW (const uint64_t vtype)
uint64_t	gem5::RiscvISA::vtype_VLMAX (const uint64_t vtype, const uint64_t vlen, const bool per_reg=false)
int64_t	gem5::RiscvISA::vtype_vlmul (const uint64_t vtype)
uint64_t	gem5::RiscvISA::vtype_regs_per_group (const uint64_t vtype)
void	gem5::RiscvISA::vtype_set_vill (uint64_t &vtype)
uint64_t	gem5::RiscvISA::width_EEW (uint64_t width)
template<typename T >
int	gem5::RiscvISA::elem_mask (const T *vs, const int index)
template<typename T >
int	gem5::RiscvISA::elem_mask_vseg (const T *vs, const int elem, const int num_fields)
template<typename FloatType , typename IntType = decltype(FloatType::v)>
auto	gem5::RiscvISA::ftype (IntType a) -> FloatType
template<typename FloatType , typename IntType = decltype(FloatType::v)>
auto	gem5::RiscvISA::ftype_freg (freg_t a) -> FloatType
template<typename FloatType >
FloatType	gem5::RiscvISA::fadd (FloatType a, FloatType b)
template<typename FloatType >
FloatType	gem5::RiscvISA::fsub (FloatType a, FloatType b)
template<typename FloatType >
FloatType	gem5::RiscvISA::fmin (FloatType a, FloatType b)
template<typename FloatType >
FloatType	gem5::RiscvISA::fmax (FloatType a, FloatType b)
template<typename FloatType >
FloatType	gem5::RiscvISA::fdiv (FloatType a, FloatType b)
template<typename FloatType >
FloatType	gem5::RiscvISA::fmul (FloatType a, FloatType b)
template<typename FloatType >
FloatType	gem5::RiscvISA::fsqrt (FloatType a)
template<typename FloatType >
FloatType	gem5::RiscvISA::frsqrte7 (FloatType a)
template<typename FloatType >
FloatType	gem5::RiscvISA::frecip7 (FloatType a)
template<typename FloatType >
FloatType	gem5::RiscvISA::fclassify (FloatType a)
template<typename FloatType >
FloatType	gem5::RiscvISA::fsgnj (FloatType a, FloatType b, bool n, bool x)
template<typename FloatType >
bool	gem5::RiscvISA::fle (FloatType a, FloatType b)
template<typename FloatType >
bool	gem5::RiscvISA::feq (FloatType a, FloatType b)
template<typename FloatType >
bool	gem5::RiscvISA::flt (FloatType a, FloatType b)
template<typename FloatType >
FloatType	gem5::RiscvISA::fmadd (FloatType a, FloatType b, FloatType c)
template<typename FloatType >
FloatType	gem5::RiscvISA::fneg (FloatType a)
template<typename FT , typename WFT = typename double_width<FT>::type>
WFT	gem5::RiscvISA::fwiden (FT a)
template<typename FloatType , typename IntType = decltype(FloatType::v)>
IntType	gem5::RiscvISA::f_to_ui (FloatType a, uint_fast8_t mode)
template<typename FloatType , typename IntType = decltype(double_width<FloatType>::type::v)>
IntType	gem5::RiscvISA::f_to_wui (FloatType a, uint_fast8_t mode)
template<typename IntType , typename FloatType = typename double_widthf<IntType>::type>
IntType	gem5::RiscvISA::f_to_nui (FloatType a, uint_fast8_t mode)
template<typename FloatType , typename IntType = decltype(FloatType::v)>
IntType	gem5::RiscvISA::f_to_i (FloatType a, uint_fast8_t mode)
template<typename FloatType , typename IntType = decltype(double_width<FloatType>::type::v)>
IntType	gem5::RiscvISA::f_to_wi (FloatType a, uint_fast8_t mode)
template<typename IntType , typename FloatType = typename double_widthf<IntType>::type>
IntType	gem5::RiscvISA::f_to_ni (FloatType a, uint_fast8_t mode)
template<typename FloatType , typename IntType = decltype(FloatType::v)>
FloatType	gem5::RiscvISA::ui_to_f (IntType a)
template<typename IntType , typename FloatType = typename double_widthf<IntType>::type>
FloatType	gem5::RiscvISA::ui_to_wf (IntType a)
template<typename FloatType , typename IntType = decltype(double_width<FloatType>::type::v)>
FloatType	gem5::RiscvISA::ui_to_nf (IntType a)
template<typename FloatType , typename IntType = decltype(FloatType::v)>
FloatType	gem5::RiscvISA::i_to_f (IntType a)
template<typename IntType , typename FloatType = typename double_widthf<IntType>::type>
FloatType	gem5::RiscvISA::i_to_wf (IntType a)
template<typename FloatType , typename IntType = std::make_signed_t< decltype(double_width<FloatType>::type::v) >>
FloatType	gem5::RiscvISA::i_to_nf (IntType a)
template<typename FloatType , typename FloatWType = typename double_width<FloatType>::type>
FloatWType	gem5::RiscvISA::f_to_wf (FloatType a)
template<typename FloatNType , typename FloatType = typename double_width<FloatNType>::type>
FloatNType	gem5::RiscvISA::f_to_nf (FloatType a)
template<typename T >
T	gem5::RiscvISA::sat_add (T x, T y, bool *sat)
template<typename T >
T	gem5::RiscvISA::sat_sub (T x, T y, bool *sat)
template<typename T >
T	gem5::RiscvISA::sat_addu (T x, T y, bool *sat)
template<typename T >
T	gem5::RiscvISA::sat_subu (T x, T y, bool *sat)
template<typename T >
T	gem5::RiscvISA::int_rounding (T result, uint8_t xrm, unsigned gb)
	Ref: https://github.com/riscv-software-src/riscv-isa-sim.