gem5
v21.2.1.1
arch
power
insts
condition.cc
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2009 The University of Edinburgh
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are
7
* met: redistributions of source code must retain the above copyright
8
* notice, this list of conditions and the following disclaimer;
9
* redistributions in binary form must reproduce the above copyright
10
* notice, this list of conditions and the following disclaimer in the
11
* documentation and/or other materials provided with the distribution;
12
* neither the name of the copyright holders nor the names of its
13
* contributors may be used to endorse or promote products derived from
14
* this software without specific prior written permission.
15
*
16
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
*/
28
29
#include "
arch/power/insts/condition.hh
"
30
31
namespace
gem5
32
{
33
34
using namespace
PowerISA;
35
36
std::string
37
CondLogicOp::generateDisassembly
(
38
Addr
pc
,
const
loader::SymbolTable
*symtab)
const
39
{
40
std::stringstream
ss
;
41
42
ccprintf
(
ss
,
"%-10s "
,
mnemonic
);
43
44
// Format is <mnemonic> bt, ba, bb
45
ss
<<
bt
<<
", "
<<
ba
<<
", "
<<
bb
;
46
47
return
ss
.str();
48
}
49
50
std::string
51
CondMoveOp::generateDisassembly
(
52
Addr
pc
,
const
loader::SymbolTable
*symtab)
const
53
{
54
std::stringstream
ss
;
55
56
ccprintf
(
ss
,
"%-10s "
,
mnemonic
);
57
58
// Format is <mnemonic> bf, bfa
59
ss
<<
bf
<<
", "
<<
bfa
;
60
61
return
ss
.str();
62
}
63
64
}
// namespace gem5
gem5::PowerISA::CondMoveOp::bfa
uint32_t bfa
Definition:
condition.hh:73
gem5::PowerISA::CondMoveOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition:
condition.cc:51
gem5::PowerISA::CondLogicOp::bb
uint32_t bb
Definition:
condition.hh:49
gem5::loader::SymbolTable
Definition:
symtab.hh:65
gem5::PowerISA::CondLogicOp::bt
uint32_t bt
Definition:
condition.hh:50
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition:
cprintf.hh:130
ss
std::stringstream ss
Definition:
trace.test.cc:45
condition.hh
gem5::PowerISA::CondLogicOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition:
condition.cc:37
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:147
gem5::PowerISA::CondLogicOp::ba
uint32_t ba
Definition:
condition.hh:48
gem5::PowerISA::CondMoveOp::bf
uint32_t bf
Definition:
condition.hh:72
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition:
pra_constants.hh:243
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition:
static_inst.hh:280
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
tlb.cc:60
Generated on Wed May 4 2022 12:13:50 for gem5 by
doxygen
1.8.17