gem5 v24.0.0.0
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condition.hh
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1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_POWER_INSTS_CONDITION_HH__
30#define __ARCH_POWER_INSTS_CONDITION_HH__
31
33#include "base/cprintf.hh"
34
35namespace gem5
36{
37
38namespace PowerISA
39{
40
45{
46 protected:
47
48 uint32_t ba;
49 uint32_t bb;
50 uint32_t bt;
51
53 CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
54 : PowerStaticInst(mnem, _machInst, __opClass),
55 ba(machInst.ba),
56 bb(machInst.bb),
58 {
59 }
60
61 std::string generateDisassembly(
62 Addr pc, const loader::SymbolTable *symtab) const override;
63};
64
69{
70 protected:
71
72 uint32_t bf;
73 uint32_t bfa;
74
76 CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
77 : PowerStaticInst(mnem, _machInst, __opClass),
78 bf(machInst.bf),
80 {
81 }
82
83 std::string generateDisassembly(
84 Addr pc, const loader::SymbolTable *symtab) const override;
85};
86
87} // namespace PowerISA
88} // namespace gem5
89
90#endif //__ARCH_POWER_INSTS_CONDITION_HH__
Class for condition register logical operations.
Definition condition.hh:45
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition condition.cc:37
CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition condition.hh:53
Class for condition register move operations.
Definition condition.hh:69
CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition condition.hh:76
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition condition.cc:51
Bitfield< 4 > pc
uint32_t MachInst
Definition types.hh:44
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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