gem5  v22.1.0.0
condition.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_CONDITION_HH__
30 #define __ARCH_POWER_INSTS_CONDITION_HH__
31 
33 #include "base/cprintf.hh"
34 
35 namespace gem5
36 {
37 
38 namespace PowerISA
39 {
40 
45 {
46  protected:
47 
48  uint32_t ba;
49  uint32_t bb;
50  uint32_t bt;
51 
53  CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
54  : PowerStaticInst(mnem, _machInst, __opClass),
55  ba(machInst.ba),
56  bb(machInst.bb),
57  bt(machInst.bt)
58  {
59  }
60 
61  std::string generateDisassembly(
62  Addr pc, const loader::SymbolTable *symtab) const override;
63 };
64 
69 {
70  protected:
71 
72  uint32_t bf;
73  uint32_t bfa;
74 
76  CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
77  : PowerStaticInst(mnem, _machInst, __opClass),
78  bf(machInst.bf),
80  {
81  }
82 
83  std::string generateDisassembly(
84  Addr pc, const loader::SymbolTable *symtab) const override;
85 };
86 
87 } // namespace PowerISA
88 } // namespace gem5
89 
90 #endif //__ARCH_POWER_INSTS_CONDITION_HH__
Class for condition register logical operations.
Definition: condition.hh:45
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: condition.cc:37
CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: condition.hh:53
Class for condition register move operations.
Definition: condition.hh:69
CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: condition.hh:76
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: condition.cc:51
Bitfield< 4 > pc
uint32_t MachInst
Definition: types.hh:44
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147

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