gem5  v21.1.0.2
condition.hh
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28 
29 #ifndef __ARCH_POWER_INSTS_CONDITION_HH__
30 #define __ARCH_POWER_INSTS_CONDITION_HH__
31 
33 #include "base/cprintf.hh"
34 
35 namespace gem5
36 {
37 
38 namespace PowerISA
39 {
40 
45 {
46  protected:
47 
48  uint32_t ba;
49  uint32_t bb;
50  uint32_t bt;
51 
53  CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
54  : PowerStaticInst(mnem, _machInst, __opClass),
55  ba(machInst.ba),
56  bb(machInst.bb),
57  bt(machInst.bt)
58  {
59  }
60 
61  std::string generateDisassembly(
62  Addr pc, const loader::SymbolTable *symtab) const override;
63 };
64 
69 {
70  protected:
71 
72  uint32_t bf;
73  uint32_t bfa;
74 
76  CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
77  : PowerStaticInst(mnem, _machInst, __opClass),
78  bf(machInst.bf),
80  {
81  }
82 
83  std::string generateDisassembly(
84  Addr pc, const loader::SymbolTable *symtab) const override;
85 };
86 
87 } // namespace PowerISA
88 } // namespace gem5
89 
90 #endif //__ARCH_POWER_INSTS_CONDITION_HH__
gem5::PowerISA::CondMoveOp
Class for condition register move operations.
Definition: condition.hh:68
gem5::PowerISA::PowerStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:45
gem5::PowerISA::CondMoveOp::bfa
uint32_t bfa
Definition: condition.hh:73
gem5::PowerISA::CondMoveOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: condition.cc:51
gem5::PowerISA::CondLogicOp::bb
uint32_t bb
Definition: condition.hh:49
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::CondLogicOp::bt
uint32_t bt
Definition: condition.hh:50
gem5::PowerISA::CondMoveOp::CondMoveOp
CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: condition.hh:76
gem5::PowerISA::CondLogicOp
Class for condition register logical operations.
Definition: condition.hh:44
gem5::PowerISA::CondLogicOp::CondLogicOp
CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
Constructor.
Definition: condition.hh:53
cprintf.hh
gem5::PowerISA::CondLogicOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: condition.cc:37
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::CondLogicOp::ba
uint32_t ba
Definition: condition.hh:48
gem5::PowerISA::MachInst
uint32_t MachInst
Definition: types.hh:44
gem5::PowerISA::CondMoveOp::bf
uint32_t bf
Definition: condition.hh:72
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
static_inst.hh
gem5::PowerISA::PowerStaticInst
Definition: static_inst.hh:42

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