gem5  v22.0.0.2
drampower.cc
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37 
38 #include "mem/drampower.hh"
39 
40 #include "base/intmath.hh"
41 #include "sim/core.hh"
42 
43 namespace gem5
44 {
45 
46 DRAMPower::DRAMPower(const DRAMInterfaceParams &p, bool include_io) :
47  powerlib(libDRAMPower(getMemSpec(p), include_io))
48 {
49 }
50 
51 Data::MemArchitectureSpec
52 DRAMPower::getArchParams(const DRAMInterfaceParams &p)
53 {
54  Data::MemArchitectureSpec archSpec;
55  archSpec.burstLength = p.burst_length;
56  archSpec.nbrOfBanks = p.banks_per_rank;
57  // One DRAMPower instance per rank, hence set this to 1
58  archSpec.nbrOfRanks = 1;
59  archSpec.dataRate = p.beats_per_clock;
60  // For now we can ignore the number of columns and rows as they
61  // are not used in the power calculation.
62  archSpec.nbrOfColumns = 0;
63  archSpec.nbrOfRows = 0;
64  archSpec.width = p.device_bus_width;
65  archSpec.nbrOfBankGroups = p.bank_groups_per_rank;
66  archSpec.dll = p.dll;
67  archSpec.twoVoltageDomains = hasTwoVDD(p);
68  // Keep this disabled for now until the model is firmed up.
69  archSpec.termination = false;
70  return archSpec;
71 }
72 
73 Data::MemTimingSpec
74 DRAMPower::getTimingParams(const DRAMInterfaceParams &p)
75 {
76  // Set the values that are used for power calculations and ignore
77  // the ones only used by the controller functionality in DRAMPower
78 
79  // All DRAMPower timings are in clock cycles
80  Data::MemTimingSpec timingSpec;
81  timingSpec.RC = divCeil((p.tRAS + p.tRP), p.tCK);
82  timingSpec.RCD = divCeil(p.tRCD, p.tCK);
83  timingSpec.RL = divCeil(p.tCL, p.tCK);
84  timingSpec.RP = divCeil(p.tRP, p.tCK);
85  timingSpec.RFC = divCeil(p.tRFC, p.tCK);
86  timingSpec.RAS = divCeil(p.tRAS, p.tCK);
87  // Write latency is read latency - 1 cycle
88  // Source: B.Jacob Memory Systems Cache, DRAM, Disk
89  timingSpec.WL = timingSpec.RL - 1;
90  timingSpec.DQSCK = 0; // ignore for now
91  timingSpec.RTP = divCeil(p.tRTP, p.tCK);
92  timingSpec.WR = divCeil(p.tWR, p.tCK);
93  timingSpec.XP = divCeil(p.tXP, p.tCK);
94  timingSpec.XPDLL = divCeil(p.tXPDLL, p.tCK);
95  timingSpec.XS = divCeil(p.tXS, p.tCK);
96  timingSpec.XSDLL = divCeil(p.tXSDLL, p.tCK);
97 
98  // Clock period in ns
99  timingSpec.clkPeriod = (p.tCK / (double)(sim_clock::as_int::ns));
100  assert(timingSpec.clkPeriod != 0);
101  timingSpec.clkMhz = (1 / timingSpec.clkPeriod) * 1000;
102  return timingSpec;
103 }
104 
105 Data::MemPowerSpec
106 DRAMPower::getPowerParams(const DRAMInterfaceParams &p)
107 {
108  // All DRAMPower currents are in mA
109  Data::MemPowerSpec powerSpec;
110  powerSpec.idd0 = p.IDD0 * 1000;
111  powerSpec.idd02 = p.IDD02 * 1000;
112  powerSpec.idd2p0 = p.IDD2P0 * 1000;
113  powerSpec.idd2p02 = p.IDD2P02 * 1000;
114  powerSpec.idd2p1 = p.IDD2P1 * 1000;
115  powerSpec.idd2p12 = p.IDD2P12 * 1000;
116  powerSpec.idd2n = p.IDD2N * 1000;
117  powerSpec.idd2n2 = p.IDD2N2 * 1000;
118  powerSpec.idd3p0 = p.IDD3P0 * 1000;
119  powerSpec.idd3p02 = p.IDD3P02 * 1000;
120  powerSpec.idd3p1 = p.IDD3P1 * 1000;
121  powerSpec.idd3p12 = p.IDD3P12 * 1000;
122  powerSpec.idd3n = p.IDD3N * 1000;
123  powerSpec.idd3n2 = p.IDD3N2 * 1000;
124  powerSpec.idd4r = p.IDD4R * 1000;
125  powerSpec.idd4r2 = p.IDD4R2 * 1000;
126  powerSpec.idd4w = p.IDD4W * 1000;
127  powerSpec.idd4w2 = p.IDD4W2 * 1000;
128  powerSpec.idd5 = p.IDD5 * 1000;
129  powerSpec.idd52 = p.IDD52 * 1000;
130  powerSpec.idd6 = p.IDD6 * 1000;
131  powerSpec.idd62 = p.IDD62 * 1000;
132  powerSpec.vdd = p.VDD;
133  powerSpec.vdd2 = p.VDD2;
134  return powerSpec;
135 }
136 
137 Data::MemorySpecification
138 DRAMPower::getMemSpec(const DRAMInterfaceParams &p)
139 {
140  Data::MemorySpecification memSpec;
141  memSpec.memArchSpec = getArchParams(p);
142  memSpec.memTimingSpec = getTimingParams(p);
143  memSpec.memPowerSpec = getPowerParams(p);
144  return memSpec;
145 }
146 
147 bool
148 DRAMPower::hasTwoVDD(const DRAMInterfaceParams &p)
149 {
150  return p.VDD2 == 0 ? false : true;
151 }
152 
153 uint8_t
154 DRAMPower::getDataRate(const DRAMInterfaceParams &p)
155 {
156  uint32_t burst_cycles = divCeil(p.tBURST_MAX, p.tCK);
157  uint8_t data_rate = p.burst_length / burst_cycles;
158  // 4 for GDDR5
159  if (data_rate != 1 && data_rate != 2 && data_rate != 4 && data_rate != 8)
160  fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
161  return data_rate;
162 }
163 
164 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
drampower.hh
gem5::DRAMPower::hasTwoVDD
static bool hasTwoVDD(const DRAMInterfaceParams &p)
Determine if DRAM has two voltage domains (or one)
Definition: drampower.cc:148
gem5::DRAMPower::getTimingParams
static Data::MemTimingSpec getTimingParams(const DRAMInterfaceParams &p)
Transforms the timing parameters defined in DRAMInterfaceParams to the memSpec of DRAMPower.
Definition: drampower.cc:74
gem5::DRAMPower::getPowerParams
static Data::MemPowerSpec getPowerParams(const DRAMInterfaceParams &p)
Transforms the power and current parameters defined in DRAMInterfaceParams to the memSpec of DRAMPowe...
Definition: drampower.cc:106
gem5::DRAMPower::getArchParams
static Data::MemArchitectureSpec getArchParams(const DRAMInterfaceParams &p)
Transform the architechture parameters defined in DRAMInterfaceParams to the memSpec of DRAMPower.
Definition: drampower.cc:52
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::DRAMPower::DRAMPower
DRAMPower(const DRAMInterfaceParams &p, bool include_io)
Definition: drampower.cc:46
gem5::divCeil
static constexpr T divCeil(const T &a, const U &b)
Definition: intmath.hh:110
core.hh
gem5::DRAMPower::getMemSpec
static Data::MemorySpecification getMemSpec(const DRAMInterfaceParams &p)
Return an instance of MemSpec based on the DRAMInterfaceParams.
Definition: drampower.cc:138
intmath.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::DRAMPower::getDataRate
static uint8_t getDataRate(const DRAMInterfaceParams &p)
Determine data rate, either one or two.
Definition: drampower.cc:154
gem5::sim_clock::as_int::ns
Tick ns
nanosecond
Definition: core.cc:71

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