gem5 v24.0.0.0
Loading...
Searching...
No Matches
fetch1.hh File Reference

Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2. More...

#include <vector>
#include "arch/generic/mmu.hh"
#include "base/named.hh"
#include "cpu/base.hh"
#include "cpu/minor/buffers.hh"
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "mem/packet.hh"

Go to the source code of this file.

Classes

class  gem5::minor::Fetch1
 A stage responsible for fetching "lines" from memory and passing them to Fetch2. More...
 
class  gem5::minor::Fetch1::IcachePort
 Exposable fetch port. More...
 
class  gem5::minor::Fetch1::FetchRequest
 Memory access queuing. More...
 
struct  gem5::minor::Fetch1::Fetch1ThreadInfo
 Stage cycle-by-cycle state. More...
 

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::minor
 

Detailed Description

Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2.

Definition in file fetch1.hh.


Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0