gem5  v21.2.0.0
fetch1.hh
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37 
45 #ifndef __CPU_MINOR_FETCH1_HH__
46 #define __CPU_MINOR_FETCH1_HH__
47 
48 #include <vector>
49 
50 #include "arch/generic/mmu.hh"
51 #include "base/named.hh"
52 #include "cpu/base.hh"
53 #include "cpu/minor/buffers.hh"
54 #include "cpu/minor/cpu.hh"
55 #include "cpu/minor/pipe_data.hh"
56 #include "mem/packet.hh"
57 
58 namespace gem5
59 {
60 
62 namespace minor
63 {
64 
67 class Fetch1 : public Named
68 {
69  protected:
72  {
73  protected:
76 
77  public:
78  IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) :
79  MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_)
80  { }
81 
82  protected:
84  { return fetch.recvTimingResp(pkt); }
85 
87  };
88 
107  class FetchRequest :
108  public BaseMMU::Translation, /* For TLB lookups */
109  public Packet::SenderState /* For packing into a Packet */
110  {
111  protected:
114 
115  public:
119  {
120  NotIssued, /* Just been made */
121  InTranslation, /* Issued to ITLB, must wait for reqply */
122  Translated, /* Translation complete */
123  RequestIssuing, /* Issued to memory, must wait for response */
124  Complete /* Complete. Either a fault, or a fetched line */
125  };
126 
128 
131 
137 
140 
143 
147 
149  void makePacket();
150 
152  void reportData(std::ostream &os) const;
153 
157  bool isDiscardable() const;
158 
160  bool isComplete() const { return state == Complete; }
161 
162  protected:
167  void markDelayed() { }
168 
172  void finish(const Fault &fault_, const RequestPtr &request_,
174 
175  public:
176  FetchRequest(Fetch1 &fetch_, InstId id_, Addr pc_) :
177  SenderState(),
178  fetch(fetch_),
179  state(NotIssued),
180  id(id_),
181  packet(NULL),
182  request(),
183  pc(pc_),
184  fault(NoFault)
185  {
186  request = std::make_shared<Request>();
187  }
188 
189  ~FetchRequest();
190  };
191 
193 
194  protected:
199 
206 
209 
213 
217  unsigned int lineSnap;
218 
223  unsigned int maxLineWidth;
224 
226  unsigned int fetchLimit;
227 
228  protected:
233  {
234  FetchHalted, /* Not fetching, waiting to be woken by transition
235  to FetchWaitingForPC. The PC is not valid in this state */
236  FetchWaitingForPC, /* Not fetching, waiting for stream change.
237  This doesn't stop issued fetches from being returned and
238  processed or for branches to change the state to Running. */
239  FetchRunning /* Try to fetch, when possible */
240  };
241 
245  {
246  // All fields have default initializers.
248 
250  state(other.state),
251  pc(other.pc->clone()),
252  streamSeqNum(other.streamSeqNum),
254  blocked(other.blocked)
255  { }
256 
258 
262  std::unique_ptr<PCStateBase> pc;
263 
266 
271 
277 
279  bool blocked = false;
280 
282  bool wakeupGuard = false;
283  };
284 
287 
290  {
291  IcacheRunning, /* Default. Step icache queues when possible */
292  IcacheNeedsRetry /* Request rejected, will be asked to retry */
293  };
294 
295  typedef Queue<FetchRequestPtr,
299 
302 
305 
308 
311 
320  unsigned int numFetchesInITLB;
321 
322  protected:
323  friend std::ostream &operator <<(std::ostream &os,
324  Fetch1::FetchState state);
325 
327  void changeStream(const BranchData &branch);
328 
332  void updateExpectedSeqNums(const BranchData &branch);
333 
335  void processResponse(FetchRequestPtr response,
336  ForwardLineData &line);
337 
338  friend std::ostream &operator <<(std::ostream &os,
339  IcacheState state);
340 
341 
345 
349  void fetchLine(ThreadID tid);
350 
355 
359  bool tryToSend(FetchRequestPtr request);
360 
363 
365  void stepQueues();
366 
369  void popAndDiscard(FetchQueue &queue);
370 
372  void handleTLBResponse(FetchRequestPtr response);
373 
376  unsigned int numInFlightFetches();
377 
379  void minorTraceResponseLine(const std::string &name,
380  FetchRequestPtr response) const;
381 
383  virtual bool recvTimingResp(PacketPtr pkt);
384  virtual void recvReqRetry();
385 
386  public:
387  Fetch1(const std::string &name_,
388  MinorCPU &cpu_,
389  const MinorCPUParams &params,
392  Latch<BranchData>::Output prediction_,
393  std::vector<InputBuffer<ForwardLineData>> &next_stage_input_buffer);
394 
395  public:
398 
400  void evaluate();
401 
403  void wakeupFetch(ThreadID tid);
404 
405  void minorTrace() const;
406 
409  bool isDrained();
410 };
411 
412 } // namespace minor
413 } // namespace gem5
414 
415 #endif /* __CPU_MINOR_FETCH1_HH__ */
pipe_data.hh
gem5::minor::ForwardLineData
Line fetch data in the forward direction.
Definition: pipe_data.hh:187
gem5::minor::Fetch1::numFetchesInITLB
unsigned int numFetchesInITLB
Number of requests inside the ITLB rather than in the queues.
Definition: fetch1.hh:320
gem5::minor::InstId::firstPredictionSeqNum
static const InstSeqNum firstPredictionSeqNum
Definition: dyn_inst.hh:82
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::MinorCPU::MinorCPUPort::MinorCPUPort
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition: cpu.hh:113
gem5::minor::Fetch1::fetchLine
void fetchLine(ThreadID tid)
Insert a line fetch into the requests.
Definition: fetch1.cc:156
gem5::minor::ReportTraitsPtrAdaptor
A similar adaptor but for elements held by pointer ElemType should implement ReportIF.
Definition: buffers.hh:108
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::minor::Fetch1::out
Latch< ForwardLineData >::Input out
Output port carrying read lines to Fetch2.
Definition: fetch1.hh:203
gem5::minor::Fetch1::operator<<
friend std::ostream & operator<<(std::ostream &os, Fetch1::FetchState state)
Definition: fetch1.cc:470
gem5::minor::Fetch1::threadPriority
ThreadID threadPriority
Definition: fetch1.hh:286
gem5::minor::Fetch1::Fetch1
Fetch1(const std::string &name_, MinorCPU &cpu_, const MinorCPUParams &params, Latch< BranchData >::Output inp_, Latch< ForwardLineData >::Input out_, Latch< BranchData >::Output prediction_, std::vector< InputBuffer< ForwardLineData >> &next_stage_input_buffer)
Definition: fetch1.cc:61
gem5::minor::InstId
Id for lines and instructions.
Definition: dyn_inst.hh:76
gem5::minor::Fetch1::FetchRequest::reportData
void reportData(std::ostream &os) const
Report interface.
Definition: fetch1.cc:750
gem5::minor::Fetch1::FetchRequest::id
InstId id
Identity of the line that this request will generate.
Definition: fetch1.hh:130
gem5::minor::Fetch1::minorTraceResponseLine
void minorTraceResponseLine(const std::string &name, FetchRequestPtr response) const
Print the appropriate MinorLine line for a fetch response.
Definition: fetch1.cc:399
gem5::minor::Fetch1::IcachePort::fetch
Fetch1 & fetch
My owner.
Definition: fetch1.hh:75
gem5::minor::Fetch1::lineSeqNum
InstSeqNum lineSeqNum
Sequence number for line fetch used for ordering lines to flush.
Definition: fetch1.hh:310
gem5::MinorCPU::MinorCPUPort
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:106
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::minor::Fetch1::FetchState
FetchState
Cycle-by-cycle state.
Definition: fetch1.hh:232
gem5::minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum
InstSeqNum predictionSeqNum
Prediction sequence number.
Definition: fetch1.hh:276
gem5::minor::Fetch1::FetchRequest
Memory access queuing.
Definition: fetch1.hh:107
named.hh
gem5::minor::Fetch1::popAndDiscard
void popAndDiscard(FetchQueue &queue)
Pop a request from the given queue and correctly deallocate and discard it.
Definition: fetch1.cc:382
gem5::minor::Fetch1::Fetch1ThreadInfo::Fetch1ThreadInfo
Fetch1ThreadInfo(const Fetch1ThreadInfo &other)
Definition: fetch1.hh:249
gem5::minor::Queue
Wrapper for a queue type to act as a pipeline stage input queue.
Definition: buffers.hh:404
gem5::MinorCPU::MinorCPUPort::cpu
MinorCPU & cpu
The enclosing cpu.
Definition: cpu.hh:110
cpu.hh
gem5::minor::Fetch1::numFetchesInMemorySystem
unsigned int numFetchesInMemorySystem
Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory s...
Definition: fetch1.hh:316
minor
gem5::minor::Fetch1::updateExpectedSeqNums
void updateExpectedSeqNums(const BranchData &branch)
Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and dis...
Definition: fetch1.cc:523
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
gem5::minor::Fetch1::FetchRequest::InTranslation
@ InTranslation
Definition: fetch1.hh:121
gem5::minor::Fetch1::IcachePort::recvReqRetry
void recvReqRetry()
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: fetch1.hh:86
std::vector
STL vector class.
Definition: stl.hh:37
gem5::minor::Fetch1::prediction
Latch< BranchData >::Output prediction
Input port carrying branch predictions from Fetch2.
Definition: fetch1.hh:205
gem5::minor::Fetch1::transfers
FetchQueue transfers
Queue of in-memory system requests and responses.
Definition: fetch1.hh:304
gem5::minor::InstId::firstStreamSeqNum
static const InstSeqNum firstStreamSeqNum
First sequence numbers to use in initialisation of the pipeline and to be expected on the first line/...
Definition: dyn_inst.hh:81
gem5::minor::Fetch1::lineSnap
unsigned int lineSnap
Line snap size in bytes.
Definition: fetch1.hh:217
packet.hh
gem5::minor::InputBuffer
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty,...
Definition: buffers.hh:572
gem5::RubyTester::SenderState
Definition: RubyTester.hh:89
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::minor::Fetch1::icachePort
IcachePort icachePort
IcachePort to pass to the CPU.
Definition: fetch1.hh:212
gem5::minor::Fetch1::handleTLBResponse
void handleTLBResponse(FetchRequestPtr response)
Handle pushing a TLB response onto the right queue.
Definition: fetch1.cc:254
gem5::minor::Fetch1::FetchRequest::isDiscardable
bool isDiscardable() const
Is this line out of date with the current stream/prediction sequence and can it be discarded without ...
Definition: fetch1.cc:755
gem5::minor::Latch::Output
Definition: buffers.hh:263
gem5::minor::Fetch1::FetchRequest::fetch
Fetch1 & fetch
Owning fetch unit.
Definition: fetch1.hh:113
gem5::minor::Fetch1::getScheduledThread
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
Definition: fetch1.cc:124
gem5::minor::Fetch1::nextStageReserve
std::vector< InputBuffer< ForwardLineData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: fetch1.hh:208
gem5::minor::Fetch1::getIcachePort
MinorCPU::MinorCPUPort & getIcachePort()
Returns the IcachePort owned by this Fetch1.
Definition: fetch1.hh:397
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::minor::Fetch1::maxLineWidth
unsigned int maxLineWidth
Maximum fetch width in bytes.
Definition: fetch1.hh:223
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::minor::Fetch1::FetchRequest::fault
Fault fault
Fill in a fault if one happens during fetch, check this by picking apart the response packet.
Definition: fetch1.hh:146
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::minor::Latch::Input
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:252
gem5::minor::Fetch1::FetchRequest::isComplete
bool isComplete() const
Is this a complete read line or fault.
Definition: fetch1.hh:160
gem5::minor::Fetch1::FetchRequest::~FetchRequest
~FetchRequest()
Definition: fetch1.cc:277
gem5::minor::Fetch1::FetchWaitingForPC
@ FetchWaitingForPC
Definition: fetch1.hh:236
gem5::minor::Fetch1::Fetch1ThreadInfo::state
FetchState state
Definition: fetch1.hh:257
gem5::minor::Fetch1::moveFromRequestsToTransfers
void moveFromRequestsToTransfers(FetchRequestPtr request)
Move a request between queues.
Definition: fetch1.cc:323
gem5::minor::Fetch1::tryToSendToTransfers
void tryToSendToTransfers(FetchRequestPtr request)
Try and issue a fetch for a translated request at the head of the requests queue.
Definition: fetch1.cc:284
gem5::minor::Fetch1::IcachePort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: fetch1.hh:83
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::minor::Fetch1
A stage responsible for fetching "lines" from memory and passing them to Fetch2.
Definition: fetch1.hh:67
mmu.hh
gem5::minor::Fetch1::Fetch1ThreadInfo::Fetch1ThreadInfo
Fetch1ThreadInfo()
Definition: fetch1.hh:247
gem5::minor::Fetch1::Fetch1ThreadInfo::blocked
bool blocked
Blocked indication for report.
Definition: fetch1.hh:279
gem5::minor::Fetch1::FetchRequest::Complete
@ Complete
Definition: fetch1.hh:124
gem5::minor::Fetch1::FetchRequest::FetchRequest
FetchRequest(Fetch1 &fetch_, InstId id_, Addr pc_)
Definition: fetch1.hh:176
gem5::minor::Fetch1::FetchRequest::RequestIssuing
@ RequestIssuing
Definition: fetch1.hh:123
gem5::minor::BranchData
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:66
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::minor::Fetch1::processResponse
void processResponse(FetchRequestPtr response, ForwardLineData &line)
Convert a response to a ForwardLineData.
Definition: fetch1.cc:541
gem5::minor::Fetch1::IcacheState
IcacheState
State of memory access for head instruction fetch.
Definition: fetch1.hh:289
gem5::minor::Fetch1::fetchLimit
unsigned int fetchLimit
Maximum number of fetches allowed in flight (in queues or memory)
Definition: fetch1.hh:226
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::minor::Fetch1::FetchHalted
@ FetchHalted
Definition: fetch1.hh:234
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::minor::Fetch1::changeStream
void changeStream(const BranchData &branch)
Start fetching from a new address.
Definition: fetch1.cc:490
gem5::minor::Fetch1::FetchRequest::state
FetchRequestState state
Definition: fetch1.hh:127
gem5::minor::Fetch1::FetchRequest::Translated
@ Translated
Definition: fetch1.hh:122
gem5::minor::Fetch1::FetchRunning
@ FetchRunning
Definition: fetch1.hh:239
gem5::minor::Fetch1::FetchRequest::makePacket
void makePacket()
Make a packet to use with the memory transaction.
Definition: fetch1.cc:229
gem5::minor::Fetch1::recvReqRetry
virtual void recvReqRetry()
Definition: fetch1.cc:455
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::minor::Fetch1::Fetch1ThreadInfo::pc
std::unique_ptr< PCStateBase > pc
Fetch PC value.
Definition: fetch1.hh:262
gem5::minor::Fetch1::FetchRequest::markDelayed
void markDelayed()
BaseMMU::Translation interface.
Definition: fetch1.hh:167
gem5::minor::Fetch1::FetchRequest::FetchRequestState
FetchRequestState
Progress of this request through address translation and memory.
Definition: fetch1.hh:118
gem5::minor::Fetch1::IcacheRunning
@ IcacheRunning
Definition: fetch1.hh:291
gem5::minor::Fetch1::inp
Latch< BranchData >::Output inp
Input port carrying branch requests from Execute.
Definition: fetch1.hh:201
gem5::minor::Fetch1::wakeupFetch
void wakeupFetch(ThreadID tid)
Initiate fetch1 fetching.
Definition: fetch1.cc:718
base.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::minor::Fetch1::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Memory interface.
Definition: fetch1.cc:418
gem5::minor::Fetch1::Fetch1ThreadInfo
Stage cycle-by-cycle state.
Definition: fetch1.hh:244
gem5::minor::Fetch1::cpu
MinorCPU & cpu
Construction-assigned data members.
Definition: fetch1.hh:198
gem5::minor::Fetch1::FetchRequest::NotIssued
@ NotIssued
Definition: fetch1.hh:120
gem5::minor::Fetch1::numInFlightFetches
unsigned int numInFlightFetches()
Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.
Definition: fetch1.cc:391
gem5::minor::Fetch1::Fetch1ThreadInfo::fetchAddr
Addr fetchAddr
The address we're currently fetching lines from.
Definition: fetch1.hh:265
gem5::minor::Fetch1::FetchRequestPtr
FetchRequest * FetchRequestPtr
Definition: fetch1.hh:192
gem5::minor::Fetch1::minorTrace
void minorTrace() const
Definition: fetch1.cc:766
gem5::minor::NoBubbleTraits
...
Definition: buffers.hh:122
gem5::minor::Fetch1::FetchRequest::finish
void finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode)
Interface for ITLB responses.
Definition: fetch1.cc:241
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::minor::Fetch1::requests
FetchQueue requests
Queue of address translated requests from Fetch1.
Definition: fetch1.hh:301
gem5::minor::Fetch1::stepQueues
void stepQueues()
Step requests along between requests and transfers queues.
Definition: fetch1.cc:360
gem5::minor::Fetch1::tryToSend
bool tryToSend(FetchRequestPtr request)
Try to send (or resend) a memory request's next/only packet to the memory system.
Definition: fetch1.cc:332
buffers.hh
gem5::minor::Fetch1::IcacheNeedsRetry
@ IcacheNeedsRetry
Definition: fetch1.hh:292
gem5::minor::Fetch1::fetchInfo
std::vector< Fetch1ThreadInfo > fetchInfo
Definition: fetch1.hh:285
gem5::minor::Fetch1::FetchQueue
Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > > FetchQueue
Definition: fetch1.hh:298
gem5::minor::Fetch1::FetchRequest::pc
Addr pc
PC to fixup with line address.
Definition: fetch1.hh:142
gem5::minor::Fetch1::evaluate
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: fetch1.cc:577
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::minor::Fetch1::FetchRequest::packet
PacketPtr packet
FetchRequests carry packets while they're in the requests and transfers responses queues.
Definition: fetch1.hh:136
gem5::minor::Fetch1::Fetch1ThreadInfo::wakeupGuard
bool wakeupGuard
Signal to guard against sleeping first cycle of wakeup.
Definition: fetch1.hh:282
gem5::minor::Fetch1::IcachePort
Exposable fetch port.
Definition: fetch1.hh:71
gem5::minor::Fetch1::FetchRequest::request
RequestPtr request
The underlying request that this fetch represents.
Definition: fetch1.hh:139
gem5::minor::Fetch1::isDrained
bool isDrained()
Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reas...
Definition: fetch1.cc:732
gem5::minor::Fetch1::icacheState
IcacheState icacheState
Retry state of icache_port.
Definition: fetch1.hh:307
gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum
InstSeqNum streamSeqNum
Stream sequence number.
Definition: fetch1.hh:270
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::minor::Fetch1::IcachePort::IcachePort
IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu)
Definition: fetch1.hh:78

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