Memory access queuing. More...
#include <fetch1.hh>
Public Types | |
| enum | FetchRequestState { NotIssued , InTranslation , Translated , RequestIssuing , Complete } |
| Progress of this request through address translation and memory. More... | |
Public Member Functions | |
| void | makePacket () |
| Make a packet to use with the memory transaction. More... | |
| void | reportData (std::ostream &os) const |
| Report interface. More... | |
| bool | isDiscardable () const |
| Is this line out of date with the current stream/prediction sequence and can it be discarded without orphaning in flight TLB lookups/memory accesses? More... | |
| bool | isComplete () const |
| Is this a complete read line or fault. More... | |
| FetchRequest (Fetch1 &fetch_, InstId id_, Addr pc_) | |
| ~FetchRequest () | |
 Public Member Functions inherited from gem5::BaseMMU::Translation | |
| virtual | ~Translation () |
| virtual bool | squashed () const |
| This function is used by the page table walker to determine if it should translate the a pending request or if the underlying request has been squashed. More... | |
| Public Member Functions inherited from gem5::Packet::SenderState | |
| SenderState () | |
| virtual | ~SenderState () |
Public Attributes | |
| FetchRequestState | state |
| InstId | id |
| Identity of the line that this request will generate. More... | |
| PacketPtr | packet |
| FetchRequests carry packets while they're in the requests and transfers responses queues. More... | |
| RequestPtr | request |
| The underlying request that this fetch represents. More... | |
| Addr | pc |
| PC to fixup with line address. More... | |
| Fault | fault |
| Fill in a fault if one happens during fetch, check this by picking apart the response packet. More... | |
| Public Attributes inherited from gem5::Packet::SenderState | |
| SenderState * | predecessor |
Protected Member Functions | |
| void | markDelayed () |
| BaseMMU::Translation interface. More... | |
| void | finish (const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseMMU::Mode mode) |
| Interface for ITLB responses. More... | |
Protected Attributes | |
| Fetch1 & | fetch |
| Owning fetch unit. More... | |
Detailed Description
Memory access queuing.
A request can be submitted by pushing it onto the requests queue after issuing an ITLB lookup (state becomes InTranslation) with a FetchSenderState senderState containing the current lineSeqNum and stream/predictionSeqNum.
Translated packets (state becomes Translation) are then passed to the memory system and the transfers queue (state becomes RequestIssuing). Retries are handled by leaving the packet on the requests queue and changing the state to IcacheNeedsRetry).
Responses from the memory system alter the request object (state become Complete). Responses can be picked up from the head of the transfers queue to pass on to Fetch2. Structure to hold SenderState info through translation and memory accesses.
Member Enumeration Documentation
◆ FetchRequestState
Constructor & Destructor Documentation
◆ FetchRequest()
◆ ~FetchRequest()
Member Function Documentation
◆ finish()
|
protectedvirtual |
Interface for ITLB responses.
Populates self and then passes the request on to the ports' handleTLBResponse member function
Implements gem5::BaseMMU::Translation.
Definition at line 241 of file fetch1.cc.
References gem5::minor::Pipeline::Fetch1StageId, and state.
◆ isComplete()
|
inline |
Is this a complete read line or fault.
Definition at line 160 of file fetch1.hh.
References Complete, and state.
Referenced by gem5::minor::Fetch1::evaluate().
◆ isDiscardable()
| bool gem5::minor::Fetch1::FetchRequest::isDiscardable | ( | ) | const |
Is this line out of date with the current stream/prediction sequence and can it be discarded without orphaning in flight TLB lookups/memory accesses?
Definition at line 755 of file fetch1.cc.
References gem5::minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum, state, and gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum.
Referenced by gem5::minor::Fetch1::evaluate(), and gem5::minor::Fetch1::tryToSendToTransfers().
◆ makePacket()
| void gem5::minor::Fetch1::FetchRequest::makePacket | ( | ) |
Make a packet to use with the memory transaction.
Definition at line 229 of file fetch1.cc.
References gem5::Packet::allocate(), packet, gem5::Packet::pushSenderState(), gem5::MemCmd::ReadReq, and request.
Referenced by gem5::minor::Fetch1::tryToSendToTransfers().
◆ markDelayed()
|
inlineprotectedvirtual |
BaseMMU::Translation interface.
Interface for ITLB responses. We can handle delay, so don't do anything
Implements gem5::BaseMMU::Translation.
◆ reportData()
| void gem5::minor::Fetch1::FetchRequest::reportData | ( | std::ostream & | os | ) | const |
Report interface.
Definition at line 750 of file fetch1.cc.
References gem5::ArmISA::id, and gem5::X86ISA::os.
Member Data Documentation
◆ fault
| Fault gem5::minor::Fetch1::FetchRequest::fault |
Fill in a fault if one happens during fetch, check this by picking apart the response packet.
Definition at line 146 of file fetch1.hh.
Referenced by gem5::minor::Fetch1::handleTLBResponse(), gem5::minor::Fetch1::minorTraceResponseLine(), gem5::minor::Fetch1::processResponse(), and gem5::minor::Fetch1::tryToSendToTransfers().
◆ fetch
|
protected |
◆ id
| InstId gem5::minor::Fetch1::FetchRequest::id |
Identity of the line that this request will generate.
Definition at line 130 of file fetch1.hh.
Referenced by gem5::minor::Fetch1::evaluate(), gem5::minor::Fetch1::fetchLine(), gem5::minor::Fetch1::minorTraceResponseLine(), gem5::minor::Fetch1::processResponse(), gem5::minor::Fetch1::recvTimingResp(), and gem5::minor::Fetch1::tryToSend().
◆ packet
| PacketPtr gem5::minor::Fetch1::FetchRequest::packet |
FetchRequests carry packets while they're in the requests and transfers responses queues.
When a Packet returns from the memory system, its request needs to have its packet updated as this may have changed in flight
Definition at line 136 of file fetch1.hh.
Referenced by makePacket(), gem5::minor::Fetch1::minorTraceResponseLine(), gem5::minor::Fetch1::processResponse(), gem5::minor::Fetch1::recvTimingResp(), gem5::minor::Fetch1::tryToSend(), and gem5::minor::Fetch1::tryToSendToTransfers().
◆ pc
| Addr gem5::minor::Fetch1::FetchRequest::pc |
PC to fixup with line address.
Definition at line 142 of file fetch1.hh.
Referenced by gem5::minor::Fetch1::processResponse().
◆ request
| RequestPtr gem5::minor::Fetch1::FetchRequest::request |
The underlying request that this fetch represents.
Definition at line 139 of file fetch1.hh.
Referenced by gem5::minor::Fetch1::fetchLine(), FetchRequest(), gem5::minor::Fetch1::handleTLBResponse(), makePacket(), gem5::minor::Fetch1::minorTraceResponseLine(), and gem5::minor::Fetch1::processResponse().
◆ state
| FetchRequestState gem5::minor::Fetch1::FetchRequest::state |
Definition at line 127 of file fetch1.hh.
Referenced by gem5::minor::Fetch1::fetchLine(), gem5::minor::Fetch1::handleTLBResponse(), isComplete(), gem5::minor::Fetch1::recvTimingResp(), gem5::minor::Fetch1::tryToSend(), and gem5::minor::Fetch1::tryToSendToTransfers().
The documentation for this class was generated from the following files: