gem5 v24.1.0.1
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cpu.hh
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1/*
2 * Copyright (c) 2012-2014, 2020 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
44#ifndef __CPU_MINOR_CPU_HH__
45#define __CPU_MINOR_CPU_HH__
46
47#include "base/compiler.hh"
48#include "base/random.hh"
49#include "cpu/base.hh"
50#include "cpu/minor/activity.hh"
51#include "cpu/minor/stats.hh"
52#include "cpu/simple_thread.hh"
53#include "enums/ThreadPolicy.hh"
54#include "params/BaseMinorCPU.hh"
55
56namespace gem5
57{
58
59namespace minor
60{
61
64class Pipeline;
65
68
69} // namespace minor
70
84class MinorCPU : public BaseCPU
85{
86 protected:
90
92
93 public:
98
103
104 public:
108 {
109 public:
112
113 public:
114 MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
115 : RequestPort(name_), cpu(cpu_)
116 { }
117
118 };
119
121 enums::ThreadPolicy threadPolicy;
122 protected:
124 Port &getDataPort() override;
125
127 Port &getInstPort() override;
128
129 public:
130 MinorCPU(const BaseMinorCPUParams &params);
131
132 ~MinorCPU();
133
134 public:
136 void init() override;
137 void startup() override;
138 void wakeup(ThreadID tid) override;
139
142
144 void regStats() override;
145
147 Counter totalInsts() const override;
148 Counter totalOps() const override;
149
150 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
151 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
152
154 void serialize(CheckpointOut &cp) const override;
155 void unserialize(CheckpointIn &cp) override;
156
158 DrainState drain() override;
159 void drainResume() override;
162 void signalDrainDone();
163 void memWriteback() override;
164
166 void switchOut() override;
167 void takeOverFrom(BaseCPU *old_cpu) override;
168
170 void activateContext(ThreadID thread_id) override;
171 void suspendContext(ThreadID thread_id) override;
172
175 {
176 std::vector<ThreadID> prio_list;
177 for (ThreadID i = 1; i <= numThreads; i++) {
178 prio_list.push_back((priority + i) % numThreads);
179 }
180 return prio_list;
181 }
182
184 {
185 std::vector<ThreadID> prio_list;
186 for (ThreadID i = 0; i < numThreads; i++) {
187 prio_list.push_back(i);
188 }
189
190 std::shuffle(prio_list.begin(), prio_list.end(),
191 rng->gen);
192
193 return prio_list;
194 }
195
201
206 void wakeupOnEvent(unsigned int stage_id);
208};
209
210} // namespace gem5
211
212#endif /* __CPU_MINOR_CPU_HH__ */
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition base.hh:588
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition base.hh:417
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition cpu.hh:108
MinorCPU & cpu
The enclosing cpu.
Definition cpu.hh:111
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition cpu.hh:114
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition cpu.hh:85
Port & getInstPort() override
Return a reference to the instruction port.
Definition cpu.cc:301
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition cpu.cc:129
void wakeup(ThreadID tid) override
Definition cpu.cc:143
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition cpu.cc:117
DrainState drain() override
Drain interface.
Definition cpu.cc:165
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition cpu.cc:313
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition cpu.cc:136
minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition cpu.hh:89
minor::MinorStats stats
Processor-specific statistics.
Definition cpu.hh:141
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition cpu.hh:97
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
Definition cpu.cc:189
void init() override
Starting, waking and initialisation.
Definition cpu.cc:98
void switchOut() override
Switching interface from BaseCPU.
Definition cpu.cc:232
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition cpu.cc:291
std::vector< ThreadID > randomPriority()
Definition cpu.hh:183
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Definition cpu.cc:226
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Definition cpu.hh:174
void tick()
The tick method in the MinorCPU is simply updating the cycle counters as the ticking of the pipeline ...
Definition cpu.hh:200
Counter totalOps() const override
Definition cpu.cc:324
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition cpu.cc:110
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition cpu.cc:252
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition cpu.cc:123
Random::RandomPtr rng
Definition cpu.hh:91
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition cpu.cc:244
void startup() override
startup() is the final initialization call before simulation.
Definition cpu.cc:154
enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
Definition cpu.hh:121
Port & getDataPort() override
Return a reference to the data port.
Definition cpu.cc:307
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition cpu.hh:102
void drainResume() override
Resume execution after a successful drain.
Definition cpu.cc:196
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Definition cpu.cc:281
EventFunctionWrapper * fetchEventWrapper
Definition cpu.hh:207
Ports are used to interface objects to each other.
Definition port.hh:62
std::shared_ptr< Random > RandomPtr
Definition random.hh:65
static RandomPtr genRandom()
Definition random.hh:68
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
ActivityRecorder with a Ticked interface.
Definition activity.hh:58
The constructed pipeline.
Definition pipeline.hh:73
STL vector class.
Definition stl.hh:37
The stats for MinorCPU separated from the CPU definition.
DrainState
Object drain/handover states.
Definition drain.hh:75
const Params & params() const
ActivityRecoder from cpu/activity.h wrapped to provide evaluate and minorTrace.
Bitfield< 7 > i
Definition misc_types.hh:67
Bitfield< 3, 0 > priority
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition cpu.hh:67
double Counter
All counters are of 64-bit values.
Definition types.hh:46
Copyright (c) 2024 Arm Limited All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
std::ostream CheckpointOut
Definition serialize.hh:66
Minor contains all the definitions within the MinorCPU apart from the CPU class itself.
Currently unused stats class.
Definition stats.hh:59

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