gem5  v21.1.0.2
cpu.hh
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37 
44 #ifndef __CPU_MINOR_CPU_HH__
45 #define __CPU_MINOR_CPU_HH__
46 
47 #include "base/compiler.hh"
48 #include "base/random.hh"
49 #include "cpu/base.hh"
50 #include "cpu/minor/activity.hh"
51 #include "cpu/minor/stats.hh"
52 #include "cpu/simple_thread.hh"
53 #include "enums/ThreadPolicy.hh"
54 #include "params/MinorCPU.hh"
55 
56 namespace gem5
57 {
58 
60 namespace minor
61 {
62 
65 class Pipeline;
66 
69 
70 } // namespace minor
71 
85 class MinorCPU : public BaseCPU
86 {
87  protected:
91 
92  public:
97 
102 
103  public:
106  class MinorCPUPort : public RequestPort
107  {
108  public:
111 
112  public:
113  MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
114  : RequestPort(name_, &cpu_), cpu(cpu_)
115  { }
116 
117  };
118 
120  enums::ThreadPolicy threadPolicy;
121  protected:
123  Port &getDataPort() override;
124 
126  Port &getInstPort() override;
127 
128  public:
129  MinorCPU(const MinorCPUParams &params);
130 
131  ~MinorCPU();
132 
133  public:
135  void init() override;
136  void startup() override;
137  void wakeup(ThreadID tid) override;
138 
141 
143  void regStats() override;
144 
146  Counter totalInsts() const override;
147  Counter totalOps() const override;
148 
149  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
150  void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
151 
153  void serialize(CheckpointOut &cp) const override;
154  void unserialize(CheckpointIn &cp) override;
155 
157  DrainState drain() override;
158  void drainResume() override;
161  void signalDrainDone();
162  void memWriteback() override;
163 
165  void switchOut() override;
166  void takeOverFrom(BaseCPU *old_cpu) override;
167 
169  void activateContext(ThreadID thread_id) override;
170  void suspendContext(ThreadID thread_id) override;
171 
174  {
175  std::vector<ThreadID> prio_list;
176  for (ThreadID i = 1; i <= numThreads; i++) {
177  prio_list.push_back((priority + i) % numThreads);
178  }
179  return prio_list;
180  }
181 
183  {
184  std::vector<ThreadID> prio_list;
185  for (ThreadID i = 0; i < numThreads; i++) {
186  prio_list.push_back(i);
187  }
188 
189  std::shuffle(prio_list.begin(), prio_list.end(),
190  random_mt.gen);
191 
192  return prio_list;
193  }
194 
200 
205  void wakeupOnEvent(unsigned int stage_id);
207 };
208 
209 } // namespace gem5
210 
211 #endif /* __CPU_MINOR_CPU_HH__ */
gem5::MinorCPU::takeOverFrom
void takeOverFrom(BaseCPU *old_cpu) override
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: cpu.cc:255
gem5::MinorCPU::randomPriority
std::vector< ThreadID > randomPriority()
Definition: cpu.hh:182
gem5::MinorCPU::pipeline
minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects.
Definition: cpu.hh:90
gem5::MinorCPU::MinorCPUPort::MinorCPUPort
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition: cpu.hh:113
gem5::MinorCPU::memWriteback
void memWriteback() override
Write back dirty buffers to memory using functional writes.
Definition: cpu.cc:237
gem5::minor::MinorActivityRecorder
ActivityRecorder with a Ticked interface.
Definition: activity.hh:58
gem5::MinorCPU::tick
void tick()
The tick method in the MinorCPU is simply updating the cycle counters as the ticking of the pipeline ...
Definition: cpu.hh:199
gem5::MinorCPU::MinorCPUPort
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:106
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::BaseCPU::updateCycleCounters
void updateCycleCounters(CPUState state)
base method keeping track of cycle progression
Definition: base.hh:523
random.hh
gem5::MinorCPU::MinorCPUPort::cpu
MinorCPU & cpu
The enclosing cpu.
Definition: cpu.hh:110
minor
gem5::MinorCPU
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:85
std::vector
STL vector class.
Definition: stl.hh:37
gem5::MinorCPU::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: cpu.cc:207
gem5::MinorCPU::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: cpu.cc:147
stats.hh
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::SimpleThread
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
Definition: simple_thread.hh:94
gem5::Random::gen
std::mt19937_64 gen
Definition: random.hh:69
gem5::MinorCPU::totalInsts
Counter totalInsts() const override
Simple inst count interface from BaseCPU.
Definition: cpu.cc:324
gem5::MinorCPU::wakeupOnEvent
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
Definition: cpu.cc:302
gem5::MinorCPU::getDataPort
Port & getDataPort() override
Return a reference to the data port.
Definition: cpu.cc:318
gem5::MinorCPU::threads
std::vector< minor::MinorThread * > threads
These are thread state-representing objects for this CPU.
Definition: cpu.hh:101
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::MinorCPU::stats
minor::MinorStats stats
Processor-specific statistics.
Definition: cpu.hh:140
gem5::BaseCPU::numThreads
ThreadID numThreads
Number of threads we're actually simulating (<= SMT_MAX_THREADS).
Definition: base.hh:368
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::MinorCPU::MinorCPU
MinorCPU(const MinorCPUParams &params)
Definition: cpu.cc:50
gem5::MinorCPU::regStats
void regStats() override
Stats interface from SimObject (by way of BaseCPU)
Definition: cpu.cc:121
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::MinorCPU::totalOps
Counter totalOps() const override
Definition: cpu.cc:335
gem5::BaseCPU::CPU_STATE_ON
@ CPU_STATE_ON
Definition: base.hh:514
gem5::MinorCPU::init
void init() override
Starting, waking and initialisation.
Definition: cpu.cc:100
gem5::BaseCPU
Definition: base.hh:107
gem5::MinorCPU::suspendContext
void suspendContext(ThreadID thread_id) override
Notify the CPU that the indicated context is now suspended.
Definition: cpu.cc:292
gem5::MinorCPU::serialize
void serialize(CheckpointOut &cp) const override
Serialize pipeline data.
Definition: cpu.cc:140
compiler.hh
gem5::minor::Pipeline
The constructed pipeline.
Definition: pipeline.hh:73
gem5::MinorCPU::wakeup
void wakeup(ThreadID tid) override
Definition: cpu.cc:154
gem5::MinorCPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: cpu.cc:134
gem5::MinorCPU::~MinorCPU
~MinorCPU()
Definition: cpu.cc:87
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::MinorCPU::signalDrainDone
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState.
Definition: cpu.cc:200
gem5::MinorCPU::drain
DrainState drain() override
Drain interface.
Definition: cpu.cc:176
gem5::MinorCPU::activateContext
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU.
Definition: cpu.cc:263
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
simple_thread.hh
gem5::MinorCPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:128
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::minor::MinorThread
SimpleThread MinorThread
Minor will use the SimpleThread state for now.
Definition: cpu.hh:65
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::MinorCPU::switchOut
void switchOut() override
Switching interface from BaseCPU.
Definition: cpu.cc:243
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MinorCPU::threadPolicy
enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
Definition: cpu.hh:120
gem5::MinorCPU::activityRecorder
minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
Definition: cpu.hh:96
gem5::MinorCPU::getInstPort
Port & getInstPort() override
Return a reference to the instruction port.
Definition: cpu.cc:312
gem5::minor::MinorStats
Currently unused stats class.
Definition: stats.hh:59
gem5::MinorCPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: cpu.cc:165
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::random_mt
Random random_mt
Definition: random.cc:99
activity.hh
gem5::MinorCPU::fetchEventWrapper
EventFunctionWrapper * fetchEventWrapper
Definition: cpu.hh:206
gem5::MinorCPU::roundRobinPriority
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
Definition: cpu.hh:173
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242

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