A stage responsible for fetching "lines" from memory and passing them to Fetch2. More...

#include <fetch1.hh>

Inheritance diagram for gem5::minor::Fetch1:

Classes
struct	Fetch1ThreadInfo
	Stage cycle-by-cycle state. More...

class	FetchRequest
	Memory access queuing. More...

class	IcachePort
	Exposable fetch port. More...

Public Member Functions
	Fetch1 (const std::string &name_, MinorCPU &cpu_, const BaseMinorCPUParams &params, Latch< BranchData >::Output inp_, Latch< ForwardLineData >::Input out_, Latch< BranchData >::Output prediction_, std::vector< InputBuffer< ForwardLineData > > &next_stage_input_buffer)

MinorCPU::MinorCPUPort &	getIcachePort ()
	Returns the IcachePort owned by this Fetch1.

void	evaluate ()
	Pass on input/buffer data to the output if you can.

void	wakeupFetch (ThreadID tid)
	Initiate fetch1 fetching.

void	minorTrace () const

bool	isDrained ()
	Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reason HaltFetch.

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Protected Types
enum	FetchState { FetchHalted , FetchWaitingForPC , FetchRunning }
	Cycle-by-cycle state. More...

enum	IcacheState { IcacheRunning , IcacheNeedsRetry }
	State of memory access for head instruction fetch. More...

typedef FetchRequest *	FetchRequestPtr

typedef Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > >	FetchQueue

Protected Member Functions
void	changeStream (const BranchData &branch)
	Start fetching from a new address.

void	updateExpectedSeqNums (const BranchData &branch)
	Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and discard (on delivery) all lines in flight)

void	processResponse (FetchRequestPtr response, ForwardLineData &line)
	Convert a response to a ForwardLineData.

ThreadID	getScheduledThread ()
	Use the current threading policy to determine the next thread to fetch from.

void	fetchLine (ThreadID tid)
	Insert a line fetch into the requests.

void	tryToSendToTransfers (FetchRequestPtr request)
	Try and issue a fetch for a translated request at the head of the requests queue.

bool	tryToSend (FetchRequestPtr request)
	Try to send (or resend) a memory request's next/only packet to the memory system.

void	moveFromRequestsToTransfers (FetchRequestPtr request)
	Move a request between queues.

void	stepQueues ()
	Step requests along between requests and transfers queues.

void	popAndDiscard (FetchQueue &queue)
	Pop a request from the given queue and correctly deallocate and discard it.

void	handleTLBResponse (FetchRequestPtr response)
	Handle pushing a TLB response onto the right queue.

unsigned int	numInFlightFetches ()
	Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.

void	minorTraceResponseLine (const std::string &name, FetchRequestPtr response) const
	Print the appropriate MinorLine line for a fetch response.

virtual bool	recvTimingResp (PacketPtr pkt)
	Memory interface.

virtual void	recvReqRetry ()

Protected Attributes
MinorCPU &	cpu
	Construction-assigned data members.

Latch< BranchData >::Output	inp
	Input port carrying branch requests from Execute.

Latch< ForwardLineData >::Input	out
	Output port carrying read lines to Fetch2.

Latch< BranchData >::Output	prediction
	Input port carrying branch predictions from Fetch2.

std::vector< InputBuffer< ForwardLineData > > &	nextStageReserve
	Interface to reserve space in the next stage.

IcachePort	icachePort
	IcachePort to pass to the CPU.

Addr	lineSnap
	Line snap size in bytes.

Addr	maxLineWidth
	Maximum fetch width in bytes.

unsigned int	fetchLimit
	Maximum number of fetches allowed in flight (in queues or memory)

std::vector< Fetch1ThreadInfo >	fetchInfo

ThreadID	threadPriority

FetchQueue	requests
	Queue of address translated requests from Fetch1.

FetchQueue	transfers
	Queue of in-memory system requests and responses.

IcacheState	icacheState
	Retry state of icache_port.

InstSeqNum	lineSeqNum
	Sequence number for line fetch used for ordering lines to flush.

unsigned int	numFetchesInMemorySystem
	Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory system.

unsigned int	numFetchesInITLB
	Number of requests inside the ITLB rather than in the queues.

Friends
std::ostream &	operator<< (std::ostream &os, Fetch1::FetchState state)

std::ostream &	operator<< (std::ostream &os, Fetch1::IcacheState state)

Detailed Description

A stage responsible for fetching "lines" from memory and passing them to Fetch2.

Definition at line 66 of file fetch1.hh.

Member Typedef Documentation

◆ FetchQueue

typedef Queue<FetchRequestPtr, ReportTraitsPtrAdaptor<FetchRequestPtr>, NoBubbleTraits<FetchRequestPtr> > gem5::minor::Fetch1::FetchQueue

protected

Definition at line 297 of file fetch1.hh.

◆ FetchRequestPtr

typedef FetchRequest* gem5::minor::Fetch1::FetchRequestPtr

protected

Definition at line 191 of file fetch1.hh.

Member Enumeration Documentation

◆ FetchState

enum gem5::minor::Fetch1::FetchState

protected

Cycle-by-cycle state.

State of memory access for head instruction fetch

Enumerator
FetchHalted
FetchWaitingForPC
FetchRunning

Definition at line 231 of file fetch1.hh.

◆ IcacheState

enum gem5::minor::Fetch1::IcacheState

protected

State of memory access for head instruction fetch.

Enumerator
IcacheRunning
IcacheNeedsRetry

Definition at line 288 of file fetch1.hh.

Constructor & Destructor Documentation

◆ Fetch1()

gem5::minor::Fetch1::Fetch1	(	const std::string &	name_,
		MinorCPU &	cpu_,
		const BaseMinorCPUParams &	params,
		Latch< BranchData >::Output	inp_,
		Latch< ForwardLineData >::Input	out_,
		Latch< BranchData >::Output	prediction_,
		std::vector< InputBuffer< ForwardLineData > > &	next_stage_input_buffer )

Definition at line 60 of file fetch1.cc.

References gem5::BaseCPU::cacheLineSize(), cpu, DPRINTF, fatal, fetchInfo, fetchLimit, lineSnap, maxLineWidth, and gem5::MinorCPU::threads.

Member Function Documentation

◆ changeStream()

void gem5::minor::Fetch1::changeStream ( const BranchData & branch )

protected

Start fetching from a new address.

Definition at line 489 of file fetch1.cc.

References DPRINTF, gem5::minor::Fetch1::Fetch1ThreadInfo::fetchAddr, FetchHalted, fetchInfo, FetchRunning, FetchWaitingForPC, gem5::minor::BranchData::HaltFetch, gem5::minor::Fetch1::Fetch1ThreadInfo::pc, gem5::minor::BranchData::reason, gem5::ArmISA::set, gem5::minor::Fetch1::Fetch1ThreadInfo::state, gem5::minor::BranchData::SuspendThread, gem5::minor::BranchData::target, gem5::minor::BranchData::threadId, updateExpectedSeqNums(), and gem5::minor::Fetch1::Fetch1ThreadInfo::wakeupGuard.

Referenced by evaluate().

◆ evaluate()

void gem5::minor::Fetch1::evaluate ( )

Pass on input/buffer data to the output if you can.

Are both branches from later stages valid and for the same thread?

Definition at line 576 of file fetch1.cc.

References gem5::ActivityRecorder::activity(), gem5::MinorCPU::activityRecorder, changeStream(), cpu, DPRINTF, gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), gem5::minor::Pipeline::Fetch1StageId, FetchHalted, fetchInfo, fetchLimit, fetchLine(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), getScheduledThread(), gem5::minor::Fetch1::FetchRequest::id, inp, gem5::InvalidThreadID, gem5::minor::BranchData::isBubble(), gem5::minor::ForwardLineData::isBubble(), gem5::minor::Fetch1::FetchRequest::isComplete(), gem5::minor::Fetch1::FetchRequest::isDiscardable(), gem5::minor::BranchData::isStreamChange(), gem5::minor::BranchData::newStreamSeqNum, nextStageReserve, numInFlightFetches(), gem5::BaseCPU::numThreads, out, popAndDiscard(), prediction, processResponse(), gem5::minor::Fetch1::Fetch1ThreadInfo::state, stepQueues(), gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, gem5::minor::BranchData::threadId, gem5::minor::InstId::threadId, transfers, and gem5::MinorCPU::wakeupOnEvent().

Referenced by gem5::minor::Pipeline::evaluate().

◆ fetchLine()

void gem5::minor::Fetch1::fetchLine ( ThreadID tid )

protected

Insert a line fetch into the requests.

This can be a partial line request where the given address has a non-0 offset into a line.

Definition at line 155 of file fetch1.cc.

References cpu, DPRINTF, gem5::BaseMMU::Execute, gem5::minor::Fetch1::Fetch1ThreadInfo::fetchAddr, fetchInfo, gem5::BaseCPU::getContext(), gem5::minor::Fetch1::FetchRequest::id, gem5::Request::INST_FETCH, gem5::BaseCPU::instRequestorId(), gem5::minor::Fetch1::FetchRequest::InTranslation, lineSeqNum, lineSnap, maxLineWidth, numFetchesInITLB, gem5::minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum, gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::push(), gem5::minor::Fetch1::FetchRequest::request, requests, gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::reserve(), gem5::minor::Fetch1::FetchRequest::state, gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, gem5::minor::InstId::threadId, gem5::MinorCPU::threads, and transfers.

Referenced by evaluate().

◆ getIcachePort()

MinorCPU::MinorCPUPort & gem5::minor::Fetch1::getIcachePort ( )

inline

Returns the IcachePort owned by this Fetch1.

Definition at line 396 of file fetch1.hh.

References icachePort.

Referenced by gem5::minor::Pipeline::getInstPort().

◆ getScheduledThread()

ThreadID gem5::minor::Fetch1::getScheduledThread ( )

inlineprotected

Use the current threading policy to determine the next thread to fetch from.

Definition at line 123 of file fetch1.cc.

References gem5::ThreadContext::Active, cpu, fetchInfo, FetchRunning, gem5::BaseCPU::getContext(), gem5::InvalidThreadID, panic, gem5::MinorCPU::randomPriority(), gem5::MinorCPU::roundRobinPriority(), gem5::ThreadContext::status(), gem5::MinorCPU::threadPolicy, and threadPriority.

Referenced by evaluate().

◆ handleTLBResponse()

void gem5::minor::Fetch1::handleTLBResponse ( FetchRequestPtr response )

protected

Handle pushing a TLB response onto the right queue.

Definition at line 253 of file fetch1.cc.

References DPRINTF, gem5::minor::Fetch1::FetchRequest::fault, minorTraceResponseLine(), gem5::Named::name(), gem5::NoFault, numFetchesInITLB, gem5::minor::Fetch1::FetchRequest::request, gem5::minor::Fetch1::FetchRequest::state, gem5::minor::Fetch1::FetchRequest::Translated, and tryToSendToTransfers().

◆ isDrained()

bool gem5::minor::Fetch1::isDrained ( )

Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reason HaltFetch.

Definition at line 731 of file fetch1.cc.

References cpu, DPRINTF, FetchHalted, fetchInfo, FetchRunning, numInFlightFetches(), gem5::BaseCPU::numThreads, out, and gem5::minor::Fetch1::Fetch1ThreadInfo::state.

Referenced by gem5::minor::Pipeline::isDrained().

◆ minorTrace()

void gem5::minor::Fetch1::minorTrace ( ) const

Definition at line 765 of file fetch1.cc.

References gem5::minor::Fetch1::Fetch1ThreadInfo::blocked, data, fetchInfo, icacheState, gem5::minor::minorTrace(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::minorTrace(), numFetchesInITLB, numFetchesInMemorySystem, out, requests, gem5::minor::Fetch1::Fetch1ThreadInfo::state, gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, and transfers.

Referenced by gem5::minor::Pipeline::minorTrace().

◆ minorTraceResponseLine()

void gem5::minor::Fetch1::minorTraceResponseLine	(	const std::string &	name,
		Fetch1::FetchRequestPtr	response ) const

protected

Print the appropriate MinorLine line for a fetch response.

Definition at line 398 of file fetch1.cc.

References gem5::minor::Fetch1::FetchRequest::fault, gem5::minor::Fetch1::FetchRequest::id, gem5::Packet::isError(), gem5::minor::minorLine(), gem5::NoFault, gem5::minor::Fetch1::FetchRequest::packet, and gem5::minor::Fetch1::FetchRequest::request.

Referenced by handleTLBResponse(), and recvTimingResp().

◆ moveFromRequestsToTransfers()

void gem5::minor::Fetch1::moveFromRequestsToTransfers ( FetchRequestPtr request )

protected

Move a request between queues.

Definition at line 322 of file fetch1.cc.

References gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::pop(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::push(), requests, and transfers.

Referenced by recvReqRetry(), and tryToSendToTransfers().

◆ numInFlightFetches()

unsigned int gem5::minor::Fetch1::numInFlightFetches ( )

protected

Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.

Definition at line 390 of file fetch1.cc.

References gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::occupiedSpace(), requests, and transfers.

Referenced by evaluate(), and isDrained().

◆ popAndDiscard()

void gem5::minor::Fetch1::popAndDiscard ( FetchQueue & queue )

protected

Pop a request from the given queue and correctly deallocate and discard it.

Definition at line 381 of file fetch1.cc.

References gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), and gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::pop().

Referenced by evaluate().

◆ processResponse()

void gem5::minor::Fetch1::processResponse	(	Fetch1::FetchRequestPtr	response,
		ForwardLineData &	line )

protected

◆ recvReqRetry()

void gem5::minor::Fetch1::recvReqRetry ( )

protectedvirtual

Definition at line 454 of file fetch1.cc.

References DPRINTF, gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), IcacheNeedsRetry, IcacheRunning, icacheState, moveFromRequestsToTransfers(), requests, and tryToSend().

Referenced by gem5::minor::Fetch1::IcachePort::recvReqRetry().

◆ recvTimingResp()

bool gem5::minor::Fetch1::recvTimingResp ( PacketPtr pkt )

protectedvirtual

Memory interface.

Definition at line 417 of file fetch1.cc.

References gem5::minor::Fetch1::FetchRequest::Complete, cpu, DPRINTF, gem5::minor::Pipeline::Fetch1StageId, gem5::minor::Fetch1::FetchRequest::id, gem5::Packet::isError(), minorTraceResponseLine(), gem5::Named::name(), numFetchesInMemorySystem, gem5::minor::Fetch1::FetchRequest::packet, gem5::Packet::popSenderState(), gem5::safe_cast(), gem5::minor::Fetch1::FetchRequest::state, and gem5::MinorCPU::wakeupOnEvent().

Referenced by gem5::minor::Fetch1::IcachePort::recvTimingResp().

◆ stepQueues()

void gem5::minor::Fetch1::stepQueues ( )

protected

Step requests along between requests and transfers queues.

Definition at line 359 of file fetch1.cc.

References DPRINTF, gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::empty(), gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::front(), IcacheNeedsRetry, IcacheRunning, icacheState, requests, and tryToSendToTransfers().

Referenced by evaluate().

◆ tryToSend()

bool gem5::minor::Fetch1::tryToSend ( FetchRequestPtr request )

protected

Try to send (or resend) a memory request's next/only packet to the memory system.

Returns true if the fetch was successfully sent to memory

Definition at line 331 of file fetch1.cc.

References DPRINTF, IcacheNeedsRetry, icachePort, icacheState, gem5::minor::Fetch1::FetchRequest::id, numFetchesInMemorySystem, gem5::minor::Fetch1::FetchRequest::packet, gem5::minor::Fetch1::FetchRequest::RequestIssuing, gem5::RequestPort::sendTimingReq(), and gem5::minor::Fetch1::FetchRequest::state.

Referenced by recvReqRetry(), and tryToSendToTransfers().

◆ tryToSendToTransfers()

void gem5::minor::Fetch1::tryToSendToTransfers ( FetchRequestPtr request )

protected

Try and issue a fetch for a translated request at the head of the requests queue.

Also tries to move the request between queues

Definition at line 283 of file fetch1.cc.

Referenced by handleTLBResponse(), and stepQueues().

◆ updateExpectedSeqNums()

void gem5::minor::Fetch1::updateExpectedSeqNums ( const BranchData & branch )

protected

Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and discard (on delivery) all lines in flight)

Definition at line 522 of file fetch1.cc.

References DPRINTF, fetchInfo, gem5::minor::BranchData::newPredictionSeqNum, gem5::minor::BranchData::newStreamSeqNum, gem5::minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum, gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, and gem5::minor::BranchData::threadId.

Referenced by changeStream().

◆ wakeupFetch()

void gem5::minor::Fetch1::wakeupFetch ( ThreadID tid )

Initiate fetch1 fetching.

Definition at line 717 of file fetch1.cc.

References cpu, DPRINTF, gem5::minor::Pipeline::Fetch1StageId, gem5::minor::Fetch1::Fetch1ThreadInfo::fetchAddr, fetchInfo, FetchRunning, gem5::BaseCPU::getContext(), gem5::minor::Fetch1::Fetch1ThreadInfo::pc, gem5::ThreadContext::pcState(), gem5::ArmISA::set, gem5::minor::Fetch1::Fetch1ThreadInfo::state, gem5::minor::Fetch1::Fetch1ThreadInfo::wakeupGuard, and gem5::MinorCPU::wakeupOnEvent().

Referenced by gem5::minor::Pipeline::drainResume(), and gem5::minor::Pipeline::wakeupFetch().

Friends And Related Symbol Documentation

◆ operator<< [1/2]

std::ostream & operator<<	(	std::ostream &	os,
		Fetch1::FetchState	state )

friend

Definition at line 468 of file fetch1.cc.

◆ operator<< [2/2]

std::ostream & operator<<	(	std::ostream &	os,
		Fetch1::IcacheState	state )

friend

Definition at line 210 of file fetch1.cc.

Member Data Documentation

◆ cpu

MinorCPU& gem5::minor::Fetch1::cpu

protected

Construction-assigned data members.

Pointer back to the containing CPU

Definition at line 197 of file fetch1.hh.

Referenced by evaluate(), Fetch1(), fetchLine(), getScheduledThread(), isDrained(), recvTimingResp(), tryToSendToTransfers(), and wakeupFetch().

◆ fetchInfo

std::vector<Fetch1ThreadInfo> gem5::minor::Fetch1::fetchInfo

protected

Definition at line 284 of file fetch1.hh.

Referenced by changeStream(), evaluate(), Fetch1(), fetchLine(), getScheduledThread(), isDrained(), minorTrace(), processResponse(), updateExpectedSeqNums(), and wakeupFetch().

◆ fetchLimit

unsigned int gem5::minor::Fetch1::fetchLimit

protected

Maximum number of fetches allowed in flight (in queues or memory)

Definition at line 225 of file fetch1.hh.

Referenced by evaluate(), and Fetch1().

◆ icachePort

IcachePort gem5::minor::Fetch1::icachePort

protected

IcachePort to pass to the CPU.

Fetch1 is the only module that uses it.

Definition at line 211 of file fetch1.hh.

Referenced by getIcachePort(), and tryToSend().

◆ icacheState

IcacheState gem5::minor::Fetch1::icacheState

protected

Retry state of icache_port.

Definition at line 306 of file fetch1.hh.

Referenced by minorTrace(), recvReqRetry(), stepQueues(), and tryToSend().

◆ inp

Latch<BranchData>::Output gem5::minor::Fetch1::inp

protected

Input port carrying branch requests from Execute.

Definition at line 200 of file fetch1.hh.

Referenced by evaluate().

◆ lineSeqNum

InstSeqNum gem5::minor::Fetch1::lineSeqNum

protected

Sequence number for line fetch used for ordering lines to flush.

Definition at line 309 of file fetch1.hh.

Referenced by fetchLine().

◆ lineSnap

Addr gem5::minor::Fetch1::lineSnap

protected

Line snap size in bytes.

All fetches clip to make their ends not extend beyond this limit. Setting this to the machine L1 cache line length will result in fetches never crossing line boundaries.

Definition at line 216 of file fetch1.hh.

Referenced by Fetch1(), and fetchLine().

◆ maxLineWidth

Addr gem5::minor::Fetch1::maxLineWidth

protected

Maximum fetch width in bytes.

Setting this (and lineSnap) to the machine L1 cache line length will result in fetches of whole cache lines. Setting this to sizeof(MachInst) will result it fetches of single instructions (except near the end of lineSnap lines)

Definition at line 222 of file fetch1.hh.

Referenced by Fetch1(), and fetchLine().

◆ nextStageReserve

std::vector<InputBuffer<ForwardLineData> >& gem5::minor::Fetch1::nextStageReserve

protected

Interface to reserve space in the next stage.

Definition at line 207 of file fetch1.hh.

Referenced by evaluate().

◆ numFetchesInITLB

unsigned int gem5::minor::Fetch1::numFetchesInITLB

protected

Number of requests inside the ITLB rather than in the queues.

All requests so located must have reserved space in the transfers queue

Definition at line 319 of file fetch1.hh.

Referenced by fetchLine(), handleTLBResponse(), and minorTrace().

◆ numFetchesInMemorySystem

unsigned int gem5::minor::Fetch1::numFetchesInMemorySystem

protected

Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory system.

Try not to rely on this value, it's better to code without knowledge of the number of outstanding accesses

Definition at line 315 of file fetch1.hh.

Referenced by minorTrace(), recvTimingResp(), and tryToSend().

◆ out

Latch<ForwardLineData>::Input gem5::minor::Fetch1::out

protected

Output port carrying read lines to Fetch2.

Definition at line 202 of file fetch1.hh.

Referenced by evaluate(), isDrained(), and minorTrace().

◆ prediction

Latch<BranchData>::Output gem5::minor::Fetch1::prediction

protected

Input port carrying branch predictions from Fetch2.

Definition at line 204 of file fetch1.hh.

Referenced by evaluate().

◆ requests

FetchQueue gem5::minor::Fetch1::requests

protected

Queue of address translated requests from Fetch1.

Definition at line 300 of file fetch1.hh.

Referenced by fetchLine(), minorTrace(), moveFromRequestsToTransfers(), numInFlightFetches(), recvReqRetry(), stepQueues(), and tryToSendToTransfers().

◆ threadPriority

ThreadID gem5::minor::Fetch1::threadPriority

protected

Definition at line 285 of file fetch1.hh.

Referenced by getScheduledThread().

◆ transfers

FetchQueue gem5::minor::Fetch1::transfers

protected

Queue of in-memory system requests and responses.

Definition at line 303 of file fetch1.hh.

Referenced by evaluate(), fetchLine(), minorTrace(), moveFromRequestsToTransfers(), and numInFlightFetches().

The documentation for this class was generated from the following files:

cpu/minor/fetch1.hh
cpu/minor/fetch1.cc

Classes

Public Member Functions

Protected Types

Protected Member Functions

Protected Attributes

Friends

Detailed Description

Member Typedef Documentation

◆ FetchQueue

◆ FetchRequestPtr

Member Enumeration Documentation

◆ FetchState

◆ IcacheState

Constructor & Destructor Documentation

◆ Fetch1()

Member Function Documentation

◆ changeStream()

◆ evaluate()

◆ fetchLine()

◆ getIcachePort()

◆ getScheduledThread()

◆ handleTLBResponse()

◆ isDrained()

◆ minorTrace()

◆ minorTraceResponseLine()

◆ moveFromRequestsToTransfers()

◆ numInFlightFetches()

◆ popAndDiscard()

◆ processResponse()

◆ recvReqRetry()

◆ recvTimingResp()

◆ stepQueues()

◆ tryToSend()

◆ tryToSendToTransfers()

◆ updateExpectedSeqNums()

◆ wakeupFetch()

Friends And Related Symbol Documentation

◆ operator<< [1/2]

◆ operator<< [2/2]

Member Data Documentation

◆ cpu

◆ fetchInfo

◆ fetchLimit

◆ icachePort

◆ icacheState

◆ inp

◆ lineSeqNum

◆ lineSnap

◆ maxLineWidth

◆ nextStageReserve

◆ numFetchesInITLB

◆ numFetchesInMemorySystem

◆ out

◆ prediction

◆ requests

◆ threadPriority

◆ transfers