gem5  v22.0.0.1
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gem5::minor::Fetch1 Class Reference

A stage responsible for fetching "lines" from memory and passing them to Fetch2. More...

#include <fetch1.hh>

Inheritance diagram for gem5::minor::Fetch1:
gem5::Named

Classes

struct  Fetch1ThreadInfo
 Stage cycle-by-cycle state. More...
 
class  FetchRequest
 Memory access queuing. More...
 
class  IcachePort
 Exposable fetch port. More...
 

Public Member Functions

 Fetch1 (const std::string &name_, MinorCPU &cpu_, const BaseMinorCPUParams &params, Latch< BranchData >::Output inp_, Latch< ForwardLineData >::Input out_, Latch< BranchData >::Output prediction_, std::vector< InputBuffer< ForwardLineData >> &next_stage_input_buffer)
 
MinorCPU::MinorCPUPortgetIcachePort ()
 Returns the IcachePort owned by this Fetch1. More...
 
void evaluate ()
 Pass on input/buffer data to the output if you can. More...
 
void wakeupFetch (ThreadID tid)
 Initiate fetch1 fetching. More...
 
void minorTrace () const
 
bool isDrained ()
 Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reason HaltFetch. More...
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 

Protected Types

enum  FetchState { FetchHalted, FetchWaitingForPC, FetchRunning }
 Cycle-by-cycle state. More...
 
enum  IcacheState { IcacheRunning, IcacheNeedsRetry }
 State of memory access for head instruction fetch. More...
 
typedef FetchRequestFetchRequestPtr
 
typedef Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > > FetchQueue
 

Protected Member Functions

void changeStream (const BranchData &branch)
 Start fetching from a new address. More...
 
void updateExpectedSeqNums (const BranchData &branch)
 Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and discard (on delivery) all lines in flight) More...
 
void processResponse (FetchRequestPtr response, ForwardLineData &line)
 Convert a response to a ForwardLineData. More...
 
ThreadID getScheduledThread ()
 Use the current threading policy to determine the next thread to fetch from. More...
 
void fetchLine (ThreadID tid)
 Insert a line fetch into the requests. More...
 
void tryToSendToTransfers (FetchRequestPtr request)
 Try and issue a fetch for a translated request at the head of the requests queue. More...
 
bool tryToSend (FetchRequestPtr request)
 Try to send (or resend) a memory request's next/only packet to the memory system. More...
 
void moveFromRequestsToTransfers (FetchRequestPtr request)
 Move a request between queues. More...
 
void stepQueues ()
 Step requests along between requests and transfers queues. More...
 
void popAndDiscard (FetchQueue &queue)
 Pop a request from the given queue and correctly deallocate and discard it. More...
 
void handleTLBResponse (FetchRequestPtr response)
 Handle pushing a TLB response onto the right queue. More...
 
unsigned int numInFlightFetches ()
 Returns the total number of queue occupancy, in-ITLB and in-memory system fetches. More...
 
void minorTraceResponseLine (const std::string &name, FetchRequestPtr response) const
 Print the appropriate MinorLine line for a fetch response. More...
 
virtual bool recvTimingResp (PacketPtr pkt)
 Memory interface. More...
 
virtual void recvReqRetry ()
 

Protected Attributes

MinorCPUcpu
 Construction-assigned data members. More...
 
Latch< BranchData >::Output inp
 Input port carrying branch requests from Execute. More...
 
Latch< ForwardLineData >::Input out
 Output port carrying read lines to Fetch2. More...
 
Latch< BranchData >::Output prediction
 Input port carrying branch predictions from Fetch2. More...
 
std::vector< InputBuffer< ForwardLineData > > & nextStageReserve
 Interface to reserve space in the next stage. More...
 
IcachePort icachePort
 IcachePort to pass to the CPU. More...
 
unsigned int lineSnap
 Line snap size in bytes. More...
 
unsigned int maxLineWidth
 Maximum fetch width in bytes. More...
 
unsigned int fetchLimit
 Maximum number of fetches allowed in flight (in queues or memory) More...
 
std::vector< Fetch1ThreadInfofetchInfo
 
ThreadID threadPriority
 
FetchQueue requests
 Queue of address translated requests from Fetch1. More...
 
FetchQueue transfers
 Queue of in-memory system requests and responses. More...
 
IcacheState icacheState
 Retry state of icache_port. More...
 
InstSeqNum lineSeqNum
 Sequence number for line fetch used for ordering lines to flush. More...
 
unsigned int numFetchesInMemorySystem
 Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory system. More...
 
unsigned int numFetchesInITLB
 Number of requests inside the ITLB rather than in the queues. More...
 

Friends

std::ostream & operator<< (std::ostream &os, Fetch1::FetchState state)
 
std::ostream & operator<< (std::ostream &os, IcacheState state)
 

Detailed Description

A stage responsible for fetching "lines" from memory and passing them to Fetch2.

Definition at line 67 of file fetch1.hh.

Member Typedef Documentation

◆ FetchQueue

Definition at line 298 of file fetch1.hh.

◆ FetchRequestPtr

Definition at line 192 of file fetch1.hh.

Member Enumeration Documentation

◆ FetchState

Cycle-by-cycle state.

State of memory access for head instruction fetch

Enumerator
FetchHalted 
FetchWaitingForPC 
FetchRunning 

Definition at line 232 of file fetch1.hh.

◆ IcacheState

State of memory access for head instruction fetch.

Enumerator
IcacheRunning 
IcacheNeedsRetry 

Definition at line 289 of file fetch1.hh.

Constructor & Destructor Documentation

◆ Fetch1()

gem5::minor::Fetch1::Fetch1 ( const std::string &  name_,
MinorCPU cpu_,
const BaseMinorCPUParams &  params,
Latch< BranchData >::Output  inp_,
Latch< ForwardLineData >::Input  out_,
Latch< BranchData >::Output  prediction_,
std::vector< InputBuffer< ForwardLineData >> &  next_stage_input_buffer 
)

Definition at line 61 of file fetch1.cc.

References cpu, DPRINTF, fatal, fetchInfo, fetchLimit, lineSnap, maxLineWidth, and gem5::MinorCPU::threads.

Member Function Documentation

◆ changeStream()

void gem5::minor::Fetch1::changeStream ( const BranchData branch)
protected

◆ evaluate()

void gem5::minor::Fetch1::evaluate ( )

◆ fetchLine()

void gem5::minor::Fetch1::fetchLine ( ThreadID  tid)
protected

◆ getIcachePort()

MinorCPU::MinorCPUPort& gem5::minor::Fetch1::getIcachePort ( )
inline

Returns the IcachePort owned by this Fetch1.

Definition at line 397 of file fetch1.hh.

References icachePort.

Referenced by gem5::minor::Pipeline::getInstPort().

◆ getScheduledThread()

ThreadID gem5::minor::Fetch1::getScheduledThread ( )
inlineprotected

Use the current threading policy to determine the next thread to fetch from.

Definition at line 124 of file fetch1.cc.

References gem5::ThreadContext::Active, cpu, fetchInfo, FetchRunning, gem5::InvalidThreadID, panic, gem5::auxv::Random, gem5::MinorCPU::randomPriority(), gem5::MinorCPU::roundRobinPriority(), gem5::MinorCPU::threadPolicy, and threadPriority.

Referenced by evaluate().

◆ handleTLBResponse()

void gem5::minor::Fetch1::handleTLBResponse ( FetchRequestPtr  response)
protected

◆ isDrained()

bool gem5::minor::Fetch1::isDrained ( )

Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reason HaltFetch.

Definition at line 732 of file fetch1.cc.

References cpu, DPRINTF, FetchHalted, fetchInfo, FetchRunning, numInFlightFetches(), out, and gem5::minor::Fetch1::Fetch1ThreadInfo::state.

Referenced by gem5::minor::Pipeline::isDrained().

◆ minorTrace()

void gem5::minor::Fetch1::minorTrace ( ) const

◆ minorTraceResponseLine()

void gem5::minor::Fetch1::minorTraceResponseLine ( const std::string &  name,
Fetch1::FetchRequestPtr  response 
) const
protected

◆ moveFromRequestsToTransfers()

void gem5::minor::Fetch1::moveFromRequestsToTransfers ( FetchRequestPtr  request)
protected

◆ numInFlightFetches()

unsigned int gem5::minor::Fetch1::numInFlightFetches ( )
protected

Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.

Definition at line 391 of file fetch1.cc.

References gem5::minor::Queue< ElemType, ReportTraits, BubbleTraits >::occupiedSpace(), requests, and transfers.

Referenced by evaluate(), and isDrained().

◆ popAndDiscard()

void gem5::minor::Fetch1::popAndDiscard ( FetchQueue queue)
protected

◆ processResponse()

void gem5::minor::Fetch1::processResponse ( Fetch1::FetchRequestPtr  response,
ForwardLineData line 
)
protected

◆ recvReqRetry()

void gem5::minor::Fetch1::recvReqRetry ( )
protectedvirtual

◆ recvTimingResp()

bool gem5::minor::Fetch1::recvTimingResp ( PacketPtr  pkt)
protectedvirtual

◆ stepQueues()

void gem5::minor::Fetch1::stepQueues ( )
protected

◆ tryToSend()

bool gem5::minor::Fetch1::tryToSend ( FetchRequestPtr  request)
protected

Try to send (or resend) a memory request's next/only packet to the memory system.

Returns true if the fetch was successfully sent to memory

Definition at line 332 of file fetch1.cc.

References DPRINTF, IcacheNeedsRetry, icachePort, icacheState, gem5::minor::Fetch1::FetchRequest::id, numFetchesInMemorySystem, gem5::minor::Fetch1::FetchRequest::packet, gem5::minor::Fetch1::FetchRequest::RequestIssuing, gem5::RequestPort::sendTimingReq(), and gem5::minor::Fetch1::FetchRequest::state.

Referenced by recvReqRetry(), and tryToSendToTransfers().

◆ tryToSendToTransfers()

void gem5::minor::Fetch1::tryToSendToTransfers ( FetchRequestPtr  request)
protected

◆ updateExpectedSeqNums()

void gem5::minor::Fetch1::updateExpectedSeqNums ( const BranchData branch)
protected

Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and discard (on delivery) all lines in flight)

Definition at line 523 of file fetch1.cc.

References DPRINTF, fetchInfo, gem5::minor::BranchData::newPredictionSeqNum, gem5::minor::BranchData::newStreamSeqNum, gem5::minor::Fetch1::Fetch1ThreadInfo::predictionSeqNum, gem5::minor::Fetch1::Fetch1ThreadInfo::streamSeqNum, and gem5::minor::BranchData::threadId.

Referenced by changeStream().

◆ wakeupFetch()

void gem5::minor::Fetch1::wakeupFetch ( ThreadID  tid)

Friends And Related Function Documentation

◆ operator<< [1/2]

std::ostream& operator<< ( std::ostream &  os,
Fetch1::FetchState  state 
)
friend

Definition at line 470 of file fetch1.cc.

◆ operator<< [2/2]

std::ostream& operator<< ( std::ostream &  os,
Fetch1::IcacheState  state 
)
friend

Definition at line 212 of file fetch1.cc.

Member Data Documentation

◆ cpu

MinorCPU& gem5::minor::Fetch1::cpu
protected

Construction-assigned data members.

Pointer back to the containing CPU

Definition at line 198 of file fetch1.hh.

Referenced by evaluate(), Fetch1(), fetchLine(), getScheduledThread(), isDrained(), recvTimingResp(), tryToSendToTransfers(), and wakeupFetch().

◆ fetchInfo

std::vector<Fetch1ThreadInfo> gem5::minor::Fetch1::fetchInfo
protected

◆ fetchLimit

unsigned int gem5::minor::Fetch1::fetchLimit
protected

Maximum number of fetches allowed in flight (in queues or memory)

Definition at line 226 of file fetch1.hh.

Referenced by evaluate(), and Fetch1().

◆ icachePort

IcachePort gem5::minor::Fetch1::icachePort
protected

IcachePort to pass to the CPU.

Fetch1 is the only module that uses it.

Definition at line 212 of file fetch1.hh.

Referenced by getIcachePort(), and tryToSend().

◆ icacheState

IcacheState gem5::minor::Fetch1::icacheState
protected

Retry state of icache_port.

Definition at line 307 of file fetch1.hh.

Referenced by minorTrace(), recvReqRetry(), stepQueues(), and tryToSend().

◆ inp

Latch<BranchData>::Output gem5::minor::Fetch1::inp
protected

Input port carrying branch requests from Execute.

Definition at line 201 of file fetch1.hh.

Referenced by evaluate().

◆ lineSeqNum

InstSeqNum gem5::minor::Fetch1::lineSeqNum
protected

Sequence number for line fetch used for ordering lines to flush.

Definition at line 310 of file fetch1.hh.

Referenced by fetchLine().

◆ lineSnap

unsigned int gem5::minor::Fetch1::lineSnap
protected

Line snap size in bytes.

All fetches clip to make their ends not extend beyond this limit. Setting this to the machine L1 cache line length will result in fetches never crossing line boundaries.

Definition at line 217 of file fetch1.hh.

Referenced by Fetch1(), and fetchLine().

◆ maxLineWidth

unsigned int gem5::minor::Fetch1::maxLineWidth
protected

Maximum fetch width in bytes.

Setting this (and lineSnap) to the machine L1 cache line length will result in fetches of whole cache lines. Setting this to sizeof(MachInst) will result it fetches of single instructions (except near the end of lineSnap lines)

Definition at line 223 of file fetch1.hh.

Referenced by Fetch1(), and fetchLine().

◆ nextStageReserve

std::vector<InputBuffer<ForwardLineData> >& gem5::minor::Fetch1::nextStageReserve
protected

Interface to reserve space in the next stage.

Definition at line 208 of file fetch1.hh.

Referenced by evaluate().

◆ numFetchesInITLB

unsigned int gem5::minor::Fetch1::numFetchesInITLB
protected

Number of requests inside the ITLB rather than in the queues.

All requests so located must have reserved space in the transfers queue

Definition at line 320 of file fetch1.hh.

Referenced by fetchLine(), handleTLBResponse(), and minorTrace().

◆ numFetchesInMemorySystem

unsigned int gem5::minor::Fetch1::numFetchesInMemorySystem
protected

Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory system.

Try not to rely on this value, it's better to code without knowledge of the number of outstanding accesses

Definition at line 316 of file fetch1.hh.

Referenced by minorTrace(), recvTimingResp(), and tryToSend().

◆ out

Latch<ForwardLineData>::Input gem5::minor::Fetch1::out
protected

Output port carrying read lines to Fetch2.

Definition at line 203 of file fetch1.hh.

Referenced by evaluate(), isDrained(), and minorTrace().

◆ prediction

Latch<BranchData>::Output gem5::minor::Fetch1::prediction
protected

Input port carrying branch predictions from Fetch2.

Definition at line 205 of file fetch1.hh.

Referenced by evaluate().

◆ requests

FetchQueue gem5::minor::Fetch1::requests
protected

Queue of address translated requests from Fetch1.

Definition at line 301 of file fetch1.hh.

Referenced by fetchLine(), minorTrace(), moveFromRequestsToTransfers(), numInFlightFetches(), recvReqRetry(), stepQueues(), and tryToSendToTransfers().

◆ threadPriority

ThreadID gem5::minor::Fetch1::threadPriority
protected

Definition at line 286 of file fetch1.hh.

Referenced by getScheduledThread().

◆ transfers

FetchQueue gem5::minor::Fetch1::transfers
protected

Queue of in-memory system requests and responses.

Definition at line 304 of file fetch1.hh.

Referenced by evaluate(), fetchLine(), minorTrace(), moveFromRequestsToTransfers(), and numInFlightFetches().


The documentation for this class was generated from the following files:

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