gem5  v21.2.1.1
i8237.hh
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28 
29 #ifndef __DEV_X86_I8237_HH__
30 #define __DEV_X86_I8237_HH__
31 
32 #include <array>
33 
34 #include "dev/io_device.hh"
35 #include "dev/reg_bank.hh"
36 #include "params/I8237.hh"
37 
38 namespace gem5
39 {
40 
41 namespace X86ISA
42 {
43 
44 class I8237 : public BasicPioDevice
45 {
46  public:
48 
49  protected:
51  uint8_t maskReg = 0;
52 
54 
55  struct Channel
56  {
57  class ChannelAddrReg : public Register
58  {
59  public:
61  };
62 
64  {
65  public:
67  };
68 
69  int number;
70 
73 
74  Channel(int _num) : number(_num), addrReg(*this), remainingReg(*this)
75  {}
76  };
77 
78  class WriteOnlyReg : public Register
79  {
80  public:
81  WriteOnlyReg(const std::string &new_name, Addr offset);
82  };
83 
84  std::array<Channel, 4> channels;
85 
94 
95  void setMaskBit(Register &reg, const uint8_t &command);
96 
97  public:
98  using Params = I8237Params;
99 
100  I8237(const Params &p);
101 
102  Tick read(PacketPtr pkt) override;
103  Tick write(PacketPtr pkt) override;
104 
105  void serialize(CheckpointOut &cp) const override;
106  void unserialize(CheckpointIn &cp) override;
107 };
108 
109 } // namespace X86ISA
110 } // namespace gem5
111 
112 #endif //__DEV_X86_I8237_HH__
gem5::X86ISA::I8237::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8237.cc:162
gem5::RegisterBank< ByteOrder::little >::Register8
Register< uint8_t > Register8
Definition: reg_bank.hh:788
gem5::X86ISA::I8237::latency
Tick latency
Definition: i8237.hh:50
io_device.hh
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::I8237::Channel
Definition: i8237.hh:55
gem5::X86ISA::I8237::temporaryMasterClearReg
Register temporaryMasterClearReg
Definition: i8237.hh:91
gem5::X86ISA::I8237::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8237.cc:156
gem5::X86ISA::offset
offset
Definition: misc.hh:1030
gem5::X86ISA::I8237::Channel::remainingReg
ChannelRemainingReg remainingReg
Definition: i8237.hh:72
gem5::X86ISA::I8237::WriteOnlyReg::WriteOnlyReg
WriteOnlyReg(const std::string &new_name, Addr offset)
Definition: i8237.cc:76
gem5::X86ISA::I8237::Channel::number
int number
Definition: i8237.hh:69
gem5::X86ISA::I8237::Channel::ChannelRemainingReg
Definition: i8237.hh:63
gem5::X86ISA::I8237::Channel::Channel
Channel(int _num)
Definition: i8237.hh:74
gem5::X86ISA::I8237
Definition: i8237.hh:44
gem5::X86ISA::I8237::channels
std::array< Channel, 4 > channels
Definition: i8237.hh:84
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::X86ISA::I8237::modeReg
WriteOnlyReg modeReg
Definition: i8237.hh:89
gem5::X86ISA::I8237::WriteOnlyReg
Definition: i8237.hh:78
gem5::X86ISA::I8237::maskReg
uint8_t maskReg
Definition: i8237.hh:51
gem5::X86ISA::I8237::writeMaskReg
WriteOnlyReg writeMaskReg
Definition: i8237.hh:93
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::X86ISA::I8237::statusCommandReg
Register statusCommandReg
Definition: i8237.hh:86
gem5::X86ISA::I8237::Channel::ChannelAddrReg::ChannelAddrReg
ChannelAddrReg(Channel &)
Definition: i8237.cc:62
gem5::X86ISA::I8237::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8237.cc:148
gem5::X86ISA::I8237::setMaskBitReg
WriteOnlyReg setMaskBitReg
Definition: i8237.hh:88
gem5::X86ISA::I8237::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8237.cc:140
gem5::X86ISA::I8237::Channel::ChannelAddrReg
Definition: i8237.hh:57
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::I8237::Channel::ChannelRemainingReg::ChannelRemainingReg
ChannelRemainingReg(Channel &)
Definition: i8237.cc:69
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::I8237::Channel::addrReg
ChannelAddrReg addrReg
Definition: i8237.hh:71
gem5::RegisterBank< ByteOrder::little >
gem5::X86ISA::I8237::requestReg
WriteOnlyReg requestReg
Definition: i8237.hh:87
gem5::X86ISA::I8237::clearMaskReg
WriteOnlyReg clearMaskReg
Definition: i8237.hh:92
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::I8237::Register
RegisterBankLE::Register8 Register
Definition: i8237.hh:47
gem5::X86ISA::I8237::regs
RegisterBankLE regs
Definition: i8237.hh:53
gem5::X86ISA::I8237::setMaskBit
void setMaskBit(Register &reg, const uint8_t &command)
Definition: i8237.cc:130
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::X86ISA::I8237::clearFlipFlopReg
WriteOnlyReg clearFlipFlopReg
Definition: i8237.hh:90
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::X86ISA::I8237::I8237
I8237(const Params &p)
Definition: i8237.cc:84
reg_bank.hh

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