gem5  v21.1.0.2
pagetable.hh
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38 
39 #ifndef __ARCH_X86_PAGETABLE_HH__
40 #define __ARCH_X86_PAGETABLE_HH__
41 
42 #include <cstdint>
43 
44 #include "arch/x86/page_size.hh"
45 #include "base/bitunion.hh"
46 #include "base/types.hh"
47 #include "base/trie.hh"
48 #include "mem/port_proxy.hh"
49 #include "sim/serialize.hh"
50 
51 namespace gem5
52 {
53 
54 class ThreadContext;
55 
56 namespace X86ISA
57 {
58  struct TlbEntry;
59 }
60 
62 
63 namespace X86ISA
64 {
65  struct TlbEntry : public Serializable
66  {
67  // The base of the physical page.
69 
70  // The beginning of the virtual page this entry maps.
72  // The size of the page this represents, in address bits.
73  unsigned logBytes;
74 
75  // Read permission is always available, assuming it isn't blocked by
76  // other mechanisms.
77  bool writable;
78  // Whether this page is accesible without being in supervisor mode.
79  bool user;
80  // Whether to use write through or write back. M5 ignores this and
81  // lets the caches handle the writeback policy.
82  //bool pwt;
83  // Whether the page is cacheable or not.
85  // Whether or not to kick this page out on a write to CR3.
86  bool global;
87  // A bit used to form an index into the PAT table.
88  bool patBit;
89  // Whether or not memory on this page can be executed.
90  bool noExec;
91  // A sequence number to keep track of LRU.
92  uint64_t lruSeq;
93 
95 
96  TlbEntry(Addr asn, Addr _vaddr, Addr _paddr,
97  bool uncacheable, bool read_only);
98  TlbEntry();
99 
100  void
101  updateVaddr(Addr new_vaddr)
102  {
103  vaddr = new_vaddr;
104  }
105 
107  {
108  return paddr;
109  }
110 
111  // Return the page size in bytes
112  int size()
113  {
114  return (1 << logBytes);
115  }
116 
117  void serialize(CheckpointOut &cp) const override;
118  void unserialize(CheckpointIn &cp) override;
119  };
120 
121 
122  BitUnion64(VAddr)
123  Bitfield<20, 12> longl1;
124  Bitfield<29, 21> longl2;
125  Bitfield<38, 30> longl3;
126  Bitfield<47, 39> longl4;
127 
128  Bitfield<20, 12> pael1;
129  Bitfield<29, 21> pael2;
130  Bitfield<31, 30> pael3;
131 
132  Bitfield<21, 12> norml1;
133  Bitfield<31, 22> norml2;
134  EndBitUnion(VAddr)
135 
136  // Unfortunately, the placement of the base field in a page table entry is
137  // very erratic and would make a mess here. It might be moved here at some
138  // point in the future.
140  Bitfield<63> nx;
141  Bitfield<51, 12> base;
142  Bitfield<11, 9> avl;
143  Bitfield<8> g;
144  Bitfield<7> ps;
145  Bitfield<6> d;
146  Bitfield<5> a;
147  Bitfield<4> pcd;
148  Bitfield<3> pwt;
149  Bitfield<2> u;
150  Bitfield<1> w;
151  Bitfield<0> p;
153 
154  template <int first, int last>
156  {
157  public:
158  Addr paddr() { return pte.base << PageShift; }
159  void paddr(Addr addr) { pte.base = addr >> PageShift; }
160 
161  bool present() { return pte.p; }
162  void present(bool p) { pte.p = p ? 1 : 0; }
163 
164  bool uncacheable() { return pte.pcd; }
165  void uncacheable(bool u) { pte.pcd = u ? 1 : 0; }
166 
167  bool readonly() { return !pte.w; }
168  void readonly(bool r) { pte.w = r ? 0 : 1; }
169 
170  void
172  {
173  entryAddr = table;
174  entryAddr += bits(vaddr, first, last) * sizeof(PageTableEntry);
175  pte = p.read<PageTableEntry>(entryAddr);
176  }
177 
178  void
179  reset(Addr _paddr, bool _present=true,
180  bool _uncacheable=false, bool _readonly=false)
181  {
182  pte = 0;
183  pte.u = 1;
184  paddr(_paddr);
185  present(_present);
186  uncacheable(_uncacheable);
187  readonly(_readonly);
188  };
189 
190  void write(PortProxy &p) { p.write(entryAddr, pte); }
191 
192  static int
194  {
195  return 1 << ((first - last) + 4 - PageShift);
196  }
197 
198  protected:
201  };
202 
203 } // namespace X86ISA
204 } // namespace gem5
205 
206 #endif
gem5::X86ISA::LongModePTE::entryAddr
Addr entryAddr
Definition: pagetable.hh:200
gem5::X86ISA::TlbEntry::writable
bool writable
Definition: pagetable.hh:77
gem5::X86ISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: pagetable.cc:66
gem5::X86ISA::pael2
Bitfield< 29, 21 > pael2
Definition: pagetable.hh:129
gem5::X86ISA::u
Bitfield< 2 > u
Definition: pagetable.hh:149
gem5::X86ISA::TlbEntry::pageStart
Addr pageStart()
Definition: pagetable.hh:106
gem5::X86ISA::TlbEntry::trieHandle
TlbEntryTrie::Handle trieHandle
Definition: pagetable.hh:94
serialize.hh
gem5::X86ISA::LongModePTE::readonly
void readonly(bool r)
Definition: pagetable.hh:168
gem5::X86ISA::LongModePTE::uncacheable
bool uncacheable()
Definition: pagetable.hh:164
gem5::X86ISA::LongModePTE::read
void read(PortProxy &p, Addr table, Addr vaddr)
Definition: pagetable.hh:171
gem5::X86ISA::TlbEntry::user
bool user
Definition: pagetable.hh:79
gem5::X86ISA::TlbEntry::patBit
bool patBit
Definition: pagetable.hh:88
gem5::X86ISA::LongModePTE::write
void write(PortProxy &p)
Definition: pagetable.hh:190
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::TlbEntry::size
int size()
Definition: pagetable.hh:112
gem5::X86ISA::longl3
Bitfield< 38, 30 > longl3
Definition: pagetable.hh:125
gem5::X86ISA::LongModePTE::present
bool present()
Definition: pagetable.hh:161
gem5::X86ISA::PageShift
const Addr PageShift
Definition: page_size.hh:48
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::TlbEntryTrie
Trie< Addr, X86ISA::TlbEntry > TlbEntryTrie
Definition: pagetable.hh:61
gem5::X86ISA::LongModePTE::paddr
Addr paddr()
Definition: pagetable.hh:158
gem5::X86ISA::TlbEntry
Definition: pagetable.hh:65
gem5::X86ISA::longl1
longl1
Definition: pagetable.hh:123
gem5::Trie
A trie is a tree-based data structure used for data retrieval.
Definition: trie.hh:54
gem5::X86ISA::norml1
Bitfield< 21, 12 > norml1
Definition: pagetable.hh:132
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:998
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::X86ISA::pcd
Bitfield< 4 > pcd
Definition: pagetable.hh:147
gem5::statistics::Node
Base class for formula statistic node.
Definition: statistics.hh:1520
gem5::X86ISA::r
Bitfield< 41 > r
Definition: misc.hh:940
gem5::X86ISA::LongModePTE::present
void present(bool p)
Definition: pagetable.hh:162
gem5::X86ISA::g
Bitfield< 8 > g
Definition: pagetable.hh:143
bitunion.hh
gem5::X86ISA::ps
Bitfield< 7 > ps
Definition: pagetable.hh:144
port_proxy.hh
gem5::X86ISA::BitUnion64
BitUnion64(VAddr) Bitfield< 20
gem5::PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:86
gem5::X86ISA::TlbEntry::uncacheable
bool uncacheable
Definition: pagetable.hh:84
gem5::X86ISA::LongModePTE::reset
void reset(Addr _paddr, bool _present=true, bool _uncacheable=false, bool _readonly=false)
Definition: pagetable.hh:179
page_size.hh
gem5::SparcISA::PageTableEntry
Definition: pagetable.hh:68
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::pael1
Bitfield< 20, 12 > pael1
Definition: pagetable.hh:128
gem5::X86ISA::TlbEntry::global
bool global
Definition: pagetable.hh:86
gem5::X86ISA::TlbEntry::paddr
Addr paddr
Definition: pagetable.hh:68
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::w
Bitfield< 1 > w
Definition: pagetable.hh:150
gem5::X86ISA::longl4
Bitfield< 47, 39 > longl4
Definition: pagetable.hh:126
gem5::X86ISA::LongModePTE::paddr
void paddr(Addr addr)
Definition: pagetable.hh:159
gem5::X86ISA::pael3
Bitfield< 31, 30 > pael3
Definition: pagetable.hh:130
gem5::X86ISA::LongModePTE
Definition: pagetable.hh:155
gem5::X86ISA::TlbEntry::vaddr
Addr vaddr
Definition: pagetable.hh:71
gem5::X86ISA::LongModePTE::tableSize
static int tableSize()
Definition: pagetable.hh:193
gem5::X86ISA::LongModePTE::uncacheable
void uncacheable(bool u)
Definition: pagetable.hh:165
gem5::X86ISA::TlbEntry::lruSeq
uint64_t lruSeq
Definition: pagetable.hh:92
gem5::X86ISA::avl
Bitfield< 11, 9 > avl
Definition: pagetable.hh:142
types.hh
gem5::X86ISA::d
Bitfield< 6 > d
Definition: pagetable.hh:145
gem5::X86ISA::TlbEntry::logBytes
unsigned logBytes
Definition: pagetable.hh:73
gem5::X86ISA::norml2
Bitfield< 31, 22 > norml2
Definition: pagetable.hh:133
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::LongModePTE::pte
PageTableEntry pte
Definition: pagetable.hh:199
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::pwt
Bitfield< 3 > pwt
Definition: pagetable.hh:148
gem5::X86ISA::longl2
Bitfield< 29, 21 > longl2
Definition: pagetable.hh:124
gem5::X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
gem5::X86ISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: pagetable.cc:81
gem5::X86ISA::TlbEntry::TlbEntry
TlbEntry()
Definition: pagetable.cc:51
gem5::X86ISA::TlbEntry::noExec
bool noExec
Definition: pagetable.hh:90
trie.hh
gem5::X86ISA::a
Bitfield< 5 > a
Definition: pagetable.hh:146
gem5::X86ISA::TlbEntry::updateVaddr
void updateVaddr(Addr new_vaddr)
Definition: pagetable.hh:101
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::LongModePTE::readonly
bool readonly()
Definition: pagetable.hh:167

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