gem5  v21.1.0.2
i8237.cc
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28 
29 #include "dev/x86/i8237.hh"
30 
31 #include "base/cprintf.hh"
32 #include "mem/packet.hh"
33 #include "mem/packet_access.hh"
34 
35 namespace gem5
36 {
37 
38 namespace X86ISA
39 {
40 
41 namespace
42 {
43 
44 I8237::Register::ReadFunc
45 readUnimpl(const std::string &label)
46 {
47  return [label](I8237::Register &reg) -> uint8_t {
48  panic("Read from i8237 %s unimplemented.", label);
49  };
50 }
51 
52 I8237::Register::WriteFunc
53 writeUnimpl(const std::string &label)
54 {
55  return [label](I8237::Register &reg, const uint8_t &value) {
56  panic("Write to i8237 %s unimplemented.", label);
57  };
58 }
59 
60 } // anonymous namespace
61 
63  Register(csprintf("channel %d current address", channel.number))
64 {
65  reader(readUnimpl(name()));
66  writer(writeUnimpl(name()));
67 }
68 
70  Register(csprintf("channel %d remaining word count", channel.number))
71 {
72  reader(readUnimpl(name()));
73  writer(writeUnimpl(name()));
74 }
75 
76 I8237::WriteOnlyReg::WriteOnlyReg(const std::string &new_name, Addr offset) :
77  Register(new_name)
78 {
79  reader([offset](I8237::Register &reg) -> uint8_t {
80  panic("Illegal read from i8237 register %d.", offset);
81  });
82 }
83 
84 I8237::I8237(const Params &p) : BasicPioDevice(p, 16), latency(p.pio_latency),
85  regs("registers", pioAddr), channels{{{0}, {1}, {2}, {3}}},
86  statusCommandReg("status/command"),
87  requestReg("request", 0x9),
88  setMaskBitReg("set mask bit", 0xa),
89  modeReg("mode", 0xb),
90  clearFlipFlopReg("clear flip-flop", 0xc),
91  temporaryMasterClearReg("temporary/maskter clear"),
92  clearMaskReg("clear mask", 0xe),
93  writeMaskReg("write mask", 0xf)
94 {
95  // Add the channel address and remaining registers.
96  for (auto &channel: channels)
97  regs.addRegisters({ channel.addrReg, channel.remainingReg });
98 
99  // Add the other registers individually.
100  regs.addRegisters({
101  statusCommandReg.
102  reader(readUnimpl("status register")).
103  writer(writeUnimpl("command register")),
104 
105  requestReg.
106  writer(writeUnimpl("request register")),
107 
108  setMaskBitReg.
109  writer(this, &I8237::setMaskBit),
110 
111  modeReg.
112  writer(writeUnimpl("mode register")),
113 
114  clearFlipFlopReg.
115  writer(writeUnimpl("clear LSB/MSB flip-flop register")),
116 
117  temporaryMasterClearReg.
118  reader(readUnimpl("temporary register")).
119  writer(writeUnimpl("master clear register")),
120 
121  clearMaskReg.
122  writer(writeUnimpl("clear mask register")),
123 
124  writeMaskReg.
125  writer(writeUnimpl("write all mask register bits"))
126  });
127 }
128 
129 void
130 I8237::setMaskBit(Register &reg, const uint8_t &command)
131 {
132  uint8_t select = bits(command, 1, 0);
133  uint8_t bitVal = bits(command, 2);
134  if (!bitVal)
135  panic("Turning on i8237 channels unimplemented.");
136  replaceBits(maskReg, select, bitVal);
137 }
138 
139 Tick
141 {
142  regs.read(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
143  pkt->makeAtomicResponse();
144  return latency;
145 }
146 
147 Tick
149 {
150  regs.write(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
151  pkt->makeAtomicResponse();
152  return latency;
153 }
154 
155 void
157 {
159 }
160 
161 void
163 {
165 }
166 
167 } // namespace X86ISA
168 } // namespace gem5
gem5::X86ISA::I8237::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8237.cc:162
gem5::X86ISA::I8237::latency
Tick latency
Definition: i8237.hh:50
gem5::BasicPioDevice::pioAddr
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:151
gem5::PowerISA::xe
Bitfield< 4 > xe
Definition: misc.hh:98
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::X86ISA::I8237::Channel
Definition: i8237.hh:55
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::X86ISA::I8237::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8237.cc:156
gem5::X86ISA::offset
offset
Definition: misc.hh:1030
gem5::RegisterBank::write
virtual void write(Addr addr, const void *buf, Addr bytes)
Definition: reg_bank.hh:884
gem5::X86ISA::I8237::WriteOnlyReg::WriteOnlyReg
WriteOnlyReg(const std::string &new_name, Addr offset)
Definition: i8237.cc:76
gem5::X86ISA::I8237::Channel::number
int number
Definition: i8237.hh:69
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::X86ISA::I8237::channels
std::array< Channel, 4 > channels
Definition: i8237.hh:84
packet.hh
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::RegisterBank::RegisterBase::name
virtual const std::string & name() const
Definition: reg_bank.hh:332
writer
Definition: test.h:47
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::X86ISA::I8237::maskReg
uint8_t maskReg
Definition: i8237.hh:51
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
i8237.hh
gem5::X86ISA::I8237::Channel::ChannelAddrReg::ChannelAddrReg
ChannelAddrReg(Channel &)
Definition: i8237.cc:62
gem5::X86ISA::I8237::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8237.cc:148
cprintf.hh
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::I8237::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8237.cc:140
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::I8237::Channel::ChannelRemainingReg::ChannelRemainingReg
ChannelRemainingReg(Channel &)
Definition: i8237.cc:69
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
packet_access.hh
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::RegisterBank::read
virtual void read(Addr addr, void *buf, Addr bytes)
Definition: reg_bank.hh:827
gem5::RegisterBank::Register::reader
constexpr This & reader(const ReadFunc &new_reader)
Definition: reg_bank.hh:612
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::I8237::Register
RegisterBankLE::Register8 Register
Definition: i8237.hh:47
gem5::X86ISA::I8237::regs
RegisterBankLE regs
Definition: i8237.hh:53
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::X86ISA::I8237::setMaskBit
void setMaskBit(Register &reg, const uint8_t &command)
Definition: i8237.cc:130
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::X86ISA::I8237::I8237
I8237(const Params &p)
Definition: i8237.cc:84
gem5::RegisterBank::Register::writer
constexpr This & writer(const WriteFunc &new_writer)
Definition: reg_bank.hh:627
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1184

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