gem5 v24.0.0.0
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#include <isa.hh>
Public Types | |
using | Params = X86ISAParams |
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typedef std::vector< const RegClass * > | RegClasses |
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typedef SimObjectParams | Params |
Public Member Functions | |
void | clear () override |
PCStateBase * | newPCState (Addr new_inst_addr=0) const override |
ISA (const Params &p) | |
RegVal | readMiscRegNoEffect (RegIndex idx) const override |
RegVal | readMiscReg (RegIndex idx) override |
void | setMiscRegNoEffect (RegIndex idx, RegVal val) override |
void | setMiscReg (RegIndex idx, RegVal val) override |
bool | inUserMode () const override |
void | copyRegsFrom (ThreadContext *src) override |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
void | setThreadContext (ThreadContext *_tc) override |
std::string | getVendorString () const |
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virtual void | takeOverFrom (ThreadContext *new_tc, ThreadContext *old_tc) |
virtual uint64_t | getExecutingAsid () const |
virtual void | resetThread () |
const RegClasses & | regClasses () const |
const std::string | getIsaName () const |
virtual void | handleLockedRead (const RequestPtr &req) |
virtual void | handleLockedRead (ExecContext *xc, const RequestPtr &req) |
virtual bool | handleLockedWrite (const RequestPtr &req, Addr cacheBlockMask) |
virtual bool | handleLockedWrite (ExecContext *xc, const RequestPtr &req, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoop (ExecContext *xc, PacketPtr pkt, Addr cacheBlockMask) |
virtual void | handleLockedSnoopHit () |
virtual void | handleLockedSnoopHit (ExecContext *xc) |
virtual void | globalClearExclusive () |
virtual void | globalClearExclusive (ExecContext *xc) |
virtual int64_t | getVectorLengthInBytes () const |
This function returns the vector length of the Vector Length Agnostic extension of the ISA. | |
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const Params & | params () const |
SimObject (const Params &p) | |
virtual | ~SimObject () |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. | |
virtual void | regProbePoints () |
Register probe points for this object. | |
virtual void | regProbeListeners () |
Register probe listeners for this object. | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. | |
virtual void | startup () |
startup() is the final initialization call before simulation. | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. | |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
Event manger manages events in the event queue. | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. | |
virtual void | notifyFork () |
Notify a child process of a fork. | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. | |
virtual void | resetStats () |
Callback to reset stats. | |
virtual void | preDumpStats () |
Callback before stats are dumped. | |
void | addStat (statistics::Info *info) |
Register a stat with this group. | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. | |
void | mergeStatGroup (Group *block) |
Merge the contents (stats & children) of a block to this block. | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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Named (const std::string &name_) | |
virtual | ~Named ()=default |
virtual std::string | name () const |
Public Attributes | |
std::unique_ptr< X86CPUID > | cpuid |
Private Member Functions | |
void | updateHandyM5Reg (Efer efer, CR0 cr0, SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) |
Private Attributes | |
RegVal | regVal [misc_reg::NumRegs] |
std::string | vendorString |
Additional Inherited Members | |
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static void | serializeAll (const std::string &cpt_dir) |
Create a checkpoint by serializing all SimObjects in the system. | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. | |
static void | setSimObjectResolver (SimObjectResolver *resolver) |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
static SimObjectResolver * | getSimObjectResolver () |
There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. | |
static void | generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream) |
Generate a checkpoint file so that the serialization can be routed to it. | |
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BaseISA (const SimObjectParams &p, const std::string &name) | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. | |
void | signalDrainDone () const |
Signal that an object is drained. | |
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ThreadContext * | tc = nullptr |
RegClasses | _regClasses |
std::string | isaName |
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const SimObjectParams & | _params |
Cached copy of the object parameters. | |
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EventQueue * | eventq |
A pointer to this object's event queue. | |
using gem5::X86ISA::ISA::Params = X86ISAParams |
gem5::X86ISA::ISA::ISA | ( | const Params & | p | ) |
Definition at line 154 of file isa.cc.
References gem5::BaseISA::_regClasses, gem5::X86ISA::APMInfo, gem5::X86ISA::CacheParams, gem5::ArmISA::ccRegClass, clear(), cpuid, gem5::X86ISA::ExtendedFeatures, gem5::X86ISA::ExtendedState, gem5::X86ISA::FamilyModelStepping, gem5::X86ISA::FamilyModelSteppingBrandFeatures, gem5::X86ISA::flatFloatRegClass, gem5::X86ISA::flatIntRegClass, gem5::X86ISA::L1CacheAndTLB, gem5::X86ISA::L2L3CacheAndL2TLB, gem5::X86ISA::LongModeAddressSize, gem5::ArmISA::matRegClass, gem5::ArmISA::miscRegClass, gem5::X86ISA::p, gem5::ArmISA::vecElemClass, gem5::ArmISA::vecPredRegClass, and gem5::ArmISA::vecRegClass.
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 112 of file isa.cc.
References gem5::X86ISA::misc_reg::ApicBase, gem5::X86ISA::misc_reg::Cr0, gem5::X86ISA::misc_reg::Dr6, gem5::X86ISA::misc_reg::Dr7, gem5::X86ISA::mask, gem5::X86ISA::misc_reg::McgCap, gem5::X86ISA::misc_reg::Mtrrcap, gem5::X86ISA::misc_reg::NumRegs, gem5::X86ISA::misc_reg::Pat, regVal, gem5::X86ISA::misc_reg::Syscfg, and gem5::X86ISA::misc_reg::TopMem.
Referenced by ISA().
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overridevirtual |
Implements gem5::BaseISA.
Definition at line 202 of file isa.cc.
References gem5::ArmISA::ccRegClass, gem5::X86ISA::copyMiscRegs(), gem5::X86ISA::flatFloatRegClass, gem5::X86ISA::flatIntRegClass, gem5::ThreadContext::getReg(), gem5::ThreadContext::pcState(), gem5::ThreadContext::setReg(), and gem5::BaseISA::tc.
std::string gem5::X86ISA::ISA::getVendorString | ( | ) | const |
Definition at line 524 of file isa.cc.
References vendorString.
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inlineoverridevirtual |
Implements gem5::BaseISA.
Definition at line 83 of file isa.hh.
References gem5::X86ISA::misc_reg::M5Reg, and readMiscRegNoEffect().
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inlineoverridevirtual |
Implements gem5::BaseISA.
Implements gem5::BaseISA.
Definition at line 229 of file isa.cc.
References gem5::X86ISA::misc_reg::ApicBase, gem5::X86ISA::base, gem5::ThreadContext::contextId(), gem5::Clocked::curCycle(), gem5::X86ISA::misc_reg::Fsw, gem5::ThreadContext::getCpuPtr(), gem5::insertBits(), readMiscRegNoEffect(), regVal, gem5::BaseISA::tc, gem5::X86ISA::misc_reg::Tsc, gem5::X86ISA::misc_reg::X87Top, and gem5::X86ISA::misc_reg::Xcr0.
Implements gem5::BaseISA.
Definition at line 218 of file isa.cc.
References gem5::X86ISA::misc_reg::isValid(), and regVal.
Referenced by gem5::X86ISA::FloatRegClassOps::flatten(), inUserMode(), and readMiscReg().
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overridevirtual |
Serialize an object.
Output an object's state into the current checkpoint section.
cp | Checkpoint state |
Reimplemented from gem5::BaseISA.
Definition at line 498 of file isa.cc.
References gem5::X86ISA::misc_reg::NumRegs, regVal, gem5::BaseISA::serialize(), and SERIALIZE_ARRAY.
Implements gem5::BaseISA.
Definition at line 297 of file isa.cc.
References gem5::X86ISA::misc_reg::Cr0, gem5::X86ISA::misc_reg::Cr2, gem5::X86ISA::misc_reg::Cr3, gem5::X86ISA::misc_reg::Cr4, gem5::X86ISA::misc_reg::Cr8, gem5::X86ISA::misc_reg::CsAttr, gem5::X86ISA::misc_reg::CsBase, gem5::X86ISA::misc_reg::CsEffBase, gem5::Clocked::curCycle(), gem5::X86ISA::misc_reg::Dr0, gem5::X86ISA::misc_reg::Dr1, gem5::X86ISA::misc_reg::Dr2, gem5::X86ISA::misc_reg::Dr3, gem5::X86ISA::misc_reg::Dr4, gem5::X86ISA::misc_reg::Dr5, gem5::X86ISA::misc_reg::Dr6, gem5::X86ISA::misc_reg::Dr7, gem5::X86ISA::misc_reg::DsBase, gem5::X86ISA::misc_reg::DsEffBase, gem5::X86ISA::misc_reg::Efer, gem5::X86ISA::misc_reg::EsBase, gem5::X86ISA::misc_reg::EsEffBase, gem5::BaseMMU::flushAll(), gem5::X86ISA::misc_reg::FsBase, gem5::ThreadContext::getCpuPtr(), gem5::ThreadContext::getMMUPtr(), gem5::X86ISA::misc_reg::GsBase, gem5::X86ISA::misc_reg::HsBase, gem5::X86ISA::misc_reg::IdtrBase, gem5::X86ISA::misc_reg::M5Reg, panic, panic_if, regVal, gem5::X86ISA::misc_reg::Rflags, gem5::X86ISA::misc_reg::SegBaseBase, gem5::X86ISA::misc_reg::segEffBase(), setMiscRegNoEffect(), gem5::X86ISA::misc_reg::SsAttr, gem5::X86ISA::misc_reg::SsBase, gem5::X86ISA::misc_reg::SsEffBase, gem5::BaseISA::tc, gem5::X86ISA::misc_reg::TrBase, gem5::X86ISA::misc_reg::Tsc, gem5::X86ISA::misc_reg::TsgBase, gem5::X86ISA::misc_reg::TslBase, updateHandyM5Reg(), gem5::X86ISA::val, and gem5::X86ISA::misc_reg::Xcr0.
Implements gem5::BaseISA.
Definition at line 255 of file isa.cc.
References gem5::X86ISA::misc_reg::Fcw, gem5::X86ISA::misc_reg::Fioff, gem5::X86ISA::misc_reg::Fiseg, gem5::X86ISA::misc_reg::Fooff, gem5::X86ISA::misc_reg::Fop, gem5::X86ISA::misc_reg::Foseg, gem5::X86ISA::misc_reg::Fsw, gem5::X86ISA::misc_reg::Ftw, gem5::X86ISA::misc_reg::isValid(), gem5::X86ISA::misc_reg::M5Reg, gem5::X86ISA::mask, gem5::X86ISA::misc_reg::Mxcsr, regVal, gem5::X86ISA::SixtyFourBitMode, gem5::X86ISA::val, and gem5::X86ISA::misc_reg::X87Top.
Referenced by setMiscReg().
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overridevirtual |
Reimplemented from gem5::BaseISA.
Definition at line 517 of file isa.cc.
References gem5::InstDecoder::as(), gem5::ThreadContext::getDecoderPtr(), gem5::X86ISA::misc_reg::M5Reg, regVal, gem5::BaseISA::setThreadContext(), and gem5::BaseISA::tc.
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overridevirtual |
Unserialize an object.
Read an object's state from the current checkpoint section.
cp | Checkpoint state |
Implements gem5::Serializable.
Definition at line 506 of file isa.cc.
References gem5::X86ISA::misc_reg::Cr0, gem5::X86ISA::misc_reg::CsAttr, gem5::X86ISA::misc_reg::Efer, gem5::X86ISA::misc_reg::NumRegs, regVal, gem5::X86ISA::misc_reg::Rflags, gem5::X86ISA::misc_reg::SsAttr, UNSERIALIZE_ARRAY, and updateHandyM5Reg().
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private |
Definition at line 51 of file isa.cc.
References gem5::InstDecoder::as(), gem5::X86ISA::CompatabilityMode, gem5::ThreadContext::getDecoderPtr(), gem5::X86ISA::misc_reg::M5Reg, gem5::X86ISA::ProtectedMode, gem5::X86ISA::RealMode, regVal, gem5::X86ISA::SixtyFourBitMode, gem5::BaseISA::tc, and gem5::X86ISA::Virtual8086Mode.
Referenced by setMiscReg(), and unserialize().
std::unique_ptr<X86CPUID> gem5::X86ISA::ISA::cpuid |
Definition at line 98 of file isa.hh.
Referenced by ISA(), and gem5::X86KvmCPU::updateCPUID().
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private |
Definition at line 57 of file isa.hh.
Referenced by clear(), readMiscReg(), readMiscRegNoEffect(), serialize(), setMiscReg(), setMiscRegNoEffect(), setThreadContext(), unserialize(), and updateHandyM5Reg().
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private |
Definition at line 61 of file isa.hh.
Referenced by getVendorString().