gem5  v21.1.0.2
intdev.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2008 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef __DEV_X86_INTDEV_HH__
42 #define __DEV_X86_INTDEV_HH__
43 
44 #include <cassert>
45 #include <functional>
46 #include <string>
47 
48 #include "base/cast.hh"
49 #include "mem/tport.hh"
50 #include "sim/sim_object.hh"
51 
52 namespace gem5
53 {
54 
55 namespace X86ISA
56 {
57 
58 template <class Device>
60 {
61  Device * device;
62 
63  public:
64  IntResponsePort(const std::string& _name, SimObject* _parent,
65  Device* dev) :
66  SimpleTimingPort(_name, _parent), device(dev)
67  {
68  }
69 
71  getAddrRanges() const
72  {
73  return device->getIntAddrRange();
74  }
75 
76  Tick
78  {
80  "%s received unexpected command %s from %s.\n",
81  name(), pkt->cmd.toString(), getPeer());
82  pkt->headerDelay = pkt->payloadDelay = 0;
83  return device->recvMessage(pkt);
84  }
85 };
86 
87 template<class T>
90 {
91  RequestPtr req = std::make_shared<Request>(
93  PacketPtr pkt = new Packet(req, MemCmd::WriteReq);
94  pkt->allocate();
95  pkt->setRaw<T>(payload);
96  return pkt;
97 }
98 
99 template <class Device>
101 {
102  private:
105 
106  Device* device;
108 
109  typedef std::function<void(PacketPtr)> OnCompletionFunc;
111  {
113  OnCompletion(OnCompletionFunc _func) : func(_func) {}
114  };
115  // If nothing extra needs to happen, just clean up the packet.
116  static void defaultOnCompletion(PacketPtr pkt) { delete pkt; }
117 
118  public:
119  IntRequestPort(const std::string& _name, SimObject* _parent,
120  Device* dev, Tick _latency) :
121  QueuedRequestPort(_name, _parent, reqQueue, snoopRespQueue),
122  reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
123  device(dev), latency(_latency)
124  {
125  }
126 
127  bool
128  recvTimingResp(PacketPtr pkt) override
129  {
130  assert(pkt->isResponse());
131  auto *oc = safe_cast<OnCompletion *>(pkt->popSenderState());
132  oc->func(pkt);
133  delete oc;
134  return true;
135  }
136 
137  void
138  sendMessage(PacketPtr pkt, bool timing,
140  {
141  if (timing) {
142  pkt->pushSenderState(new OnCompletion(func));
143  schedTimingReq(pkt, curTick() + latency);
144  // The target handles cleaning up the packet in timing mode.
145  } else {
146  // ignore the latency involved in the atomic transaction
147  sendAtomic(pkt);
148  func(pkt);
149  }
150  }
151 };
152 
153 } // namespace X86ISA
154 } // namespace gem5
155 
156 #endif //__DEV_X86_INTDEV_HH__
gem5::X86ISA::IntRequestPort::sendMessage
void sendMessage(PacketPtr pkt, bool timing, OnCompletionFunc func=defaultOnCompletion)
Definition: intdev.hh:138
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Port::getPeer
Port & getPeer()
Return a reference to this port's peer.
Definition: port.hh:108
gem5::X86ISA::IntRequestPort::IntRequestPort
IntRequestPort(const std::string &_name, SimObject *_parent, Device *dev, Tick _latency)
Definition: intdev.hh:119
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::Packet::setRaw
void setRaw(T v)
Set the value in the data pointer to v without byte swapping.
Definition: packet_access.hh:61
gem5::QueuedRequestPort
The QueuedRequestPort combines two queues, a request queue and a snoop response queue,...
Definition: qport.hh:109
gem5::Packet::pushSenderState
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
Definition: packet.cc:316
gem5::Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:125
gem5::RequestPort::sendAtomic
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time,...
Definition: port.hh:464
cast.hh
gem5::X86ISA::IntRequestPort::OnCompletionFunc
std::function< void(PacketPtr)> OnCompletionFunc
Definition: intdev.hh:109
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
gem5::X86ISA::IntResponsePort::recvAtomic
Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the peer.
Definition: intdev.hh:77
gem5::SimpleTimingPort
The simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvA...
Definition: tport.hh:62
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::X86ISA::IntRequestPort
Definition: intdev.hh:100
gem5::X86ISA::IntRequestPort::device
Device * device
Definition: intdev.hh:106
sim_object.hh
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::X86ISA::IntRequestPort::OnCompletion::OnCompletion
OnCompletion(OnCompletionFunc _func)
Definition: intdev.hh:113
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::X86ISA::buildIntPacket
PacketPtr buildIntPacket(Addr addr, T payload)
Definition: intdev.hh:89
gem5::X86ISA::IntRequestPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: intdev.hh:128
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::IntRequestPort::snoopRespQueue
SnoopRespPacketQueue snoopRespQueue
Definition: intdev.hh:104
gem5::Packet::popSenderState
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
Definition: packet.cc:324
gem5::MemCmd::toString
const std::string & toString() const
Return the string to a cmd given by idx.
Definition: packet.hh:265
gem5::X86ISA::IntRequestPort::reqQueue
ReqPacketQueue reqQueue
Definition: intdev.hh:103
gem5::X86ISA::IntRequestPort::OnCompletion::func
OnCompletionFunc func
Definition: intdev.hh:112
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::X86ISA::IntResponsePort::getAddrRanges
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: intdev.hh:71
gem5::X86ISA::IntResponsePort::IntResponsePort
IntResponsePort(const std::string &_name, SimObject *_parent, Device *dev)
Definition: intdev.hh:64
gem5::Packet::allocate
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1326
tport.hh
gem5::X86ISA::IntResponsePort
Definition: intdev.hh:59
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::X86ISA::IntRequestPort::OnCompletion
Definition: intdev.hh:110
gem5::X86ISA::IntResponsePort::device
Device * device
Definition: intdev.hh:61
gem5::ReqPacketQueue
Definition: packet_queue.hh:226
gem5::QueuedRequestPort::schedTimingReq
void schedTimingReq(PacketPtr pkt, Tick when)
Schedule the sending of a timing request.
Definition: qport.hh:149
std::list< AddrRange >
gem5::SnoopRespPacketQueue
Definition: packet_queue.hh:262
gem5::X86ISA::IntRequestPort::defaultOnCompletion
static void defaultOnCompletion(PacketPtr pkt)
Definition: intdev.hh:116
gem5::Request::intRequestorId
@ intRequestorId
This requestor id is used for message signaled interrupts.
Definition: request.hh:262
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::IntRequestPort::latency
Tick latency
Definition: intdev.hh:107
gem5::Packet::isResponse
bool isResponse() const
Definition: packet.hh:587
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

Generated on Tue Sep 21 2021 12:25:23 for gem5 by doxygen 1.8.17