gem5  v22.1.0.0
ltage.hh
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1 /*
2  * Copyright (c) 2014 The University of Wisconsin
3  *
4  * Copyright (c) 2006 INRIA (Institut National de Recherche en
5  * Informatique et en Automatique / French National Research Institute
6  * for Computer Science and Applied Mathematics)
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33 
34 /* @file
35  * Implementation of a L-TAGE branch predictor. TAGE is a global-history based
36  * branch predictor. It features a PC-indexed bimodal predictor and N
37  * partially tagged tables, indexed with a hash of the PC and the global
38  * branch history. The different lengths of global branch history used to
39  * index the partially tagged tables grow geometrically. A small path history
40  * is also used in the hash. L-TAGE also features a loop predictor that records
41  * iteration count of loops and predicts accordingly.
42  *
43  * All TAGE tables are accessed in parallel, and the one using the longest
44  * history that matches provides the prediction (some exceptions apply).
45  * Entries are allocated in components using a longer history than the
46  * one that predicted when the prediction is incorrect.
47  */
48 
49 #ifndef __CPU_PRED_LTAGE_HH__
50 #define __CPU_PRED_LTAGE_HH__
51 
52 
53 #include <vector>
54 
55 #include "base/types.hh"
57 #include "cpu/pred/tage.hh"
58 #include "params/LTAGE.hh"
59 
60 namespace gem5
61 {
62 
63 namespace branch_prediction
64 {
65 
66 class LTAGE : public TAGE
67 {
68  public:
69  LTAGE(const LTAGEParams &params);
70 
71  // Base class methods.
72  void squash(ThreadID tid, void *bp_history) override;
73  void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
74  bool squashed, const StaticInstPtr & inst,
75  Addr corrTarget) override;
76 
77  void init() override;
78 
79  protected:
82 
83  // more provider types
84  enum
85  {
88  };
89 
90  // Primary branch history entry
92  {
95  : TageBranchInfo(tage), lpBranchInfo(lp.makeBranchInfo())
96  {}
97 
98  virtual ~LTageBranchInfo()
99  {
100  delete lpBranchInfo;
101  }
102  };
103 
114  bool predict(
115  ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) override;
116 };
117 
118 } // namespace branch_prediction
119 } // namespace gem5
120 
121 #endif // __CPU_PRED_LTAGE_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
void squash(ThreadID tid, void *bp_history) override
Definition: ltage.cc:139
void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, bool squashed, const StaticInstPtr &inst, Addr corrTarget) override
Updates the BP with taken/not taken information.
Definition: ltage.cc:97
LTAGE(const LTAGEParams &params)
Definition: ltage.cc:53
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: ltage.cc:59
bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) override
Get a branch prediction from LTAGE.
Definition: ltage.cc:66
LoopPredictor * loopPredictor
The loop predictor object.
Definition: ltage.hh:81
const Params & params() const
Definition: sim_object.hh:176
Bitfield< 7 > b
Definition: misc_types.hh:388
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
LoopPredictor::BranchInfo * lpBranchInfo
Definition: ltage.hh:93
LTageBranchInfo(TAGEBase &tage, LoopPredictor &lp)
Definition: ltage.hh:94

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