gem5 v24.0.0.0
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ltage.hh
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1/*
2 * Copyright (c) 2022-2023 The University of Edinburgh
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2014 The University of Wisconsin
15 *
16 * Copyright (c) 2006 INRIA (Institut National de Recherche en
17 * Informatique et en Automatique / French National Research Institute
18 * for Computer Science and Applied Mathematics)
19 *
20 * All rights reserved.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are
24 * met: redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer;
26 * redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution;
29 * neither the name of the copyright holders nor the names of its
30 * contributors may be used to endorse or promote products derived from
31 * this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46/* @file
47 * Implementation of a L-TAGE branch predictor. TAGE is a global-history based
48 * branch predictor. It features a PC-indexed bimodal predictor and N
49 * partially tagged tables, indexed with a hash of the PC and the global
50 * branch history. The different lengths of global branch history used to
51 * index the partially tagged tables grow geometrically. A small path history
52 * is also used in the hash. L-TAGE also features a loop predictor that records
53 * iteration count of loops and predicts accordingly.
54 *
55 * All TAGE tables are accessed in parallel, and the one using the longest
56 * history that matches provides the prediction (some exceptions apply).
57 * Entries are allocated in components using a longer history than the
58 * one that predicted when the prediction is incorrect.
59 */
60
61#ifndef __CPU_PRED_LTAGE_HH__
62#define __CPU_PRED_LTAGE_HH__
63
64
65#include <vector>
66
67#include "base/types.hh"
69#include "cpu/pred/tage.hh"
70#include "params/LTAGE.hh"
71
72namespace gem5
73{
74
75namespace branch_prediction
76{
77
78class LTAGE : public TAGE
79{
80 public:
81 LTAGE(const LTAGEParams &params);
82
83 // Base class methods.
84 void squash(ThreadID tid, void * &bp_history) override;
85 void update(ThreadID tid, Addr pc, bool taken,
86 void * &bp_history, bool squashed,
87 const StaticInstPtr & inst, Addr target) override;
88
89 void init() override;
90
91 protected:
94
95 // more provider types
96 enum
97 {
100 };
101
102 // Primary branch history entry
104 {
107 : TageBranchInfo(tage), lpBranchInfo(lp.makeBranchInfo())
108 {}
109
111 {
112 delete lpBranchInfo;
113 lpBranchInfo = nullptr;
114 }
115 };
116
127 bool predict(
128 ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) override;
129};
130
131} // namespace branch_prediction
132} // namespace gem5
133
134#endif // __CPU_PRED_LTAGE_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
void update(ThreadID tid, Addr pc, bool taken, void *&bp_history, bool squashed, const StaticInstPtr &inst, Addr target) override
Updates the BP with taken/not taken information.
Definition ltage.cc:109
LTAGE(const LTAGEParams &params)
Definition ltage.cc:65
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition ltage.cc:71
bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) override
Get a branch prediction from LTAGE.
Definition ltage.cc:78
LoopPredictor * loopPredictor
The loop predictor object.
Definition ltage.hh:93
void squash(ThreadID tid, void *&bp_history) override
Definition ltage.cc:152
const Params & params() const
Bitfield< 7 > b
Bitfield< 4 > pc
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
LoopPredictor::BranchInfo * lpBranchInfo
Definition ltage.hh:105
LTageBranchInfo(TAGEBase &tage, LoopPredictor &lp)
Definition ltage.hh:106

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