gem5 v24.0.0.0
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ltage.cc
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1/*
2 * Copyright (c) 2022-2023 The University of Edinburgh
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2014 The University of Wisconsin
15 *
16 * Copyright (c) 2006 INRIA (Institut National de Recherche en
17 * Informatique et en Automatique / French National Research Institute
18 * for Computer Science and Applied Mathematics)
19 *
20 * All rights reserved.
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31 * this software without specific prior written permission.
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33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 */
45
46/* @file
47 * Implementation of a L-TAGE branch predictor
48 */
49
50#include "cpu/pred/ltage.hh"
51
52#include "base/intmath.hh"
53#include "base/logging.hh"
54#include "base/random.hh"
55#include "base/trace.hh"
56#include "debug/Fetch.hh"
57#include "debug/LTage.hh"
58
59namespace gem5
60{
61
62namespace branch_prediction
63{
64
65LTAGE::LTAGE(const LTAGEParams &params)
66 : TAGE(params), loopPredictor(params.loop_predictor)
67{
68}
69
70void
72{
73 TAGE::init();
74}
75
76//prediction
77bool
78LTAGE::predict(ThreadID tid, Addr branch_pc, bool cond_branch, void* &b)
79{
81 b = (void*)(bi);
82
83 bool pred_taken = tage->tagePredict(tid, branch_pc, cond_branch,
84 bi->tageBranchInfo);
85
86 pred_taken = loopPredictor->loopPredict(tid, branch_pc, cond_branch,
87 bi->lpBranchInfo, pred_taken,
89 if (cond_branch) {
90 if (bi->lpBranchInfo->loopPredUsed) {
91 bi->tageBranchInfo->provider = LOOP;
92 }
93 DPRINTF(LTage, "Predict for %lx: taken?:%d, loopTaken?:%d, "
94 "loopValid?:%d, loopUseCounter:%d, tagePred:%d, altPred:%d\n",
95 branch_pc, pred_taken, bi->lpBranchInfo->loopPred,
96 bi->lpBranchInfo->loopPredValid,
98 bi->tageBranchInfo->tagePred, bi->tageBranchInfo->altTaken);
99 }
100
101 // record final prediction
102 bi->lpBranchInfo->predTaken = pred_taken;
103
104 return pred_taken;
105}
106
107// PREDICTOR UPDATE
108void
109LTAGE::update(ThreadID tid, Addr pc, bool taken, void * &bp_history,
110 bool squashed, const StaticInstPtr & inst, Addr target)
111{
112 assert(bp_history);
113
114 LTageBranchInfo* bi = static_cast<LTageBranchInfo*>(bp_history);
115
116 if (squashed) {
118 // This restores the global history, then update it
119 // and recomputes the folded histories.
120 tage->squash(tid, taken, bi->tageBranchInfo, target);
121
122 if (bi->tageBranchInfo->condBranch) {
123 loopPredictor->squashLoop(bi->lpBranchInfo);
124 }
125 }
126 return;
127 }
128
129 int nrand = random_mt.random<int>() & 3;
130 if (bi->tageBranchInfo->condBranch) {
131 DPRINTF(LTage, "Updating tables for branch:%lx; taken?:%d\n",
132 pc, taken);
133 tage->updateStats(taken, bi->tageBranchInfo);
134
135 loopPredictor->updateStats(taken, bi->lpBranchInfo);
136
137 loopPredictor->condBranchUpdate(tid, pc, taken,
138 bi->tageBranchInfo->tagePred, bi->lpBranchInfo, instShiftAmt);
139
140 tage->condBranchUpdate(tid, pc, taken, bi->tageBranchInfo,
141 nrand, target, bi->lpBranchInfo->predTaken);
142 }
143
144 tage->updateHistories(tid, pc, taken, bi->tageBranchInfo, false,
145 inst, target);
146
147 delete bi;
148 bp_history = nullptr;
149}
150
151void
152LTAGE::squash(ThreadID tid, void * &bp_history)
153{
154 LTageBranchInfo* bi = (LTageBranchInfo*)(bp_history);
155
156 if (bi->tageBranchInfo->condBranch) {
157 loopPredictor->squash(tid, bi->lpBranchInfo);
158 }
159
160 TAGE::squash(tid, bp_history);
161}
162
163} // namespace branch_prediction
164} // namespace gem5
#define DPRINTF(x,...)
Definition trace.hh:210
const unsigned instShiftAmt
Number of bits to shift instructions by for predictor addresses.
void update(ThreadID tid, Addr pc, bool taken, void *&bp_history, bool squashed, const StaticInstPtr &inst, Addr target) override
Updates the BP with taken/not taken information.
Definition ltage.cc:109
LTAGE(const LTAGEParams &params)
Definition ltage.cc:65
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition ltage.cc:71
bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) override
Get a branch prediction from LTAGE.
Definition ltage.cc:78
LoopPredictor * loopPredictor
The loop predictor object.
Definition ltage.hh:93
void squash(ThreadID tid, void *&bp_history) override
Definition ltage.cc:152
void updateStats(bool taken, BranchInfo *bi)
Update the stats.
void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, bool tage_pred, BranchInfo *bi, unsigned instShiftAmt)
Update LTAGE for conditional branches.
int8_t getLoopUseCounter() const
Gets the value of the loop use counter.
bool loopPredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi, bool prev_pred_taken, unsigned instShiftAmt)
Get the loop prediction.
void squash(ThreadID tid, BranchInfo *bi)
virtual void updateHistories(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *b, bool speculative, const StaticInstPtr &inst=nullStaticInstPtr, Addr target=MaxAddr)
(Speculatively) updates global histories (path and direction).
Definition tage_base.cc:588
virtual void updateStats(bool taken, BranchInfo *bi)
Update the stats.
Definition tage_base.cc:662
virtual void squash(ThreadID tid, bool taken, BranchInfo *bi, Addr target)
Restores speculatively updated path and direction histories.
Definition tage_base.cc:629
bool tagePredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi)
TAGE prediction called from TAGE::predict.
Definition tage_base.cc:360
virtual void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *bi, int nrand, Addr corrTarget, bool pred, bool preAdjustAlloc=false)
Update TAGE for conditional branches.
Definition tage_base.cc:514
virtual void squash(ThreadID tid, void *&bp_history) override
Definition tage.cc:102
Random random_mt
Definition random.cc:99
std::enable_if_t< std::is_integral_v< T >, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition random.hh:90
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition sim_object.cc:73
Bitfield< 7 > b
Bitfield< 4 > pc
Bitfield< 20, 16 > bi
Definition types.hh:80
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
int16_t ThreadID
Thread index/ID type.
Definition types.hh:235
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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