gem5  v21.1.0.2
ltage.cc
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33 
34 /* @file
35  * Implementation of a L-TAGE branch predictor
36  */
37 
38 #include "cpu/pred/ltage.hh"
39 
40 #include "base/intmath.hh"
41 #include "base/logging.hh"
42 #include "base/random.hh"
43 #include "base/trace.hh"
44 #include "debug/Fetch.hh"
45 #include "debug/LTage.hh"
46 
47 namespace gem5
48 {
49 
50 namespace branch_prediction
51 {
52 
53 LTAGE::LTAGE(const LTAGEParams &params)
54  : TAGE(params), loopPredictor(params.loop_predictor)
55 {
56 }
57 
58 void
60 {
61  TAGE::init();
62 }
63 
64 //prediction
65 bool
66 LTAGE::predict(ThreadID tid, Addr branch_pc, bool cond_branch, void* &b)
67 {
69  b = (void*)(bi);
70 
71  bool pred_taken = tage->tagePredict(tid, branch_pc, cond_branch,
72  bi->tageBranchInfo);
73 
74  pred_taken = loopPredictor->loopPredict(tid, branch_pc, cond_branch,
75  bi->lpBranchInfo, pred_taken,
76  instShiftAmt);
77  if (cond_branch) {
78  if (bi->lpBranchInfo->loopPredUsed) {
79  bi->tageBranchInfo->provider = LOOP;
80  }
81  DPRINTF(LTage, "Predict for %lx: taken?:%d, loopTaken?:%d, "
82  "loopValid?:%d, loopUseCounter:%d, tagePred:%d, altPred:%d\n",
83  branch_pc, pred_taken, bi->lpBranchInfo->loopPred,
84  bi->lpBranchInfo->loopPredValid,
86  bi->tageBranchInfo->tagePred, bi->tageBranchInfo->altTaken);
87  }
88 
89  // record final prediction
90  bi->lpBranchInfo->predTaken = pred_taken;
91 
92  return pred_taken;
93 }
94 
95 // PREDICTOR UPDATE
96 void
97 LTAGE::update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history,
98  bool squashed, const StaticInstPtr & inst, Addr corrTarget)
99 {
100  assert(bp_history);
101 
102  LTageBranchInfo* bi = static_cast<LTageBranchInfo*>(bp_history);
103 
104  if (squashed) {
106  // This restores the global history, then update it
107  // and recomputes the folded histories.
108  tage->squash(tid, taken, bi->tageBranchInfo, corrTarget);
109 
110  if (bi->tageBranchInfo->condBranch) {
111  loopPredictor->squashLoop(bi->lpBranchInfo);
112  }
113  }
114  return;
115  }
116 
117  int nrand = random_mt.random<int>() & 3;
118  if (bi->tageBranchInfo->condBranch) {
119  DPRINTF(LTage, "Updating tables for branch:%lx; taken?:%d\n",
120  branch_pc, taken);
121  tage->updateStats(taken, bi->tageBranchInfo);
122 
123  loopPredictor->updateStats(taken, bi->lpBranchInfo);
124 
125  loopPredictor->condBranchUpdate(tid, branch_pc, taken,
126  bi->tageBranchInfo->tagePred, bi->lpBranchInfo, instShiftAmt);
127 
128  tage->condBranchUpdate(tid, branch_pc, taken, bi->tageBranchInfo,
129  nrand, corrTarget, bi->lpBranchInfo->predTaken);
130  }
131 
132  tage->updateHistories(tid, branch_pc, taken, bi->tageBranchInfo, false,
133  inst, corrTarget);
134 
135  delete bi;
136 }
137 
138 void
139 LTAGE::squash(ThreadID tid, void *bp_history)
140 {
141  LTageBranchInfo* bi = (LTageBranchInfo*)(bp_history);
142 
143  if (bi->tageBranchInfo->condBranch) {
144  loopPredictor->squash(tid, bi->lpBranchInfo);
145  }
146 
147  TAGE::squash(tid, bp_history);
148 }
149 
150 } // namespace branch_prediction
151 } // namespace gem5
gem5::branch_prediction::TAGEBase::squash
virtual void squash(ThreadID tid, bool taken, BranchInfo *bi, Addr target)
Restores speculatively updated path and direction histories.
Definition: tage_base.cc:629
ltage.hh
gem5::branch_prediction::TAGE::squash
virtual void squash(ThreadID tid, void *bp_history) override
Definition: tage.cc:90
gem5::branch_prediction::TAGEBase::isSpeculativeUpdateEnabled
bool isSpeculativeUpdateEnabled() const
Definition: tage_base.cc:786
gem5::branch_prediction::LoopPredictor::squashLoop
void squashLoop(BranchInfo *bi)
Definition: loop_predictor.cc:310
gem5::branch_prediction::TAGEBase::updateStats
virtual void updateStats(bool taken, BranchInfo *bi)
Update the stats.
Definition: tage_base.cc:662
gem5::SimObject::init
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: sim_object.cc:76
random.hh
gem5::branch_prediction::LTAGE::squash
void squash(ThreadID tid, void *bp_history) override
Definition: ltage.cc:139
gem5::branch_prediction::LoopPredictor::squash
void squash(ThreadID tid, BranchInfo *bi)
Definition: loop_predictor.cc:299
gem5::branch_prediction::LoopPredictor::loopPredict
bool loopPredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi, bool prev_pred_taken, unsigned instShiftAmt)
Get the loop prediction.
Definition: loop_predictor.cc:277
gem5::branch_prediction::LTAGE::update
void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, bool squashed, const StaticInstPtr &inst, Addr corrTarget) override
Updates the BP with taken/not taken information.
Definition: ltage.cc:97
gem5::PowerISA::bi
Bitfield< 20, 16 > bi
Definition: types.hh:80
gem5::branch_prediction::LTAGE::LTAGE
LTAGE(const LTAGEParams &params)
Definition: ltage.cc:53
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:381
gem5::Random::random
std::enable_if_t< std::is_integral< T >::value, T > random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Definition: random.hh:90
gem5::branch_prediction::LTAGE::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: ltage.cc:59
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::branch_prediction::LTAGE::LOOP
@ LOOP
Definition: ltage.hh:86
gem5::branch_prediction::TAGEBase::updateHistories
virtual void updateHistories(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *b, bool speculative, const StaticInstPtr &inst=nullStaticInstPtr, Addr target=MaxAddr)
(Speculatively) updates global histories (path and direction).
Definition: tage_base.cc:588
gem5::branch_prediction::LoopPredictor::condBranchUpdate
void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, bool tage_pred, BranchInfo *bi, unsigned instShiftAmt)
Update LTAGE for conditional branches.
Definition: loop_predictor.cc:331
gem5::branch_prediction::TAGEBase::condBranchUpdate
virtual void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, BranchInfo *bi, int nrand, Addr corrTarget, bool pred, bool preAdjustAlloc=false)
Update TAGE for conditional branches.
Definition: tage_base.cc:514
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::branch_prediction::LTAGE::predict
bool predict(ThreadID tid, Addr branch_pc, bool cond_branch, void *&b) override
Get a branch prediction from LTAGE.
Definition: ltage.cc:66
gem5::branch_prediction::TAGE
Definition: tage.hh:64
gem5::branch_prediction::LTAGE::LTageBranchInfo
Definition: ltage.hh:91
gem5::branch_prediction::BPredUnit::instShiftAmt
const unsigned instShiftAmt
Number of bits to shift instructions by for predictor addresses.
Definition: bpred_unit.hh:320
gem5::branch_prediction::LoopPredictor::getLoopUseCounter
int8_t getLoopUseCounter() const
Gets the value of the loop use counter.
Definition: loop_predictor.hh:252
gem5::branch_prediction::LoopPredictor::updateStats
void updateStats(bool taken, BranchInfo *bi)
Update the stats.
Definition: loop_predictor.cc:321
logging.hh
gem5::branch_prediction::LTAGE::loopPredictor
LoopPredictor * loopPredictor
The loop predictor object.
Definition: ltage.hh:81
gem5::branch_prediction::TAGE::tage
TAGEBase * tage
Definition: tage.hh:67
trace.hh
intmath.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::random_mt
Random random_mt
Definition: random.cc:99
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::branch_prediction::TAGEBase::tagePredict
bool tagePredict(ThreadID tid, Addr branch_pc, bool cond_branch, BranchInfo *bi)
TAGE prediction called from TAGE::predict.
Definition: tage_base.cc:360

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