base.hh File Reference

Declares a basic cache interface BaseCache. More...

#include <cassert>
#include <cstdint>
#include <string>
#include "base/addr_range.hh"
#include "base/compiler.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
#include "debug/CachePort.hh"
#include "enums/Clusivity.hh"
#include "mem/cache/cache_blk.hh"
#include "mem/cache/compressors/base.hh"
#include "mem/cache/mshr_queue.hh"
#include "mem/cache/tags/base.hh"
#include "mem/cache/write_queue.hh"
#include "mem/cache/write_queue_entry.hh"
#include "mem/packet.hh"
#include "mem/packet_queue.hh"
#include "mem/qport.hh"
#include "mem/request.hh"
#include "params/WriteAllocator.hh"
#include "sim/clocked_object.hh"
#include "sim/eventq.hh"
#include "sim/probe/probe.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"

Go to the source code of this file.

Classes
class	gem5::BaseCache
	A basic cache interface. More...
struct	gem5::BaseCache::DataUpdate
	A data contents update is composed of the updated block's address, the old contents, and the new contents. More...
class	gem5::BaseCache::CacheRequestPort
	A cache request port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks). More...
class	gem5::BaseCache::CacheReqPacketQueue
	Override the default behaviour of sendDeferredPacket to enable the memory-side cache port to also send requests based on the current MSHR status. More...
class	gem5::BaseCache::MemSidePort
	The memory-side port extends the base cache request port with access functions for functional, atomic and timing snoops. More...
class	gem5::BaseCache::CacheResponsePort
	A cache response port is used for the CPU-side port of the cache, and it is basically a simple timing port that uses a transmit list for responses to the CPU (or connected requestor). More...
class	gem5::BaseCache::CpuSidePort
	The CPU-side port extends the base cache response port with access functions for functional, atomic and timing requests. More...
struct	gem5::BaseCache::CacheCmdStats
struct	gem5::BaseCache::CacheStats
class	gem5::WriteAllocator
	The write allocator inspects write packets and detects streaming patterns. More...

Namespaces
	gem5
	Reference material can be found at the JEDEC website: UFS standard http://www.jedec.org/standards-documents/results/jesd220 UFS HCI specification http://www.jedec.org/standards-documents/results/jesd223.
	gem5::prefetch

Functions
	gem5::GEM5_DEPRECATED_NAMESPACE (Prefetcher, prefetch)

Detailed Description

Declares a basic cache interface BaseCache.

Definition in file base.hh.