gem5 v24.0.0.0
Loading...
Searching...
No Matches
write_queue_entry.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
46#ifndef __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
47#define __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
48
49#include <cassert>
50#include <iosfwd>
51#include <list>
52#include <string>
53
54#include "base/printable.hh"
55#include "base/types.hh"
57#include "mem/packet.hh"
58
59namespace gem5
60{
61
62class BaseCache;
63
67class WriteQueueEntry : public QueueEntry, public Printable
68{
69
73 template<typename Entry>
74 friend class Queue;
75 friend class WriteQueue;
76
77 public:
78 class TargetList : public std::list<Target>
79 {
80
81 public:
82
86 void print(std::ostream &os, int verbosity,
87 const std::string &prefix) const;
88 };
89
93 typedef List::iterator Iterator;
94
95 bool sendPacket(BaseCache &cache) override;
96
97 private:
98
104
110
113
114 public:
115
117 WriteQueueEntry(const std::string &name)
119 {}
120
129 void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
130 Tick when_ready, Counter _order);
131
132
136 void deallocate();
137
142 int getNumTargets() const
143 { return targets.size(); }
144
149 bool hasTargets() const { return !targets.empty(); }
150
155 Target *getTarget() override
156 {
157 assert(hasTargets());
158 return &targets.front();
159 }
160
165 {
166 targets.pop_front();
167 }
168
170
174 void print(std::ostream &os,
175 int verbosity = 0,
176 const std::string &prefix = "") const override;
183 std::string print() const;
184
185 bool matchBlockAddr(const Addr addr, const bool is_secure) const override;
186 bool matchBlockAddr(const PacketPtr pkt) const override;
187 bool conflictAddr(const QueueEntry* entry) const override;
188};
189
190} // namespace gem5
191
192#endif // __MEM_CACHE_WRITE_QUEUE_ENTRY_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
A basic cache interface.
Definition base.hh:100
virtual std::string name() const
Definition named.hh:47
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Abstract base class for objects which support being printed to a stream for debugging.
Definition printable.hh:48
A queue entry is holding packets that will be serviced as soon as resources are available.
A queue entry base class, to be used by both the MSHRs and write-queue entries.
Counter order
Order number assigned to disambiguate writes and misses.
Tick readyTime
Tick when ready to issue.
A high-level queue interface, to be used by both the MSHR queue and the write buffer.
Definition queue.hh:71
void add(PacketPtr pkt, Tick readyTime, Counter order)
int getNumTargets() const
Returns the current number of allocated targets.
Target * getTarget() override
Returns a reference to the first target.
void popTarget()
Pop first target.
Iterator allocIter
Pointer to this entry on the allocated list.
bool matchBlockAddr(const Addr addr, const bool is_secure) const override
Check if entry corresponds to the one being looked for.
bool trySatisfyFunctional(PacketPtr pkt)
std::string print() const
A no-args wrapper of print(std::ostream...) meant to be invoked from DPRINTFs avoiding string overhea...
bool sendPacket(BaseCache &cache) override
Send this queue entry as a downstream packet, with the exact behaviour depending on the specific entr...
bool hasTargets() const
Returns true if there are targets left.
void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter _order)
Allocate a miss to this entry.
TargetList targets
List of all requests that match the address.
void deallocate()
Mark this entry as free.
Iterator readyIter
Pointer to this entry on the ready list.
std::list< WriteQueueEntry * > List
A list of write queue entriess.
WriteQueueEntry(const std::string &name)
A simple constructor.
bool conflictAddr(const QueueEntry *entry) const override
Check if given entry's packets conflict with this' entries packets.
List::iterator Iterator
WriteQueueEntry list iterator.
A write queue for all eviction packets, i.e.
STL list class.
Definition stl.hh:51
Bitfield< 17 > os
Definition misc.hh:838
Bitfield< 3 > addr
Definition types.hh:84
double Counter
All counters are of 64-bit values.
Definition types.hh:46
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
uint64_t Tick
Tick count type.
Definition types.hh:58
Declaration of the Packet class.
Generic queue entry.

Generated on Tue Jun 18 2024 16:24:05 for gem5 by doxygen 1.11.0