gem5  v21.1.0.2
base.hh
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40 
46 #ifndef __MEM_CACHE_BASE_HH__
47 #define __MEM_CACHE_BASE_HH__
48 
49 #include <cassert>
50 #include <cstdint>
51 #include <string>
52 
53 #include "base/addr_range.hh"
54 #include "base/compiler.hh"
55 #include "base/statistics.hh"
56 #include "base/trace.hh"
57 #include "base/types.hh"
58 #include "debug/Cache.hh"
59 #include "debug/CachePort.hh"
60 #include "enums/Clusivity.hh"
61 #include "mem/cache/cache_blk.hh"
63 #include "mem/cache/mshr_queue.hh"
64 #include "mem/cache/tags/base.hh"
65 #include "mem/cache/write_queue.hh"
67 #include "mem/packet.hh"
68 #include "mem/packet_queue.hh"
69 #include "mem/qport.hh"
70 #include "mem/request.hh"
71 #include "params/WriteAllocator.hh"
72 #include "sim/clocked_object.hh"
73 #include "sim/eventq.hh"
74 #include "sim/probe/probe.hh"
75 #include "sim/serialize.hh"
76 #include "sim/sim_exit.hh"
77 #include "sim/system.hh"
78 
79 namespace gem5
80 {
81 
83 namespace prefetch
84 {
85  class Base;
86 }
87 class MSHR;
88 class RequestPort;
89 class QueueEntry;
90 struct BaseCacheParams;
91 
95 class BaseCache : public ClockedObject
96 {
97  protected:
102  {
105  };
106 
107  public:
112  {
117  };
118 
124  struct DataUpdate
125  {
129  bool isSecure;
134 
135  DataUpdate(Addr _addr, bool is_secure)
136  : addr(_addr), isSecure(is_secure), oldData(), newData()
137  {
138  }
139  };
140 
141  protected:
142 
153  {
154 
155  public:
156 
161  void schedSendEvent(Tick time)
162  {
163  DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
164  reqQueue.schedSendEvent(time);
165  }
166 
167  protected:
168 
169  CacheRequestPort(const std::string &_name, BaseCache *_cache,
170  ReqPacketQueue &_reqQueue,
171  SnoopRespPacketQueue &_snoopRespQueue) :
172  QueuedRequestPort(_name, _cache, _reqQueue, _snoopRespQueue)
173  { }
174 
180  virtual bool isSnooping() const { return true; }
181  };
182 
190  {
191 
192  protected:
193 
196 
197  public:
198 
200  SnoopRespPacketQueue &snoop_resp_queue,
201  const std::string &label) :
203  snoopRespQueue(snoop_resp_queue) { }
204 
210  virtual void sendDeferredPacket();
211 
221  {
223  DPRINTF(CachePort, "Waiting for snoop response to be "
224  "sent\n");
226  schedSendEvent(when);
227  return true;
228  }
229  return false;
230  }
231  };
232 
233 
239  {
240  private:
241 
244 
246 
247  // a pointer to our specific cache implementation
249 
250  protected:
251 
252  virtual void recvTimingSnoopReq(PacketPtr pkt);
253 
254  virtual bool recvTimingResp(PacketPtr pkt);
255 
256  virtual Tick recvAtomicSnoop(PacketPtr pkt);
257 
258  virtual void recvFunctionalSnoop(PacketPtr pkt);
259 
260  public:
261 
262  MemSidePort(const std::string &_name, BaseCache *_cache,
263  const std::string &_label);
264  };
265 
275  {
276 
277  public:
278 
280  void setBlocked();
281 
283  void clearBlocked();
284 
285  bool isBlocked() const { return blocked; }
286 
287  protected:
288 
289  CacheResponsePort(const std::string &_name, BaseCache *_cache,
290  const std::string &_label);
291 
294 
295  bool blocked;
296 
298 
299  private:
300 
301  void processSendRetry();
302 
304 
305  };
306 
312  {
313  private:
314 
315  // a pointer to our specific cache implementation
317 
318  protected:
319  virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
320 
321  virtual bool tryTiming(PacketPtr pkt) override;
322 
323  virtual bool recvTimingReq(PacketPtr pkt) override;
324 
325  virtual Tick recvAtomic(PacketPtr pkt) override;
326 
327  virtual void recvFunctional(PacketPtr pkt) override;
328 
329  virtual AddrRangeList getAddrRanges() const override;
330 
331  public:
332 
333  CpuSidePort(const std::string &_name, BaseCache *_cache,
334  const std::string &_label);
335 
336  };
337 
340 
341  protected:
342 
345 
348 
351 
354 
357 
360 
363 
366 
373 
389 
397 
402  std::unique_ptr<Packet> pendingDelete;
403 
408  void markInService(MSHR *mshr, bool pending_modified_resp)
409  {
410  bool wasFull = mshrQueue.isFull();
411  mshrQueue.markInService(mshr, pending_modified_resp);
412 
413  if (wasFull && !mshrQueue.isFull()) {
415  }
416  }
417 
419  {
420  bool wasFull = writeBuffer.isFull();
421  writeBuffer.markInService(entry);
422 
423  if (wasFull && !writeBuffer.isFull()) {
425  }
426  }
427 
441  inline bool allocOnFill(MemCmd cmd) const
442  {
443  return clusivity == enums::mostly_incl ||
444  cmd == MemCmd::WriteLineReq ||
445  cmd == MemCmd::ReadReq ||
446  cmd == MemCmd::WriteReq ||
447  cmd.isPrefetch() ||
448  cmd.isLLSC();
449  }
450 
460 
469  Cycles calculateTagOnlyLatency(const uint32_t delay,
470  const Cycles lookup_lat) const;
480  Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
481  const Cycles lookup_lat) const;
482 
491  virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
492  PacketList &writebacks);
493 
494  /*
495  * Handle a timing request that hit in the cache
496  *
497  * @param ptk The request packet
498  * @param blk The referenced block
499  * @param request_time The tick at which the block lookup is compete
500  */
501  virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
502  Tick request_time);
503 
504  /*
505  * Handle a timing request that missed in the cache
506  *
507  * Implementation specific handling for different cache
508  * implementations
509  *
510  * @param ptk The request packet
511  * @param blk The referenced block
512  * @param forward_time The tick at which we can process dependent requests
513  * @param request_time The tick at which the block lookup is compete
514  */
515  virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
516  Tick forward_time,
517  Tick request_time) = 0;
518 
519  /*
520  * Handle a timing request that missed in the cache
521  *
522  * Common functionality across different cache implementations
523  *
524  * @param ptk The request packet
525  * @param blk The referenced block
526  * @param mshr Any existing mshr for the referenced cache block
527  * @param forward_time The tick at which we can process dependent requests
528  * @param request_time The tick at which the block lookup is compete
529  */
530  void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
531  Tick forward_time, Tick request_time);
532 
537  virtual void recvTimingReq(PacketPtr pkt);
538 
544 
555  virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
556  CacheBlk *blk) = 0;
557 
562  virtual void recvTimingResp(PacketPtr pkt);
563 
568  virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
569 
574  virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
575 
588  virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
589  PacketList &writebacks) = 0;
590 
596  virtual Tick recvAtomic(PacketPtr pkt);
597 
604  virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
605 
612  virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
613 
623  void updateBlockData(CacheBlk *blk, const PacketPtr cpkt,
624  bool has_old_data);
625 
629  void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
630 
638 
642  virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
643 
647  virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
648 
664  virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
665  bool needs_writable,
666  bool is_whole_line_write) const = 0;
667 
675  const bool writebackClean;
676 
685 
692  assert(tempBlockWriteback != nullptr);
693  PacketList writebacks{tempBlockWriteback};
694  doWritebacksAtomic(writebacks);
695  tempBlockWriteback = nullptr;
696  }
697 
704 
729  bool updateCompressionData(CacheBlk *&blk, const uint64_t* data,
730  PacketList &writebacks);
731 
742  virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
743  bool deferred_response = false,
744  bool pending_downgrade = false);
745 
755  void maintainClusivity(bool from_cache, CacheBlk *blk);
756 
766  bool handleEvictions(std::vector<CacheBlk*> &evict_blks,
767  PacketList &writebacks);
768 
788  PacketList &writebacks, bool allocate);
789 
802  CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks);
811  GEM5_NO_DISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
812 
821  void evictBlock(CacheBlk *blk, PacketList &writebacks);
822 
828  void invalidateBlock(CacheBlk *blk);
829 
837 
850 
854  virtual void memWriteback() override;
855 
863  virtual void memInvalidate() override;
864 
870  bool isDirty() const;
871 
880  bool inRange(Addr addr) const;
881 
885  Tick nextQueueReadyTime() const;
886 
888  const unsigned blkSize;
889 
895 
901 
908 
911 
918 
922  const bool sequentialAccess;
923 
925  const int numTarget;
926 
929 
935  const enums::Clusivity clusivity;
936 
943  const bool isReadOnly;
944 
951  const bool replaceExpansions;
952 
959  const bool moveContractions;
960 
965  uint8_t blocked;
966 
968  uint64_t order;
969 
972 
975 
978 
983 
984  public:
987 
989  {
990  CacheCmdStats(BaseCache &c, const std::string &name);
991 
998  void regStatsFromParent();
999 
1001 
1035  };
1036 
1038  {
1040 
1041  void regStats() override;
1042 
1044  return *cmd[p->cmdToIndex()];
1045  }
1046 
1048 
1053 
1058 
1063 
1068 
1073 
1078 
1083 
1086 
1089 
1094 
1099 
1102 
1107 
1110 
1115 
1120 
1123 
1126 
1129 
1135 
1138  } stats;
1139 
1141  void regProbePoints() override;
1142 
1143  public:
1144  BaseCache(const BaseCacheParams &p, unsigned blk_size);
1145  ~BaseCache();
1146 
1147  void init() override;
1148 
1149  Port &getPort(const std::string &if_name,
1150  PortID idx=InvalidPortID) override;
1151 
1156  unsigned
1158  {
1159  return blkSize;
1160  }
1161 
1162  const AddrRangeList &getAddrRanges() const { return addrRanges; }
1163 
1164  MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
1165  {
1167  pkt, time, order++,
1168  allocOnFill(pkt->cmd));
1169 
1170  if (mshrQueue.isFull()) {
1172  }
1173 
1174  if (sched_send) {
1175  // schedule the send
1176  schedMemSideSendEvent(time);
1177  }
1178 
1179  return mshr;
1180  }
1181 
1183  {
1184  // should only see writes or clean evicts here
1185  assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
1186 
1187  Addr blk_addr = pkt->getBlockAddr(blkSize);
1188 
1189  // If using compression, on evictions the block is decompressed and
1190  // the operation's latency is added to the payload delay. Consume
1191  // that payload delay here, meaning that the data is always stored
1192  // uncompressed in the writebuffer
1193  if (compressor) {
1194  time += pkt->payloadDelay;
1195  pkt->payloadDelay = 0;
1196  }
1197 
1198  WriteQueueEntry *wq_entry =
1199  writeBuffer.findMatch(blk_addr, pkt->isSecure());
1200  if (wq_entry && !wq_entry->inService) {
1201  DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
1202  }
1203 
1204  writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
1205 
1206  if (writeBuffer.isFull()) {
1208  }
1209 
1210  // schedule the send
1211  schedMemSideSendEvent(time);
1212  }
1213 
1217  bool isBlocked() const
1218  {
1219  return blocked != 0;
1220  }
1221 
1228  {
1229  uint8_t flag = 1 << cause;
1230  if (blocked == 0) {
1231  stats.blockedCauses[cause]++;
1232  blockedCycle = curCycle();
1234  }
1235  blocked |= flag;
1236  DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
1237  }
1238 
1247  {
1248  uint8_t flag = 1 << cause;
1249  blocked &= ~flag;
1250  DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
1251  if (blocked == 0) {
1252  stats.blockedCycles[cause] += curCycle() - blockedCycle;
1254  }
1255  }
1256 
1266  {
1268  }
1269 
1270  bool inCache(Addr addr, bool is_secure) const {
1271  return tags->findBlock(addr, is_secure);
1272  }
1273 
1274  bool hasBeenPrefetched(Addr addr, bool is_secure) const {
1275  CacheBlk *block = tags->findBlock(addr, is_secure);
1276  if (block) {
1277  return block->wasPrefetched();
1278  } else {
1279  return false;
1280  }
1281  }
1282 
1283  bool inMissQueue(Addr addr, bool is_secure) const {
1284  return mshrQueue.findMatch(addr, is_secure);
1285  }
1286 
1288  {
1289  assert(pkt->req->requestorId() < system->maxRequestors());
1290  stats.cmdStats(pkt).misses[pkt->req->requestorId()]++;
1291  pkt->req->incAccessDepth();
1292  if (missCount) {
1293  --missCount;
1294  if (missCount == 0)
1295  exitSimLoop("A cache reached the maximum miss count");
1296  }
1297  }
1299  {
1300  assert(pkt->req->requestorId() < system->maxRequestors());
1301  stats.cmdStats(pkt).hits[pkt->req->requestorId()]++;
1302  }
1303 
1309  bool coalesce() const;
1310 
1311 
1316  void writebackVisitor(CacheBlk &blk);
1317 
1323  void invalidateVisitor(CacheBlk &blk);
1324 
1333  virtual bool sendMSHRQueuePacket(MSHR* mshr);
1334 
1343  bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
1344 
1350  void serialize(CheckpointOut &cp) const override;
1351  void unserialize(CheckpointIn &cp) override;
1352 };
1353 
1370 {
1371  public:
1372  WriteAllocator(const WriteAllocatorParams &p) :
1373  SimObject(p),
1374  coalesceLimit(p.coalesce_limit * p.block_size),
1375  noAllocateLimit(p.no_allocate_limit * p.block_size),
1376  delayThreshold(p.delay_threshold)
1377  {
1378  reset();
1379  }
1380 
1387  bool coalesce() const {
1388  return mode != WriteMode::ALLOCATE;
1389  }
1390 
1396  bool allocate() const {
1397  return mode != WriteMode::NO_ALLOCATE;
1398  }
1399 
1406  void reset() {
1408  byteCount = 0;
1409  nextAddr = 0;
1410  }
1411 
1418  bool delay(Addr blk_addr) {
1419  if (delayCtr[blk_addr] > 0) {
1420  --delayCtr[blk_addr];
1421  return true;
1422  } else {
1423  return false;
1424  }
1425  }
1426 
1432  void resetDelay(Addr blk_addr) {
1433  delayCtr.erase(blk_addr);
1434  }
1435 
1446  void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr);
1447 
1448  private:
1454  enum class WriteMode : char
1455  {
1456  ALLOCATE,
1457  COALESCE,
1458  NO_ALLOCATE,
1459  };
1461 
1464 
1469  uint32_t byteCount;
1470 
1474  const uint32_t coalesceLimit;
1475  const uint32_t noAllocateLimit;
1479  const uint32_t delayThreshold;
1480 
1485  std::unordered_map<Addr, Counter> delayCtr;
1486 };
1487 
1488 } // namespace gem5
1489 
1490 #endif //__MEM_CACHE_BASE_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::Packet::getBlockAddr
Addr getBlockAddr(unsigned int blk_size) const
Definition: packet.hh:805
gem5::BaseCache::memWriteback
virtual void memWriteback() override
Write back dirty blocks in the cache using functional accesses.
Definition: base.cc:1712
gem5::BaseCache::evictBlock
virtual GEM5_NO_DISCARD PacketPtr evictBlock(CacheBlk *blk)=0
Evict a cache block.
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:252
gem5::MSHR
Miss Status and handling Register.
Definition: mshr.hh:74
gem5::PacketQueue::deferredPacketReadyTime
Tick deferredPacketReadyTime() const
Get the next packet ready time.
Definition: packet_queue.hh:172
gem5::BaseCache::CacheResponsePort::queue
RespPacketQueue queue
A normal packet queue used to store responses.
Definition: base.hh:293
gem5::BaseCache::MemSidePort::MemSidePort
MemSidePort(const std::string &_name, BaseCache *_cache, const std::string &_label)
Definition: base.cc:2585
gem5::BaseCache::CacheCmdStats::accesses
statistics::Formula accesses
The number of accesses per command and thread.
Definition: base.hh:1014
gem5::BaseCache::incMissCount
void incMissCount(PacketPtr pkt)
Definition: base.hh:1287
gem5::BaseCache::cpuSidePort
CpuSidePort cpuSidePort
Definition: base.hh:338
gem5::BaseCache::CacheStats::overallMshrUncacheable
statistics::Formula overallMshrUncacheable
Total number of misses that miss in the MSHRs.
Definition: base.hh:1101
gem5::BaseCache::CacheCmdStats::hits
statistics::Vector hits
Number of hits per thread for each type of command.
Definition: base.hh:1004
gem5::WriteAllocator::delayCtr
std::unordered_map< Addr, Counter > delayCtr
Keep track of the number of times the allocator has delayed an WriteReq MSHR.
Definition: base.hh:1485
gem5::BaseCache::handleTimingReqMiss
virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time)=0
gem5::BaseCache::CacheCmdStats::regStatsFromParent
void regStatsFromParent()
Callback to register stats from parent CacheStats::regStats().
Definition: base.cc:1987
gem5::WriteAllocator::reset
void reset()
Reset the write allocator state, meaning that it allocates for writes and has not recorded any inform...
Definition: base.hh:1406
gem5::BaseCache::~BaseCache
~BaseCache()
Definition: base.cc:139
gem5::BaseCache::MemSidePort::_reqQueue
CacheReqPacketQueue _reqQueue
The cache-specific queue.
Definition: base.hh:243
gem5::BaseCache::invalidateBlock
void invalidateBlock(CacheBlk *blk)
Invalidate a cache block.
Definition: base.cc:1587
system.hh
gem5::BaseCache::DataUpdate::oldData
std::vector< uint64_t > oldData
The stale data contents.
Definition: base.hh:131
gem5::BaseCache::DataUpdate::DataUpdate
DataUpdate(Addr _addr, bool is_secure)
Definition: base.hh:135
gem5::MemCmd::CleanEvict
@ CleanEvict
Definition: packet.hh:95
gem5::BaseCache::CacheStats::replacements
statistics::Scalar replacements
Number of replacements of valid blocks.
Definition: base.hh:1125
gem5::BaseCache::MSHRQueue_MSHRs
@ MSHRQueue_MSHRs
Definition: base.hh:103
gem5::BaseCache::cmpAndSwap
void cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
Handle doing the Compare and Swap function for SPARC.
Definition: base.cc:721
gem5::RespPacketQueue
Definition: packet_queue.hh:300
gem5::BaseCache::NUM_BLOCKED_CAUSES
@ NUM_BLOCKED_CAUSES
Definition: base.hh:116
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::BaseCache::MemSidePort
The memory-side port extends the base cache request port with access functions for functional,...
Definition: base.hh:238
gem5::Clocked::curCycle
Cycles curCycle() const
Determine the current cycle, corresponding to a tick aligned to a clock edge.
Definition: clocked_object.hh:195
gem5::BaseCache::ppDataUpdate
ProbePointArg< DataUpdate > * ppDataUpdate
To probe when the contents of a block are updated.
Definition: base.hh:372
serialize.hh
gem5::WriteAllocator::WriteMode::ALLOCATE
@ ALLOCATE
gem5::BaseCache::CacheRequestPort
A cache request port is used for the memory-side port of the cache, and in addition to the basic timi...
Definition: base.hh:152
gem5::BaseCache::access
virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks)
Does all the processing necessary to perform the provided request.
Definition: base.cc:1153
gem5::BaseCache::forwardSnoops
bool forwardSnoops
Do we forward snoops from mem side port through to cpu side port?
Definition: base.hh:928
gem5::BaseCache::CacheCmdStats::mshrHits
statistics::Vector mshrHits
Number of misses that hit in the MSHRs per command and thread.
Definition: base.hh:1020
gem5::BaseCache::CacheResponsePort::processSendRetry
void processSendRetry()
Definition: base.cc:172
gem5::BaseCache::writeBuffer
WriteQueue writeBuffer
Write/writeback buffer.
Definition: base.hh:347
gem5::BaseCache::CacheCmdStats::avgMshrMissLatency
statistics::Formula avgMshrMissLatency
The average latency of an MSHR miss, per command and thread.
Definition: base.hh:1032
gem5::BaseCache::missCount
Counter missCount
The number of misses to trigger an exit event.
Definition: base.hh:977
gem5::BaseCache::moveContractions
const bool moveContractions
Similar to data expansions, after a block improves its compression, it may need to be moved elsewhere...
Definition: base.hh:959
gem5::BaseCache::CacheStats::overallMshrHits
statistics::Formula overallMshrHits
Total number of misses that hit in the MSHRs.
Definition: base.hh:1093
gem5::QueuedRequestPort
The QueuedRequestPort combines two queues, a request queue and a snoop response queue,...
Definition: qport.hh:109
gem5::BaseCache::recvTimingResp
virtual void recvTimingResp(PacketPtr pkt)
Handles a response (cache line fill/write ack) from the bus.
Definition: base.cc:420
gem5::BaseCache::CacheResponsePort::CacheResponsePort
CacheResponsePort(const std::string &_name, BaseCache *_cache, const std::string &_label)
Definition: base.cc:69
gem5::Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:366
gem5::WriteQueue::markInService
void markInService(WriteQueueEntry *entry)
Mark the given entry as in service.
Definition: write_queue.cc:78
gem5::BaseCache::MemSidePort::recvFunctionalSnoop
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
Definition: base.cc:2538
gem5::BaseCache::coalesce
bool coalesce() const
Checks if the cache is coalescing writes.
Definition: base.cc:1731
base.hh
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::BaseCache::CacheReqPacketQueue::snoopRespQueue
SnoopRespPacketQueue & snoopRespQueue
Definition: base.hh:195
gem5::BaseCache::CacheCmdStats::mshrUncacheable
statistics::Vector mshrUncacheable
Number of misses that miss in the MSHRs, per command and thread.
Definition: base.hh:1024
gem5::BaseCache::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: base.cc:201
gem5::BaseCache::CacheStats::overallAccesses
statistics::Formula overallAccesses
The number of overall accesses.
Definition: base.hh:1067
gem5::BaseCache::MemSidePort::cache
BaseCache * cache
Definition: base.hh:248
gem5::BaseCache::markInService
void markInService(MSHR *mshr, bool pending_modified_resp)
Mark a request as in service (sent downstream in the memory system), effectively making this MSHR the...
Definition: base.hh:408
gem5::WriteAllocator::WriteMode::COALESCE
@ COALESCE
gem5::TempCacheBlk
Special instance of CacheBlk for use with tempBlk that deals with its block address regeneration.
Definition: cache_blk.hh:500
gem5::Packet::isWrite
bool isWrite() const
Definition: packet.hh:583
gem5::Packet::isSecure
bool isSecure() const
Definition: packet.hh:810
gem5::BaseCache::clearBlocked
void clearBlocked(BlockedCause cause)
Marks the cache as unblocked for the given cause.
Definition: base.hh:1246
gem5::BaseCache::CacheCmdStats::missRate
statistics::Formula missRate
The miss rate per command and thread.
Definition: base.hh:1016
gem5::BaseCache::dataLatency
const Cycles dataLatency
The latency of data access of a cache.
Definition: base.hh:900
gem5::BaseCache::updateCompressionData
bool updateCompressionData(CacheBlk *&blk, const uint64_t *data, PacketList &writebacks)
When a block is overwriten, its compression information must be updated, and it may need to be recomp...
Definition: base.cc:902
gem5::BaseCache::CacheCmdStats::mshrMisses
statistics::Vector mshrMisses
Number of misses that miss in the MSHRs, per command and thread.
Definition: base.hh:1022
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::BaseCache::replaceExpansions
const bool replaceExpansions
when a data expansion of a compressed block happens it will not be able to co-allocate where it is at...
Definition: base.hh:951
gem5::BaseCache::blocked
uint8_t blocked
Bit vector of the blocking reasons for the access path.
Definition: base.hh:965
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector< uint64_t >
gem5::BaseCache::CacheStats::demandAccesses
statistics::Formula demandAccesses
The number of demand accesses.
Definition: base.hh:1065
gem5::BaseCache::CacheStats::overallAvgMshrMissLatency
statistics::Formula overallAvgMshrMissLatency
The average overall latency of an MSHR miss.
Definition: base.hh:1119
gem5::WriteAllocator::updateMode
void updateMode(Addr write_addr, unsigned write_size, Addr blk_addr)
Update the write mode based on the current write packet.
Definition: base.cc:2595
gem5::BaseCache::sequentialAccess
const bool sequentialAccess
Whether tags and data are accessed sequentially.
Definition: base.hh:922
gem5::BaseCache::BaseCache
BaseCache(const BaseCacheParams &p, unsigned blk_size)
Definition: base.cc:79
gem5::BaseCache::updateBlockData
void updateBlockData(CacheBlk *blk, const PacketPtr cpkt, bool has_old_data)
Update the data contents of a block.
Definition: base.cc:695
gem5::MSHRQueue::markInService
void markInService(MSHR *mshr, bool pending_modified_resp)
Mark the given MSHR as in service.
Definition: mshr_queue.cc:115
gem5::BaseCache::pendingDelete
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Definition: base.hh:402
gem5::BaseCache::CacheResponsePort
A cache response port is used for the CPU-side port of the cache, and it is basically a simple timing...
Definition: base.hh:274
gem5::BaseCache::recvAtomicSnoop
virtual Tick recvAtomicSnoop(PacketPtr pkt)=0
Snoop for the provided request in the cache and return the estimated time taken.
gem5::InvalidPortID
const PortID InvalidPortID
Definition: types.hh:253
sim_exit.hh
gem5::BaseCache::blockedCycle
Cycles blockedCycle
Stores time the cache blocked for statistics.
Definition: base.hh:971
request.hh
gem5::BaseCache::CacheStats::overallAvgMissLatency
statistics::Formula overallAvgMissLatency
The average miss latency for all misses.
Definition: base.hh:1077
gem5::BaseCache::CacheStats::overallMshrMissRate
statistics::Formula overallMshrMissRate
The overall miss rate in the MSHRs.
Definition: base.hh:1114
gem5::exitSimLoop
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:88
gem5::WriteAllocator::WriteMode
WriteMode
The current mode for write coalescing and allocation, either normal operation (ALLOCATE),...
Definition: base.hh:1454
gem5::BaseCache::MSHRQueueIndex
MSHRQueueIndex
Indexes to enumerate the MSHR queues.
Definition: base.hh:101
gem5::BaseCache::CacheStats::cache
const BaseCache & cache
Definition: base.hh:1047
gem5::CacheBlk
A Basic Cache block.
Definition: cache_blk.hh:70
gem5::BaseCache::tempBlock
TempCacheBlk * tempBlock
Temporary cache block for occasional transitory use.
Definition: base.hh:396
gem5::BaseCache::CacheStats::blockedCycles
statistics::Vector blockedCycles
The total number of cycles blocked for each blocked cause.
Definition: base.hh:1080
gem5::BaseCache::MSHRQueue_WriteBuffer
@ MSHRQueue_WriteBuffer
Definition: base.hh:104
gem5::BaseCache::handleAtomicReqMiss
virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks)=0
Handle a request in atomic mode that missed in this cache.
packet.hh
gem5::BaseCache::sendWriteQueuePacket
bool sendWriteQueuePacket(WriteQueueEntry *wq_entry)
Similar to sendMSHR, but for a write-queue entry instead.
Definition: base.cc:1893
gem5::BaseCache::CacheCmdStats::mshrMissLatency
statistics::Vector mshrMissLatency
Total cycle latency of each MSHR miss, per command and thread.
Definition: base.hh:1026
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::BaseCache::CpuSidePort::recvTimingReq
virtual bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
Definition: base.cc:2449
gem5::BaseCache::CacheResponsePort::setBlocked
void setBlocked()
Do not accept any new requests.
Definition: base.cc:145
gem5::BaseCache::isBlocked
bool isBlocked() const
Returns true if the cache is blocked for accesses.
Definition: base.hh:1217
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::BaseCache::writeAllocator
WriteAllocator *const writeAllocator
The writeAllocator drive optimizations for streaming writes.
Definition: base.hh:388
gem5::WriteAllocator::WriteAllocator
WriteAllocator(const WriteAllocatorParams &p)
Definition: base.hh:1372
gem5::BaseCache::inRange
bool inRange(Addr addr) const
Determine if an address is in the ranges covered by this cache.
Definition: base.cc:213
gem5::MemCmd
Definition: packet.hh:75
gem5::BaseCache::DataUpdate::newData
std::vector< uint64_t > newData
The new data contents.
Definition: base.hh:133
gem5::WriteQueue::allocate
WriteQueueEntry * allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter order)
Allocates a new WriteQueueEntry for the request and size.
Definition: write_queue.cc:61
gem5::BaseCache::CacheCmdStats::misses
statistics::Vector misses
Number of misses per thread for each type of command.
Definition: base.hh:1007
gem5::WriteAllocator::coalesceLimit
const uint32_t coalesceLimit
Limits for when to switch between the different write modes.
Definition: base.hh:1474
gem5::BaseCache::writebackTempBlockAtomicEvent
EventFunctionWrapper writebackTempBlockAtomicEvent
An event to writeback the tempBlock after recvAtomic finishes.
Definition: base.hh:703
gem5::BaseCache::CacheStats::demandMshrHits
statistics::Formula demandMshrHits
Demand misses that hit in the MSHRs.
Definition: base.hh:1091
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::BaseCache::Blocked_NoTargets
@ Blocked_NoTargets
Definition: base.hh:115
gem5::BaseCache::DataUpdate
A data contents update is composed of the updated block's address, the old contents,...
Definition: base.hh:124
gem5::BaseCache::CacheStats::overallMshrMisses
statistics::Formula overallMshrMisses
Total number of misses that miss in the MSHRs.
Definition: base.hh:1098
gem5::BaseCache::order
uint64_t order
Increasing order number assigned to each incoming request.
Definition: base.hh:968
gem5::BaseCache::CacheCmdStats::avgMshrUncacheableLatency
statistics::Formula avgMshrUncacheableLatency
The average latency of an MSHR miss, per command and thread.
Definition: base.hh:1034
gem5::BaseCache::CacheStats::overallMissLatency
statistics::Formula overallMissLatency
Total number of cycles spent waiting for all misses.
Definition: base.hh:1062
gem5::Flags< FlagsType >
gem5::BaseCache::CacheResponsePort::isBlocked
bool isBlocked() const
Definition: base.hh:285
gem5::BaseCache::serialize
void serialize(CheckpointOut &cp) const override
Serialize the state of the caches.
Definition: base.cc:1917
gem5::BaseCache::ppMiss
ProbePointArg< PacketPtr > * ppMiss
To probe when a cache miss occurs.
Definition: base.hh:362
gem5::System::maxRequestors
RequestorID maxRequestors()
Get the number of requestors registered in the system.
Definition: system.hh:518
gem5::BaseCache::prefetcher
prefetch::Base * prefetcher
Prefetcher.
Definition: base.hh:356
gem5::System
Definition: system.hh:77
gem5::BaseCache::tags
BaseTags * tags
Tag and data Storage.
Definition: base.hh:350
gem5::WriteAllocator::allocate
bool allocate() const
Should writes allocate?
Definition: base.hh:1396
gem5::Queue::isFull
bool isFull() const
Definition: queue.hh:150
gem5::BaseCache::CacheStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: base.cc:2191
gem5::BaseCache::ppFill
ProbePointArg< PacketPtr > * ppFill
To probe when a cache fill occurs.
Definition: base.hh:365
gem5::PacketQueue::checkConflict
bool checkConflict(const PacketPtr pkt, const int blk_size) const
Check if a packet corresponding to the same address exists in the queue.
Definition: packet_queue.cc:75
gem5::BaseCache::CacheStats::cmd
std::vector< std::unique_ptr< CacheCmdStats > > cmd
Per-command statistics.
Definition: base.hh:1137
gem5::BaseCache::allocateWriteBuffer
void allocateWriteBuffer(PacketPtr pkt, Tick time)
Definition: base.hh:1182
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::BaseCache::MemSidePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the peer.
Definition: base.cc:2511
gem5::BaseCache::CacheReqPacketQueue::cache
BaseCache & cache
Definition: base.hh:194
gem5::Packet::print
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
Definition: packet.cc:373
gem5::BaseCache::stats
gem5::BaseCache::CacheStats stats
gem5::WriteAllocator::mode
WriteMode mode
Definition: base.hh:1460
gem5::BaseCache
A basic cache interface.
Definition: base.hh:95
gem5::QueuedResponsePort
A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module...
Definition: qport.hh:61
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::WriteAllocator::nextAddr
Addr nextAddr
Address to match writes against to detect streams.
Definition: base.hh:1463
gem5::PacketId
uint64_t PacketId
Definition: packet.hh:73
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::BaseCache::calculateTagOnlyLatency
Cycles calculateTagOnlyLatency(const uint32_t delay, const Cycles lookup_lat) const
Calculate latency of accesses that only touch the tag array.
Definition: base.cc:1110
gem5::BaseCache::hasBeenPrefetched
bool hasBeenPrefetched(Addr addr, bool is_secure) const
Definition: base.hh:1274
gem5::BaseCache::sendMSHRQueuePacket
virtual bool sendMSHRQueuePacket(MSHR *mshr)
Take an MSHR, turn it into a suitable downstream packet, and send it out.
Definition: base.cc:1790
gem5::WriteAllocator::byteCount
uint32_t byteCount
Bytes written contiguously.
Definition: base.hh:1469
gem5::BaseCache::writecleanBlk
PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
Create a writeclean request for the given block.
Definition: base.cc:1666
gem5::BaseCache::CacheStats::overallHits
statistics::Formula overallHits
Number of hit for all accesses.
Definition: base.hh:1052
gem5::QueuedRequestPort::reqQueue
ReqPacketQueue & reqQueue
Packet queue used to store outgoing requests.
Definition: qport.hh:115
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::BaseCache::blkSize
const unsigned blkSize
Block size of this cache.
Definition: base.hh:888
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::BaseCache::CpuSidePort
The CPU-side port extends the base cache response port with access functions for functional,...
Definition: base.hh:311
gem5::BaseCache::regenerateBlkAddr
Addr regenerateBlkAddr(CacheBlk *blk)
Regenerate block address using tags.
Definition: base.cc:182
gem5::BaseCache::DataUpdate::isSecure
bool isSecure
Whether the block belongs to the secure address space.
Definition: base.hh:129
gem5::BaseCache::ppHit
ProbePointArg< PacketPtr > * ppHit
To probe when a cache hit occurs.
Definition: base.hh:359
gem5::BaseCache::CacheResponsePort::clearBlocked
void clearBlocked()
Return to normal operation and accept new requests.
Definition: base.cc:160
gem5::PacketQueue::schedSendEvent
void schedSendEvent(Tick when)
Schedule a send event if we are not already waiting for a retry.
Definition: packet_queue.cc:155
gem5::BaseCache::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt)
Performs the access specified by the request.
Definition: base.cc:559
gem5::BaseCache::CpuSidePort::recvTimingSnoopResp
virtual bool recvTimingSnoopResp(PacketPtr pkt) override
Receive a timing snoop response from the peer.
Definition: base.cc:2420
gem5::MemCmd::ReadReq
@ ReadReq
Definition: packet.hh:86
gem5::compression::Base
Base cache compressor interface.
Definition: base.hh:65
gem5::BaseCache::CacheCmdStats::mshrMissRate
statistics::Formula mshrMissRate
The miss rate in the MSHRs pre command and thread.
Definition: base.hh:1030
packet_queue.hh
gem5::BaseCache::CacheStats::blockedCauses
statistics::Vector blockedCauses
The number of times this cache blocked for each blocked cause.
Definition: base.hh:1082
gem5::BaseCache::CacheStats::writebacks
statistics::Vector writebacks
Number of blocks written back per thread.
Definition: base.hh:1088
GEM5_NO_DISCARD
#define GEM5_NO_DISCARD
Definition: compiler.hh:70
gem5::BaseCache::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: base.cc:192
gem5::BaseCache::CpuSidePort::CpuSidePort
CpuSidePort(const std::string &_name, BaseCache *_cache, const std::string &_label)
Definition: base.cc:2499
gem5::WriteAllocator::WriteMode::NO_ALLOCATE
@ NO_ALLOCATE
gem5::BaseCache::CacheRequestPort::schedSendEvent
void schedSendEvent(Tick time)
Schedule a send of a request packet (from the MSHR).
Definition: base.hh:161
gem5::MSHRQueue::allocate
MSHR * allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt, Tick when_ready, Counter order, bool alloc_on_fill)
Allocates a new MSHR for the request and size.
Definition: mshr_queue.cc:63
gem5::Queue::findMatch
Entry * findMatch(Addr blk_addr, bool is_secure, bool ignore_uncacheable=true) const
Find the first entry that matches the provided address.
Definition: queue.hh:168
gem5::BaseCache::CacheStats::overallMisses
statistics::Formula overallMisses
Number of misses for all accesses.
Definition: base.hh:1057
gem5::BaseCache::CacheCmdStats::missLatency
statistics::Vector missLatency
Total number of cycles per thread/command spent waiting for a miss.
Definition: base.hh:1012
base.hh
gem5::BaseCache::CacheRequestPort::isSnooping
virtual bool isSnooping() const
Memory-side port always snoops.
Definition: base.hh:180
gem5::BaseCache::CacheStats::dataExpansions
statistics::Scalar dataExpansions
Number of data expansions.
Definition: base.hh:1128
gem5::BaseCache::CacheResponsePort::mustSendRetry
bool mustSendRetry
Definition: base.hh:297
compiler.hh
gem5::BaseCache::CacheStats::demandMissRate
statistics::Formula demandMissRate
The miss rate of all demand accesses.
Definition: base.hh:1070
gem5::BaseCache::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: base.cc:1937
gem5::BaseCache::allocOnFill
bool allocOnFill(MemCmd cmd) const
Determine whether we should allocate on a fill or not.
Definition: base.hh:441
gem5::BaseCache::incHitCount
void incHitCount(PacketPtr pkt)
Definition: base.hh:1298
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseCache::Blocked_NoWBBuffers
@ Blocked_NoWBBuffers
Definition: base.hh:114
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::ArmISA::c
Bitfield< 29 > c
Definition: misc_types.hh:53
gem5::BaseCache::recvTimingSnoopResp
virtual void recvTimingSnoopResp(PacketPtr pkt)=0
Handle a snoop response.
gem5::BaseCache::Blocked_NoMSHRs
@ Blocked_NoMSHRs
Definition: base.hh:113
gem5::BaseCache::CpuSidePort::recvFunctional
virtual void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
Definition: base.cc:2478
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::BaseCache::doWritebacksAtomic
virtual void doWritebacksAtomic(PacketList &writebacks)=0
Send writebacks down the memory hierarchy in atomic mode.
gem5::BaseCache::getBlockSize
unsigned getBlockSize() const
Query block size of a cache.
Definition: base.hh:1157
gem5::BaseCache::inMissQueue
bool inMissQueue(Addr addr, bool is_secure) const
Definition: base.hh:1283
gem5::BaseCache::tempBlockWriteback
PacketPtr tempBlockWriteback
Writebacks from the tempBlock, resulting on the response path in atomic mode, must happen after the c...
Definition: base.hh:684
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::BaseCache::recvTimingReq
virtual void recvTimingReq(PacketPtr pkt)
Performs the access specified by the request.
Definition: base.cc:350
gem5::BaseCache::MemSidePort::recvTimingSnoopReq
virtual void recvTimingSnoopReq(PacketPtr pkt)
Receive a timing snoop request from the peer.
Definition: base.cc:2519
addr_range.hh
gem5::Cache
A coherent cache that can be arranged in flexible topologies.
Definition: cache.hh:67
gem5::BaseCache::MemSidePort::recvAtomicSnoop
virtual Tick recvAtomicSnoop(PacketPtr pkt)
Receive an atomic snoop request packet from our peer.
Definition: base.cc:2529
gem5::BaseCache::CacheStats::overallMissRate
statistics::Formula overallMissRate
The miss rate for all accesses.
Definition: base.hh:1072
gem5::WriteQueueEntry
Write queue entry.
Definition: write_queue_entry.hh:67
gem5::BaseCache::schedMemSideSendEvent
void schedMemSideSendEvent(Tick time)
Schedule a send event for the memory-side port.
Definition: base.hh:1265
gem5::WriteAllocator::noAllocateLimit
const uint32_t noAllocateLimit
Definition: base.hh:1475
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::BaseCache::maintainClusivity
void maintainClusivity(bool from_cache, CacheBlk *blk)
Maintain the clusivity of this cache by potentially invalidating a block.
Definition: base.cc:1422
gem5::BaseCache::isReadOnly
const bool isReadOnly
Is this cache read only, for example the instruction cache, or table-walker cache.
Definition: base.hh:943
gem5::BaseCache::CacheReqPacketQueue::sendDeferredPacket
virtual void sendDeferredPacket()
Override the normal sendDeferredPacket and do not only consider the transmit list (used for responses...
Definition: base.cc:2550
gem5::BaseCache::noTargetMSHR
MSHR * noTargetMSHR
Pointer to the MSHR that has no targets.
Definition: base.hh:974
gem5::BaseCache::CacheStats::demandAvgMissLatency
statistics::Formula demandAvgMissLatency
The average miss latency for demand misses.
Definition: base.hh:1075
gem5::BaseCache::clusivity
const enums::Clusivity clusivity
Clusivity with respect to the upstream cache, determining if we fill into both this cache and the cac...
Definition: base.hh:935
gem5::WriteQueue
A write queue for all eviction packets, i.e.
Definition: write_queue.hh:60
write_queue.hh
gem5::BaseCache::memInvalidate
virtual void memInvalidate() override
Invalidates all blocks in the cache.
Definition: base.cc:1718
gem5::BaseCache::CacheCmdStats::CacheCmdStats
CacheCmdStats(BaseCache &c, const std::string &name)
Definition: base.cc:1949
gem5::BaseCache::regProbePoints
void regProbePoints() override
Registers probes.
Definition: base.cc:2405
gem5::BaseCache::CacheStats::overallMshrMissLatency
statistics::Formula overallMshrMissLatency
Total cycle latency of overall MSHR misses.
Definition: base.hh:1106
gem5::BaseCache::CacheStats::demandMshrMisses
statistics::Formula demandMshrMisses
Demand misses that miss in the MSHRs.
Definition: base.hh:1096
cache_blk.hh
gem5::BaseCache::DataUpdate::addr
Addr addr
The updated block's address.
Definition: base.hh:127
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::BaseCache::isDirty
bool isDirty() const
Determine if there are any dirty blocks in the cache.
Definition: base.cc:1724
gem5::BaseCache::CacheStats::cmdStats
CacheCmdStats & cmdStats(const PacketPtr p)
Definition: base.hh:1043
gem5::BaseCache::allocateBlock
CacheBlk * allocateBlock(const PacketPtr pkt, PacketList &writebacks)
Allocate a new block and perform any necessary writebacks.
Definition: base.cc:1530
types.hh
gem5::BaseCache::CacheStats::dataContractions
statistics::Scalar dataContractions
Number of data contractions (blocks that had their compression factor improved).
Definition: base.hh:1134
qport.hh
gem5::BaseCache::CacheReqPacketQueue::checkConflictingSnoop
bool checkConflictingSnoop(const PacketPtr pkt)
Check if there is a conflicting snoop response about to be send out, and if so simply stall any reque...
Definition: base.hh:220
gem5::BaseCache::recvTimingSnoopReq
virtual void recvTimingSnoopReq(PacketPtr pkt)=0
Snoops bus transactions to maintain coherence.
gem5::BaseCache::fillLatency
const Cycles fillLatency
The latency to fill a cache block.
Definition: base.hh:910
clocked_object.hh
gem5::BaseCache::handleTimingReqHit
virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
Definition: base.cc:224
gem5::BaseCache::addrRanges
const AddrRangeList addrRanges
The address range to which the cache responds on the CPU side.
Definition: base.hh:982
gem5::BaseCache::CacheStats::avgBlocked
statistics::Formula avgBlocked
The average number of cycles blocked for each blocked cause.
Definition: base.hh:1085
gem5::BaseCache::system
System * system
System we are currently operating in.
Definition: base.hh:986
gem5::WriteAllocator::delay
bool delay(Addr blk_addr)
Access whether we need to delay the current write.
Definition: base.hh:1418
gem5::BaseCache::mshrQueue
MSHRQueue mshrQueue
Miss status registers.
Definition: base.hh:344
gem5::BaseCache::memSidePort
MemSidePort memSidePort
Definition: base.hh:339
gem5::CacheBlk::wasPrefetched
bool wasPrefetched() const
Check if this block was the result of a hardware prefetch, yet to be touched.
Definition: cache_blk.hh:249
gem5::BaseCache::handleUncacheableWriteResp
void handleUncacheableWriteResp(PacketPtr pkt)
Handling the special case of uncacheable write responses to make recvTimingResp less cluttered.
Definition: base.cc:408
gem5::BaseCache::getAddrRanges
const AddrRangeList & getAddrRanges() const
Definition: base.hh:1162
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::BaseCache::writebackClean
const bool writebackClean
Determine if clean lines should be written back or not.
Definition: base.hh:675
gem5::MemCmd::WriteReq
@ WriteReq
Definition: packet.hh:89
gem5::BaseCache::CacheCmdStats::mshrUncacheableLatency
statistics::Vector mshrUncacheableLatency
Total cycle latency of each MSHR miss, per command and thread.
Definition: base.hh:1028
gem5::BaseCache::CacheStats::demandHits
statistics::Formula demandHits
Number of hits for demand accesses.
Definition: base.hh:1050
gem5::QueueEntry
A queue entry base class, to be used by both the MSHRs and write-queue entries.
Definition: queue_entry.hh:62
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::MSHRQueue
A Class for maintaining a list of pending and allocated memory requests.
Definition: mshr_queue.hh:61
gem5::BaseCache::CacheResponsePort::blocked
bool blocked
Definition: base.hh:295
gem5::BaseCache::CacheStats::demandMshrMissRate
statistics::Formula demandMshrMissRate
The demand miss rate in the MSHRs.
Definition: base.hh:1112
gem5::BaseCache::invalidateVisitor
void invalidateVisitor(CacheBlk &blk)
Cache block visitor that invalidates all blocks in the cache.
Definition: base.cc:1760
gem5::BaseCache::writebackTempBlockAtomic
void writebackTempBlockAtomic()
Send the outstanding tempBlock writeback.
Definition: base.hh:691
gem5::BaseCache::getNextQueueEntry
QueueEntry * getNextQueueEntry()
Return the next queue entry to service, either a pending miss from the MSHR queue,...
Definition: base.cc:774
gem5::ReqPacketQueue
Definition: packet_queue.hh:226
gem5::BaseCache::inCache
bool inCache(Addr addr, bool is_secure) const
Definition: base.hh:1270
gem5::BaseCache::serviceMSHRTargets
virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)=0
Service non-deferred MSHR targets using the received response.
gem5::BaseCache::CpuSidePort::cache
BaseCache * cache
Definition: base.hh:316
gem5::BaseCache::lookupLatency
const Cycles lookupLatency
The latency of tag lookup of a cache.
Definition: base.hh:894
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::BaseCache::allocateMissBuffer
MSHR * allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send=true)
Definition: base.hh:1164
gem5::WriteAllocator::coalesce
bool coalesce() const
Should writes be coalesced? This is true if the mode is set to NO_ALLOCATE.
Definition: base.hh:1387
gem5::BaseTags::findBlock
virtual CacheBlk * findBlock(Addr addr, bool is_secure) const
Finds the block in the cache without touching it.
Definition: base.cc:80
gem5::BaseCache::CacheStats::demandMshrMissLatency
statistics::Formula demandMshrMissLatency
Total cycle latency of demand MSHR misses.
Definition: base.hh:1104
trace.hh
gem5::BaseCache::doWritebacks
virtual void doWritebacks(PacketList &writebacks, Tick forward_time)=0
Insert writebacks into the write buffer.
gem5::MemCmd::isLLSC
bool isLLSC() const
Definition: packet.hh:241
gem5::BaseCache::setBlocked
void setBlocked(BlockedCause cause)
Marks the access path of the cache as blocked for the given cause.
Definition: base.hh:1227
mshr_queue.hh
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::BaseCache::CacheStats::demandAvgMshrMissLatency
statistics::Formula demandAvgMshrMissLatency
The average latency of a demand MSHR miss.
Definition: base.hh:1117
gem5::PacketQueue::label
const std::string label
Label to use for print request packets label stack.
Definition: packet_queue.hh:110
gem5::WriteAllocator::delayThreshold
const uint32_t delayThreshold
The number of times the allocator will delay an WriteReq MSHR.
Definition: base.hh:1479
std::list< AddrRange >
gem5::BaseCache::CacheStats
Definition: base.hh:1037
gem5::BaseCache::writebackVisitor
void writebackVisitor(CacheBlk &blk)
Cache block visitor that writes back dirty cache blocks using functional writes.
Definition: base.cc:1737
gem5::BaseCache::CacheCmdStats
Definition: base.hh:988
gem5::BaseCache::numTarget
const int numTarget
The number of targets for each MSHR.
Definition: base.hh:925
gem5::BaseCache::createMissPacket
virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const =0
Create an appropriate downstream bus request packet.
gem5::BaseCache::CacheStats::demandMisses
statistics::Formula demandMisses
Number of misses for demand accesses.
Definition: base.hh:1055
gem5::SnoopRespPacketQueue
Definition: packet_queue.hh:262
probe.hh
gem5::BaseCache::functionalAccess
virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side)
Performs the access specified by the request.
Definition: base.cc:639
gem5::BaseCache::CacheResponsePort::sendRetryEvent
EventFunctionWrapper sendRetryEvent
Definition: base.hh:303
gem5::BaseCache::handleEvictions
bool handleEvictions(std::vector< CacheBlk * > &evict_blks, PacketList &writebacks)
Try to evict the given blocks.
Definition: base.cc:865
gem5::BaseTags
A common base class of Cache tagstore objects.
Definition: base.hh:73
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseCache::CacheStats::demandMissLatency
statistics::Formula demandMissLatency
Total number of cycles spent waiting for demand misses.
Definition: base.hh:1060
gem5::BaseCache::CacheCmdStats::cache
const BaseCache & cache
Definition: base.hh:1000
gem5::MemCmd::isPrefetch
bool isPrefetch() const
Definition: packet.hh:244
gem5::BaseCache::CacheReqPacketQueue::CacheReqPacketQueue
CacheReqPacketQueue(BaseCache &cache, RequestPort &port, SnoopRespPacketQueue &snoop_resp_queue, const std::string &label)
Definition: base.hh:199
gem5::BaseCache::MemSidePort::_snoopRespQueue
SnoopRespPacketQueue _snoopRespQueue
Definition: base.hh:245
gem5::BaseCache::forwardLatency
const Cycles forwardLatency
This is the forward latency of the cache.
Definition: base.hh:907
gem5::BaseCache::nextQueueReadyTime
Tick nextQueueReadyTime() const
Find next request ready time from among possible sources.
Definition: base.cc:1773
gem5::BaseCache::CacheCmdStats::avgMissLatency
statistics::Formula avgMissLatency
The average miss latency per command and thread.
Definition: base.hh:1018
gem5::QueueEntry::inService
bool inService
True if the entry has been sent downstream.
Definition: queue_entry.hh:110
gem5::BaseCache::CpuSidePort::getAddrRanges
virtual AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
Definition: base.cc:2492
gem5::BaseCache::CacheStats::overallAvgMshrUncacheableLatency
statistics::Formula overallAvgMshrUncacheableLatency
The average overall latency of an MSHR miss.
Definition: base.hh:1122
gem5::prefetch::Base
Definition: base.hh:72
gem5::BaseCache::CpuSidePort::recvAtomic
virtual Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
Definition: base.cc:2467
gem5::BaseCache::BlockedCause
BlockedCause
Reasons for caches to be blocked.
Definition: base.hh:111
write_queue_entry.hh
gem5::WriteAllocator
The write allocator inspects write packets and detects streaming patterns.
Definition: base.hh:1369
gem5::MemCmd::WriteLineReq
@ WriteLineReq
Definition: packet.hh:101
gem5::BaseCache::CacheReqPacketQueue
Override the default behaviour of sendDeferredPacket to enable the memory-side cache port to also sen...
Definition: base.hh:189
gem5::BaseCache::CacheRequestPort::CacheRequestPort
CacheRequestPort(const std::string &_name, BaseCache *_cache, ReqPacketQueue &_reqQueue, SnoopRespPacketQueue &_snoopRespQueue)
Definition: base.hh:169
gem5::BaseCache::handleFill
CacheBlk * handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, bool allocate)
Handle a fill operation caused by a received packet.
Definition: base.cc:1434
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::BaseCache::CacheStats::CacheStats
CacheStats(BaseCache &c)
Definition: base.cc:2111
gem5::BaseCache::calculateAccessLatency
Cycles calculateAccessLatency(const CacheBlk *blk, const uint32_t delay, const Cycles lookup_lat) const
Calculate access latency in ticks given a tag lookup latency, and whether access was a hit or miss.
Definition: base.cc:1119
gem5::BaseCache::writebackBlk
PacketPtr writebackBlk(CacheBlk *blk)
Create a writeback request for the given block.
Definition: base.cc:1616
gem5::BaseCache::CpuSidePort::tryTiming
virtual bool tryTiming(PacketPtr pkt) override
Availability request from the peer.
Definition: base.cc:2434
gem5::BaseCache::markInService
void markInService(WriteQueueEntry *entry)
Definition: base.hh:418
gem5::WriteAllocator::resetDelay
void resetDelay(Addr blk_addr)
Clear delay counter for the input block.
Definition: base.hh:1432
gem5::BaseCache::satisfyRequest
virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false)
Perform any necessary updates to the block and perform any data exchange between the packet and the b...
Definition: base.cc:1012
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::BaseCache::CacheStats::overallMshrUncacheableLatency
statistics::Formula overallMshrUncacheableLatency
Total cycle latency of overall MSHR misses.
Definition: base.hh:1109
eventq.hh
gem5::BaseCache::responseLatency
const Cycles responseLatency
The latency of sending reponse to its upper level cache/core on a linefill.
Definition: base.hh:917
gem5::BaseCache::compressor
compression::Base * compressor
Compression method being used.
Definition: base.hh:353

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