gem5  v21.1.0.2
Classes | Public Types | Public Member Functions | Public Attributes | Protected Types | Protected Member Functions | Protected Attributes | List of all members
gem5::BaseCache Class Referenceabstract

A basic cache interface. More...

#include <base.hh>

Inheritance diagram for gem5::BaseCache:
gem5::ClockedObject gem5::SimObject gem5::Clocked gem5::EventManager gem5::Serializable gem5::Drainable gem5::statistics::Group gem5::Named gem5::Cache gem5::NoncoherentCache

Classes

struct  CacheCmdStats
 
class  CacheReqPacketQueue
 Override the default behaviour of sendDeferredPacket to enable the memory-side cache port to also send requests based on the current MSHR status. More...
 
class  CacheRequestPort
 A cache request port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks). More...
 
class  CacheResponsePort
 A cache response port is used for the CPU-side port of the cache, and it is basically a simple timing port that uses a transmit list for responses to the CPU (or connected requestor). More...
 
struct  CacheStats
 
class  CpuSidePort
 The CPU-side port extends the base cache response port with access functions for functional, atomic and timing requests. More...
 
struct  DataUpdate
 A data contents update is composed of the updated block's address, the old contents, and the new contents. More...
 
class  MemSidePort
 The memory-side port extends the base cache request port with access functions for functional, atomic and timing snoops. More...
 

Public Types

enum  BlockedCause { Blocked_NoMSHRs = MSHRQueue_MSHRs, Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, Blocked_NoTargets, NUM_BLOCKED_CAUSES }
 Reasons for caches to be blocked. More...
 
- Public Types inherited from gem5::ClockedObject
using Params = ClockedObjectParams
 Parameters of ClockedObject. More...
 
- Public Types inherited from gem5::SimObject
typedef SimObjectParams Params
 

Public Member Functions

void regProbePoints () override
 Registers probes. More...
 
 BaseCache (const BaseCacheParams &p, unsigned blk_size)
 
 ~BaseCache ()
 
void init () override
 init() is called after all C++ SimObjects have been created and all ports are connected. More...
 
PortgetPort (const std::string &if_name, PortID idx=InvalidPortID) override
 Get a port with a given name and index. More...
 
unsigned getBlockSize () const
 Query block size of a cache. More...
 
const AddrRangeListgetAddrRanges () const
 
MSHRallocateMissBuffer (PacketPtr pkt, Tick time, bool sched_send=true)
 
void allocateWriteBuffer (PacketPtr pkt, Tick time)
 
bool isBlocked () const
 Returns true if the cache is blocked for accesses. More...
 
void setBlocked (BlockedCause cause)
 Marks the access path of the cache as blocked for the given cause. More...
 
void clearBlocked (BlockedCause cause)
 Marks the cache as unblocked for the given cause. More...
 
void schedMemSideSendEvent (Tick time)
 Schedule a send event for the memory-side port. More...
 
bool inCache (Addr addr, bool is_secure) const
 
bool hasBeenPrefetched (Addr addr, bool is_secure) const
 
bool inMissQueue (Addr addr, bool is_secure) const
 
void incMissCount (PacketPtr pkt)
 
void incHitCount (PacketPtr pkt)
 
bool coalesce () const
 Checks if the cache is coalescing writes. More...
 
void writebackVisitor (CacheBlk &blk)
 Cache block visitor that writes back dirty cache blocks using functional writes. More...
 
void invalidateVisitor (CacheBlk &blk)
 Cache block visitor that invalidates all blocks in the cache. More...
 
virtual bool sendMSHRQueuePacket (MSHR *mshr)
 Take an MSHR, turn it into a suitable downstream packet, and send it out. More...
 
bool sendWriteQueuePacket (WriteQueueEntry *wq_entry)
 Similar to sendMSHR, but for a write-queue entry instead. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize the state of the caches. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::ClockedObject
 ClockedObject (const ClockedObjectParams &p)
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::SimObject
const Paramsparams () const
 
 SimObject (const Params &p)
 
virtual ~SimObject ()
 
virtual void loadState (CheckpointIn &cp)
 loadState() is called on each SimObject when restoring from a checkpoint. More...
 
virtual void initState ()
 initState() is called on each SimObject when not restoring from a checkpoint. More...
 
virtual void regProbeListeners ()
 Register probe listeners for this object. More...
 
ProbeManagergetProbeManager ()
 Get the probe manager for this object. More...
 
virtual void startup ()
 startup() is the final initialization call before simulation. More...
 
DrainState drain () override
 Provide a default implementation of the drain interface for objects that don't need draining. More...
 
void serialize (CheckpointOut &cp) const override
 Serialize an object. More...
 
void unserialize (CheckpointIn &cp) override
 Unserialize an object. More...
 
- Public Member Functions inherited from gem5::EventManager
EventQueueeventQueue () const
 
void schedule (Event &event, Tick when)
 
void deschedule (Event &event)
 
void reschedule (Event &event, Tick when, bool always=false)
 
void schedule (Event *event, Tick when)
 
void deschedule (Event *event)
 
void reschedule (Event *event, Tick when, bool always=false)
 
void wakeupEventQueue (Tick when=(Tick) -1)
 This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...
 
void setCurTick (Tick newVal)
 
 EventManager (EventManager &em)
 Event manger manages events in the event queue. More...
 
 EventManager (EventManager *em)
 
 EventManager (EventQueue *eq)
 
- Public Member Functions inherited from gem5::Serializable
 Serializable ()
 
virtual ~Serializable ()
 
void serializeSection (CheckpointOut &cp, const char *name) const
 Serialize an object into a new section. More...
 
void serializeSection (CheckpointOut &cp, const std::string &name) const
 
void unserializeSection (CheckpointIn &cp, const char *name)
 Unserialize an a child object. More...
 
void unserializeSection (CheckpointIn &cp, const std::string &name)
 
- Public Member Functions inherited from gem5::Drainable
DrainState drainState () const
 Return the current drain state of an object. More...
 
virtual void notifyFork ()
 Notify a child process of a fork. More...
 
- Public Member Functions inherited from gem5::statistics::Group
 Group (Group *parent, const char *name=nullptr)
 Construct a new statistics group. More...
 
virtual ~Group ()
 
virtual void regStats ()
 Callback to set stat parameters. More...
 
virtual void resetStats ()
 Callback to reset stats. More...
 
virtual void preDumpStats ()
 Callback before stats are dumped. More...
 
void addStat (statistics::Info *info)
 Register a stat with this group. More...
 
const std::map< std::string, Group * > & getStatGroups () const
 Get all child groups associated with this object. More...
 
const std::vector< Info * > & getStats () const
 Get all stats associated with this object. More...
 
void addStatGroup (const char *name, Group *block)
 Add a stat block as a child of this block. More...
 
const InforesolveStat (std::string name) const
 Resolve a stat by its name within this group. More...
 
void mergeStatGroup (Group *block)
 Merge the contents (stats & children) of a block to this block. More...
 
 Group ()=delete
 
 Group (const Group &)=delete
 
Groupoperator= (const Group &)=delete
 
- Public Member Functions inherited from gem5::Named
 Named (const std::string &name_)
 
virtual ~Named ()=default
 
virtual std::string name () const
 
- Public Member Functions inherited from gem5::Clocked
void updateClockPeriod ()
 Update the tick to the current tick. More...
 
Tick clockEdge (Cycles cycles=Cycles(0)) const
 Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...
 
Cycles curCycle () const
 Determine the current cycle, corresponding to a tick aligned to a clock edge. More...
 
Tick nextCycle () const
 Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...
 
uint64_t frequency () const
 
Tick clockPeriod () const
 
double voltage () const
 
Cycles ticksToCycles (Tick t) const
 
Tick cyclesToTicks (Cycles c) const
 

Public Attributes

Systemsystem
 System we are currently operating in. More...
 
gem5::BaseCache::CacheStats stats
 
- Public Attributes inherited from gem5::ClockedObject
PowerStatepowerState
 

Protected Types

enum  MSHRQueueIndex { MSHRQueue_MSHRs, MSHRQueue_WriteBuffer }
 Indexes to enumerate the MSHR queues. More...
 

Protected Member Functions

void markInService (MSHR *mshr, bool pending_modified_resp)
 Mark a request as in service (sent downstream in the memory system), effectively making this MSHR the ordering point. More...
 
void markInService (WriteQueueEntry *entry)
 
bool allocOnFill (MemCmd cmd) const
 Determine whether we should allocate on a fill or not. More...
 
Addr regenerateBlkAddr (CacheBlk *blk)
 Regenerate block address using tags. More...
 
Cycles calculateTagOnlyLatency (const uint32_t delay, const Cycles lookup_lat) const
 Calculate latency of accesses that only touch the tag array. More...
 
Cycles calculateAccessLatency (const CacheBlk *blk, const uint32_t delay, const Cycles lookup_lat) const
 Calculate access latency in ticks given a tag lookup latency, and whether access was a hit or miss. More...
 
virtual bool access (PacketPtr pkt, CacheBlk *&blk, Cycles &lat, PacketList &writebacks)
 Does all the processing necessary to perform the provided request. More...
 
virtual void handleTimingReqHit (PacketPtr pkt, CacheBlk *blk, Tick request_time)
 
virtual void handleTimingReqMiss (PacketPtr pkt, CacheBlk *blk, Tick forward_time, Tick request_time)=0
 
void handleTimingReqMiss (PacketPtr pkt, MSHR *mshr, CacheBlk *blk, Tick forward_time, Tick request_time)
 
virtual void recvTimingReq (PacketPtr pkt)
 Performs the access specified by the request. More...
 
void handleUncacheableWriteResp (PacketPtr pkt)
 Handling the special case of uncacheable write responses to make recvTimingResp less cluttered. More...
 
virtual void serviceMSHRTargets (MSHR *mshr, const PacketPtr pkt, CacheBlk *blk)=0
 Service non-deferred MSHR targets using the received response. More...
 
virtual void recvTimingResp (PacketPtr pkt)
 Handles a response (cache line fill/write ack) from the bus. More...
 
virtual void recvTimingSnoopReq (PacketPtr pkt)=0
 Snoops bus transactions to maintain coherence. More...
 
virtual void recvTimingSnoopResp (PacketPtr pkt)=0
 Handle a snoop response. More...
 
virtual Cycles handleAtomicReqMiss (PacketPtr pkt, CacheBlk *&blk, PacketList &writebacks)=0
 Handle a request in atomic mode that missed in this cache. More...
 
virtual Tick recvAtomic (PacketPtr pkt)
 Performs the access specified by the request. More...
 
virtual Tick recvAtomicSnoop (PacketPtr pkt)=0
 Snoop for the provided request in the cache and return the estimated time taken. More...
 
virtual void functionalAccess (PacketPtr pkt, bool from_cpu_side)
 Performs the access specified by the request. More...
 
void updateBlockData (CacheBlk *blk, const PacketPtr cpkt, bool has_old_data)
 Update the data contents of a block. More...
 
void cmpAndSwap (CacheBlk *blk, PacketPtr pkt)
 Handle doing the Compare and Swap function for SPARC. More...
 
QueueEntrygetNextQueueEntry ()
 Return the next queue entry to service, either a pending miss from the MSHR queue, a buffered write from the write buffer, or something from the prefetcher. More...
 
virtual void doWritebacks (PacketList &writebacks, Tick forward_time)=0
 Insert writebacks into the write buffer. More...
 
virtual void doWritebacksAtomic (PacketList &writebacks)=0
 Send writebacks down the memory hierarchy in atomic mode. More...
 
virtual PacketPtr createMissPacket (PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const =0
 Create an appropriate downstream bus request packet. More...
 
void writebackTempBlockAtomic ()
 Send the outstanding tempBlock writeback. More...
 
bool updateCompressionData (CacheBlk *&blk, const uint64_t *data, PacketList &writebacks)
 When a block is overwriten, its compression information must be updated, and it may need to be recompressed. More...
 
virtual void satisfyRequest (PacketPtr pkt, CacheBlk *blk, bool deferred_response=false, bool pending_downgrade=false)
 Perform any necessary updates to the block and perform any data exchange between the packet and the block. More...
 
void maintainClusivity (bool from_cache, CacheBlk *blk)
 Maintain the clusivity of this cache by potentially invalidating a block. More...
 
bool handleEvictions (std::vector< CacheBlk * > &evict_blks, PacketList &writebacks)
 Try to evict the given blocks. More...
 
CacheBlkhandleFill (PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, bool allocate)
 Handle a fill operation caused by a received packet. More...
 
CacheBlkallocateBlock (const PacketPtr pkt, PacketList &writebacks)
 Allocate a new block and perform any necessary writebacks. More...
 
virtual GEM5_NO_DISCARD PacketPtr evictBlock (CacheBlk *blk)=0
 Evict a cache block. More...
 
void evictBlock (CacheBlk *blk, PacketList &writebacks)
 Evict a cache block. More...
 
void invalidateBlock (CacheBlk *blk)
 Invalidate a cache block. More...
 
PacketPtr writebackBlk (CacheBlk *blk)
 Create a writeback request for the given block. More...
 
PacketPtr writecleanBlk (CacheBlk *blk, Request::Flags dest, PacketId id)
 Create a writeclean request for the given block. More...
 
virtual void memWriteback () override
 Write back dirty blocks in the cache using functional accesses. More...
 
virtual void memInvalidate () override
 Invalidates all blocks in the cache. More...
 
bool isDirty () const
 Determine if there are any dirty blocks in the cache. More...
 
bool inRange (Addr addr) const
 Determine if an address is in the ranges covered by this cache. More...
 
Tick nextQueueReadyTime () const
 Find next request ready time from among possible sources. More...
 
- Protected Member Functions inherited from gem5::Drainable
 Drainable ()
 
virtual ~Drainable ()
 
virtual void drainResume ()
 Resume execution after a successful drain. More...
 
void signalDrainDone () const
 Signal that an object is drained. More...
 
- Protected Member Functions inherited from gem5::Clocked
 Clocked (ClockDomain &clk_domain)
 Create a clocked object and set the clock domain based on the parameters. More...
 
 Clocked (Clocked &)=delete
 
Clockedoperator= (Clocked &)=delete
 
virtual ~Clocked ()
 Virtual destructor due to inheritance. More...
 
void resetClock () const
 Reset the object's clock using the current global tick value. More...
 
virtual void clockPeriodUpdated ()
 A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...
 

Protected Attributes

CpuSidePort cpuSidePort
 
MemSidePort memSidePort
 
MSHRQueue mshrQueue
 Miss status registers. More...
 
WriteQueue writeBuffer
 Write/writeback buffer. More...
 
BaseTagstags
 Tag and data Storage. More...
 
compression::Basecompressor
 Compression method being used. More...
 
prefetch::Baseprefetcher
 Prefetcher. More...
 
ProbePointArg< PacketPtr > * ppHit
 To probe when a cache hit occurs. More...
 
ProbePointArg< PacketPtr > * ppMiss
 To probe when a cache miss occurs. More...
 
ProbePointArg< PacketPtr > * ppFill
 To probe when a cache fill occurs. More...
 
ProbePointArg< DataUpdate > * ppDataUpdate
 To probe when the contents of a block are updated. More...
 
WriteAllocator *const writeAllocator
 The writeAllocator drive optimizations for streaming writes. More...
 
TempCacheBlktempBlock
 Temporary cache block for occasional transitory use. More...
 
std::unique_ptr< PacketpendingDelete
 Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call. More...
 
const bool writebackClean
 Determine if clean lines should be written back or not. More...
 
PacketPtr tempBlockWriteback
 Writebacks from the tempBlock, resulting on the response path in atomic mode, must happen after the call to recvAtomic has finished (for the right ordering of the packets). More...
 
EventFunctionWrapper writebackTempBlockAtomicEvent
 An event to writeback the tempBlock after recvAtomic finishes. More...
 
const unsigned blkSize
 Block size of this cache. More...
 
const Cycles lookupLatency
 The latency of tag lookup of a cache. More...
 
const Cycles dataLatency
 The latency of data access of a cache. More...
 
const Cycles forwardLatency
 This is the forward latency of the cache. More...
 
const Cycles fillLatency
 The latency to fill a cache block. More...
 
const Cycles responseLatency
 The latency of sending reponse to its upper level cache/core on a linefill. More...
 
const bool sequentialAccess
 Whether tags and data are accessed sequentially. More...
 
const int numTarget
 The number of targets for each MSHR. More...
 
bool forwardSnoops
 Do we forward snoops from mem side port through to cpu side port? More...
 
const enums::Clusivity clusivity
 Clusivity with respect to the upstream cache, determining if we fill into both this cache and the cache above on a miss. More...
 
const bool isReadOnly
 Is this cache read only, for example the instruction cache, or table-walker cache. More...
 
const bool replaceExpansions
 when a data expansion of a compressed block happens it will not be able to co-allocate where it is at anymore. More...
 
const bool moveContractions
 Similar to data expansions, after a block improves its compression, it may need to be moved elsewhere compatible with the new compression factor, or, if not required by the compaction method, it may be moved to co-allocate with an existing block and thus free an entry. More...
 
uint8_t blocked
 Bit vector of the blocking reasons for the access path. More...
 
uint64_t order
 Increasing order number assigned to each incoming request. More...
 
Cycles blockedCycle
 Stores time the cache blocked for statistics. More...
 
MSHRnoTargetMSHR
 Pointer to the MSHR that has no targets. More...
 
Counter missCount
 The number of misses to trigger an exit event. More...
 
const AddrRangeList addrRanges
 The address range to which the cache responds on the CPU side. More...
 
- Protected Attributes inherited from gem5::SimObject
const SimObjectParams & _params
 Cached copy of the object parameters. More...
 
- Protected Attributes inherited from gem5::EventManager
EventQueueeventq
 A pointer to this object's event queue. More...
 

Additional Inherited Members

- Static Public Member Functions inherited from gem5::SimObject
static void serializeAll (const std::string &cpt_dir)
 Create a checkpoint by serializing all SimObjects in the system. More...
 
static SimObjectfind (const char *name)
 Find the SimObject with the given name and return a pointer to it. More...
 
static void setSimObjectResolver (SimObjectResolver *resolver)
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
static SimObjectResolvergetSimObjectResolver ()
 There is a single object name resolver, and it is only set when simulation is restoring from checkpoints. More...
 
- Static Public Member Functions inherited from gem5::Serializable
static const std::string & currentSection ()
 Gets the fully-qualified name of the active section. More...
 
static void generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
 Generate a checkpoint file so that the serialization can be routed to it. More...
 

Detailed Description

A basic cache interface.

Implements some common functions for speed.

Definition at line 95 of file base.hh.

Member Enumeration Documentation

◆ BlockedCause

Reasons for caches to be blocked.

Enumerator
Blocked_NoMSHRs 
Blocked_NoWBBuffers 
Blocked_NoTargets 
NUM_BLOCKED_CAUSES 

Definition at line 111 of file base.hh.

◆ MSHRQueueIndex

Indexes to enumerate the MSHR queues.

Enumerator
MSHRQueue_MSHRs 
MSHRQueue_WriteBuffer 

Definition at line 101 of file base.hh.

Constructor & Destructor Documentation

◆ BaseCache()

gem5::BaseCache::BaseCache ( const BaseCacheParams &  p,
unsigned  blk_size 
)

Definition at line 79 of file base.cc.

References writebackTempBlockAtomic().

◆ ~BaseCache()

gem5::BaseCache::~BaseCache ( )

Definition at line 139 of file base.cc.

References tempBlock.

Member Function Documentation

◆ access()

bool gem5::BaseCache::access ( PacketPtr  pkt,
CacheBlk *&  blk,
Cycles lat,
PacketList writebacks 
)
protectedvirtual

Does all the processing necessary to perform the provided request.

Parameters
pktThe memory request to perform.
blkThe cache block to be updated.
latThe latency of the access.
writebacksList for any writebacks that need to be performed.
Returns
Boolean indicating whether the request was satisfied.

Reimplemented in gem5::Cache, and gem5::NoncoherentCache.

Definition at line 1153 of file base.cc.

References gem5::BaseTags::accessBlock(), allocateBlock(), blkSize, calculateAccessLatency(), calculateTagOnlyLatency(), chatty_assert, gem5::MemCmd::CleanEvict, gem5::Packet::clearBlockCached(), gem5::Clocked::clockEdge(), gem5::Packet::cmd, compressor, gem5::Clocked::cyclesToTicks(), gem5::CacheBlk::DirtyBit, DPRINTF, fillLatency, gem5::Queue< Entry >::findMatch(), gem5::Packet::fromCache(), gem5::Packet::getAddr(), gem5::Packet::getConstPtr(), gem5::compression::Base::getDecompressionLatency(), gem5::WriteQueueEntry::getNumTargets(), gem5::Packet::getSize(), gem5::WriteQueueEntry::getTarget(), gem5::Packet::hasSharers(), gem5::Packet::headerDelay, incHitCount(), incMissCount(), invalidateBlock(), gem5::Packet::isCleanEviction(), gem5::Packet::isEviction(), gem5::Packet::isLLSC(), gem5::Packet::isRead(), isReadOnly, gem5::Packet::isRequest(), gem5::Packet::isSecure(), gem5::CacheBlk::isSet(), gem5::TaggedEntry::isValid(), gem5::Packet::isWrite(), gem5::Packet::isWriteback(), maintainClusivity(), markInService(), mshrQueue, gem5::Named::name(), gem5::Packet::needsResponse(), gem5::Packet::needsWritable(), gem5::Packet::payloadDelay, gem5::QueueEntry::Target::pkt, gem5::CacheBlk::print(), gem5::Packet::print(), gem5::CacheBlk::ReadableBit, gem5::Packet::req, satisfyRequest(), gem5::CacheBlk::setCoherenceBits(), gem5::CacheBlk::setWhenReady(), tags, updateBlockData(), updateCompressionData(), gem5::CacheBlk::WritableBit, gem5::MemCmd::WritebackClean, gem5::MemCmd::WritebackDirty, writeBuffer, gem5::MemCmd::WriteClean, and gem5::Packet::writeThrough().

Referenced by gem5::NoncoherentCache::access(), gem5::Cache::access(), recvAtomic(), and recvTimingReq().

◆ allocateBlock()

CacheBlk * gem5::BaseCache::allocateBlock ( const PacketPtr  pkt,
PacketList writebacks 
)
protected

Allocate a new block and perform any necessary writebacks.

Find a victim block and if necessary prepare writebacks for any existing data. May return nullptr if there are no replaceable blocks. If a replaceable block is found, it inserts the new block in its place. The new block, however, is not set as valid yet.

Parameters
pktPacket holding the address to update
writebacksA list of writeback packets for the evicted blocks
Returns
the allocated block

Definition at line 1530 of file base.cc.

References gem5::X86ISA::addr, blkSize, gem5::compression::Base::compress(), compressor, DPRINTF, gem5::BaseTags::findVictim(), gem5::Packet::getAddr(), gem5::Packet::getConstPtr(), handleEvictions(), gem5::Packet::hasData(), gem5::BaseTags::insertBlock(), gem5::Packet::isSecure(), gem5::CacheBlk::print(), gem5::compression::Base::setDecompressionLatency(), gem5::compression::Base::setSizeBits(), and tags.

Referenced by access(), and handleFill().

◆ allocateMissBuffer()

MSHR* gem5::BaseCache::allocateMissBuffer ( PacketPtr  pkt,
Tick  time,
bool  sched_send = true 
)
inline

◆ allocateWriteBuffer()

void gem5::BaseCache::allocateWriteBuffer ( PacketPtr  pkt,
Tick  time 
)
inline

◆ allocOnFill()

bool gem5::BaseCache::allocOnFill ( MemCmd  cmd) const
inlineprotected

Determine whether we should allocate on a fill or not.

If this cache is mostly inclusive with regards to the upstream cache(s) we always allocate (for any non-forwarded and cacheable requests). In the case of a mostly exclusive cache, we allocate on fill if the packet did not come from a cache, thus if we: are dealing with a whole-line write (the latter behaves much like a writeback), the original target packet came from a non-caching source, or if we are performing a prefetch or LLSC.

Parameters
cmdCommand of the incoming requesting packet
Returns
Whether we should allocate on the fill

Definition at line 441 of file base.hh.

References clusivity, gem5::MemCmd::isLLSC(), gem5::MemCmd::isPrefetch(), gem5::MemCmd::ReadReq, gem5::MemCmd::WriteLineReq, and gem5::MemCmd::WriteReq.

Referenced by allocateMissBuffer(), gem5::NoncoherentCache::handleAtomicReqMiss(), gem5::Cache::handleAtomicReqMiss(), and handleTimingReqMiss().

◆ calculateAccessLatency()

Cycles gem5::BaseCache::calculateAccessLatency ( const CacheBlk blk,
const uint32_t  delay,
const Cycles  lookup_lat 
) const
protected

Calculate access latency in ticks given a tag lookup latency, and whether access was a hit or miss.

Parameters
blkThe cache block that was accessed.
delayThe delay until the packet's metadata is present.
lookup_latLatency of the respective tag lookup.
Returns
The number of ticks that pass due to a block access.

Definition at line 1119 of file base.cc.

References calculateTagOnlyLatency(), gem5::curTick(), dataLatency, gem5::CacheBlk::getWhenReady(), sequentialAccess, gem5::Clocked::tick, and gem5::Clocked::ticksToCycles().

Referenced by access().

◆ calculateTagOnlyLatency()

Cycles gem5::BaseCache::calculateTagOnlyLatency ( const uint32_t  delay,
const Cycles  lookup_lat 
) const
protected

Calculate latency of accesses that only touch the tag array.

See also
calculateAccessLatency
Parameters
delayThe delay until the packet's metadata is present.
lookup_latLatency of the respective tag lookup.
Returns
The number of ticks that pass due to a tag-only access.

Definition at line 1110 of file base.cc.

References gem5::Clocked::ticksToCycles().

Referenced by access(), and calculateAccessLatency().

◆ clearBlocked()

void gem5::BaseCache::clearBlocked ( BlockedCause  cause)
inline

Marks the cache as unblocked for the given cause.

This also clears the blocked flags in the appropriate interfaces.

Parameters
causeThe newly unblocked cause.
Warning
Calling this function can cause a blocked request on the bus to access the cache. The cache must be in a state to handle that request.

Definition at line 1246 of file base.hh.

References blocked, blockedCycle, gem5::BaseCache::CacheStats::blockedCycles, gem5::BaseCache::CacheResponsePort::clearBlocked(), cpuSidePort, gem5::Clocked::curCycle(), DPRINTF, and stats.

Referenced by markInService(), recvTimingResp(), and gem5::Cache::sendMSHRQueuePacket().

◆ cmpAndSwap()

void gem5::BaseCache::cmpAndSwap ( CacheBlk blk,
PacketPtr  pkt 
)
protected

◆ coalesce()

bool gem5::BaseCache::coalesce ( ) const

Checks if the cache is coalescing writes.

Returns
True if the cache is coalescing writes

Definition at line 1731 of file base.cc.

References gem5::WriteAllocator::coalesce(), and writeAllocator.

Referenced by gem5::prefetch::Base::probeNotify().

◆ createMissPacket()

virtual PacketPtr gem5::BaseCache::createMissPacket ( PacketPtr  cpu_pkt,
CacheBlk blk,
bool  needs_writable,
bool  is_whole_line_write 
) const
protectedpure virtual

Create an appropriate downstream bus request packet.

Creates a new packet with the request to be send to the memory below, or nullptr if the current request in cpu_pkt should just be forwarded on.

Parameters
cpu_pktThe miss packet that needs to be satisfied.
blkThe referenced block, can be nullptr.
needs_writableIndicates that the block must be writable even if the request in cpu_pkt doesn't indicate that.
is_whole_line_writeTrue if there are writes for the whole line
Returns
A packet send to the memory below

Implemented in gem5::Cache, and gem5::NoncoherentCache.

Referenced by sendMSHRQueuePacket().

◆ doWritebacks()

virtual void gem5::BaseCache::doWritebacks ( PacketList writebacks,
Tick  forward_time 
)
protectedpure virtual

Insert writebacks into the write buffer.

Implemented in gem5::Cache, and gem5::NoncoherentCache.

Referenced by recvTimingReq(), recvTimingResp(), and sendMSHRQueuePacket().

◆ doWritebacksAtomic()

virtual void gem5::BaseCache::doWritebacksAtomic ( PacketList writebacks)
protectedpure virtual

Send writebacks down the memory hierarchy in atomic mode.

Implemented in gem5::Cache, and gem5::NoncoherentCache.

Referenced by recvAtomic(), and writebackTempBlockAtomic().

◆ evictBlock() [1/2]

virtual GEM5_NO_DISCARD PacketPtr gem5::BaseCache::evictBlock ( CacheBlk blk)
protectedpure virtual

Evict a cache block.

Performs a writeback if necesssary and invalidates the block

Parameters
blkBlock to invalidate
Returns
A packet with the writeback, can be nullptr

Implemented in gem5::Cache, and gem5::NoncoherentCache.

Referenced by gem5::Cache::access(), evictBlock(), handleEvictions(), recvAtomic(), and recvTimingResp().

◆ evictBlock() [2/2]

void gem5::BaseCache::evictBlock ( CacheBlk blk,
PacketList writebacks 
)
protected

Evict a cache block.

Performs a writeback if necesssary and invalidates the block

Parameters
blkBlock to invalidate
writebacksReturn a list of packets with writebacks

Definition at line 1607 of file base.cc.

References evictBlock().

◆ functionalAccess()

void gem5::BaseCache::functionalAccess ( PacketPtr  pkt,
bool  from_cpu_side 
)
protectedvirtual

◆ getAddrRanges()

const AddrRangeList& gem5::BaseCache::getAddrRanges ( ) const
inline

Definition at line 1162 of file base.hh.

References addrRanges.

◆ getBlockSize()

unsigned gem5::BaseCache::getBlockSize ( ) const
inline

Query block size of a cache.

Returns
The block size

Definition at line 1157 of file base.hh.

References blkSize.

Referenced by gem5::prefetch::Base::setCache().

◆ getNextQueueEntry()

QueueEntry * gem5::BaseCache::getNextQueueEntry ( )
protected

◆ getPort()

Port & gem5::BaseCache::getPort ( const std::string &  if_name,
PortID  idx = InvalidPortID 
)
overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters
if_namePort name
idxIndex in the case of a VectorPort
Returns
A reference to the given port

Reimplemented from gem5::SimObject.

Definition at line 201 of file base.cc.

References cpuSidePort, gem5::SimObject::getPort(), and memSidePort.

◆ handleAtomicReqMiss()

virtual Cycles gem5::BaseCache::handleAtomicReqMiss ( PacketPtr  pkt,
CacheBlk *&  blk,
PacketList writebacks 
)
protectedpure virtual

Handle a request in atomic mode that missed in this cache.

Creates a downstream request, sends it to the memory below and handles the response. As we are in atomic mode all operations are performed immediately.

Parameters
pktThe packet with the requests
blkThe referenced block
writebacksA list with packets for any performed writebacks
Returns
Cycles for handling the request

Implemented in gem5::Cache, and gem5::NoncoherentCache.

Referenced by recvAtomic().

◆ handleEvictions()

bool gem5::BaseCache::handleEvictions ( std::vector< CacheBlk * > &  evict_blks,
PacketList writebacks 
)
protected

Try to evict the given blocks.

If any of them is a transient eviction, that is, the block is present in the MSHR queue all evictions are cancelled since handling such cases has not been implemented.

Parameters
evict_blksBlocks marked for eviction.
writebacksList for any writebacks that need to be performed.
Returns
False if any of the evicted blocks is in transient state.

Definition at line 865 of file base.cc.

References evictBlock(), gem5::Queue< Entry >::findMatch(), gem5::MSHR::isCleaning(), mshrQueue, gem5::MSHR::needsWritable(), regenerateBlkAddr(), gem5::BaseCache::CacheStats::replacements, stats, and gem5::CacheBlk::WritableBit.

Referenced by allocateBlock(), and updateCompressionData().

◆ handleFill()

CacheBlk * gem5::BaseCache::handleFill ( PacketPtr  pkt,
CacheBlk blk,
PacketList writebacks,
bool  allocate 
)
protected

Handle a fill operation caused by a received packet.

Populates a cache block and handles all outstanding requests for the satisfied fill request. This version takes two memory requests. One contains the fill data, the other is an optional target to satisfy. Note that the reason we return a list of writebacks rather than inserting them directly in the write buffer is that this function is called by both atomic and timing-mode accesses, and in atomic mode we don't mess with the write buffer (we just perform the writebacks atomically once the original request is complete).

Parameters
pktThe memory request with the fill data.
blkThe cache block if it already exists.
writebacksList for any writebacks that need to be performed.
allocateWhether to allocate a block or use the temp block
Returns
Pointer to the new cache block.

Definition at line 1434 of file base.cc.

References gem5::X86ISA::addr, allocateBlock(), blkSize, gem5::Packet::cacheResponding(), chatty_assert, gem5::Clocked::clockEdge(), gem5::Packet::cmd, gem5::CacheBlk::DirtyBit, DPRINTF, fillLatency, gem5::Queue< Entry >::findMatch(), gem5::Packet::getAddr(), gem5::Packet::getBlockAddr(), gem5::Packet::getSize(), gem5::Packet::hasData(), gem5::Packet::hasSharers(), gem5::Packet::headerDelay, gem5::TempCacheBlk::insert(), gem5::MemCmd::InvalidateResp, gem5::Packet::isRead(), isReadOnly, gem5::Packet::isResponse(), gem5::TaggedEntry::isSecure(), gem5::Packet::isSecure(), gem5::TaggedEntry::isValid(), gem5::Named::name(), gem5::Packet::payloadDelay, gem5::CacheBlk::print(), gem5::CacheBlk::ReadableBit, regenerateBlkAddr(), gem5::CacheBlk::setCoherenceBits(), gem5::CacheBlk::setWhenReady(), tempBlock, updateBlockData(), gem5::CacheBlk::WritableBit, and writeBuffer.

Referenced by gem5::NoncoherentCache::handleAtomicReqMiss(), gem5::Cache::handleAtomicReqMiss(), and recvTimingResp().

◆ handleTimingReqHit()

void gem5::BaseCache::handleTimingReqHit ( PacketPtr  pkt,
CacheBlk blk,
Tick  request_time 
)
protectedvirtual

◆ handleTimingReqMiss() [1/2]

virtual void gem5::BaseCache::handleTimingReqMiss ( PacketPtr  pkt,
CacheBlk blk,
Tick  forward_time,
Tick  request_time 
)
protectedpure virtual

◆ handleTimingReqMiss() [2/2]

void gem5::BaseCache::handleTimingReqMiss ( PacketPtr  pkt,
MSHR mshr,
CacheBlk blk,
Tick  forward_time,
Tick  request_time 
)
protected

◆ handleUncacheableWriteResp()

void gem5::BaseCache::handleUncacheableWriteResp ( PacketPtr  pkt)
protected

Handling the special case of uncacheable write responses to make recvTimingResp less cluttered.

Definition at line 408 of file base.cc.

References gem5::Clocked::clockEdge(), cpuSidePort, gem5::Packet::headerDelay, gem5::Packet::payloadDelay, responseLatency, and gem5::QueuedResponsePort::schedTimingResp().

Referenced by recvTimingResp().

◆ hasBeenPrefetched()

bool gem5::BaseCache::hasBeenPrefetched ( Addr  addr,
bool  is_secure 
) const
inline

◆ inCache()

bool gem5::BaseCache::inCache ( Addr  addr,
bool  is_secure 
) const
inline

Definition at line 1270 of file base.hh.

References gem5::X86ISA::addr, gem5::BaseTags::findBlock(), and tags.

Referenced by gem5::prefetch::Base::inCache().

◆ incHitCount()

void gem5::BaseCache::incHitCount ( PacketPtr  pkt)
inline

◆ incMissCount()

void gem5::BaseCache::incMissCount ( PacketPtr  pkt)
inline

◆ init()

void gem5::BaseCache::init ( )
overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from gem5::SimObject.

Definition at line 192 of file base.cc.

References cpuSidePort, fatal, forwardSnoops, gem5::Port::isConnected(), gem5::ResponsePort::isSnooping(), memSidePort, gem5::Named::name(), and gem5::ResponsePort::sendRangeChange().

◆ inMissQueue()

bool gem5::BaseCache::inMissQueue ( Addr  addr,
bool  is_secure 
) const
inline

◆ inRange()

bool gem5::BaseCache::inRange ( Addr  addr) const
protected

Determine if an address is in the ranges covered by this cache.

This is useful to filter snoops.

Parameters
addrAddress to check against
Returns
If the address in question is in range

Definition at line 213 of file base.cc.

References gem5::X86ISA::addr, addrRanges, and gem5::MipsISA::r.

Referenced by gem5::Cache::recvAtomicSnoop(), and gem5::Cache::recvTimingSnoopReq().

◆ invalidateBlock()

void gem5::BaseCache::invalidateBlock ( CacheBlk blk)
protected

◆ invalidateVisitor()

void gem5::BaseCache::invalidateVisitor ( CacheBlk blk)

Cache block visitor that invalidates all blocks in the cache.

@warn Dirty cache lines will not be written back to memory.

Definition at line 1760 of file base.cc.

References gem5::CacheBlk::DirtyBit, invalidateBlock(), gem5::CacheBlk::isSet(), gem5::TaggedEntry::isValid(), and warn_once.

Referenced by memInvalidate().

◆ isBlocked()

bool gem5::BaseCache::isBlocked ( ) const
inline

Returns true if the cache is blocked for accesses.

Definition at line 1217 of file base.hh.

References blocked.

Referenced by getNextQueueEntry(), nextQueueReadyTime(), and recvTimingResp().

◆ isDirty()

bool gem5::BaseCache::isDirty ( ) const
protected

Determine if there are any dirty blocks in the cache.

Returns
true if at least one block is dirty, false otherwise.

Definition at line 1724 of file base.cc.

References gem5::BaseTags::anyBlk(), gem5::CacheBlk::DirtyBit, gem5::CacheBlk::isSet(), and tags.

Referenced by serialize().

◆ maintainClusivity()

void gem5::BaseCache::maintainClusivity ( bool  from_cache,
CacheBlk blk 
)
protected

Maintain the clusivity of this cache by potentially invalidating a block.

This method works in conjunction with satisfyRequest, but is separate to allow us to handle all MSHR targets before potentially dropping a block.

Parameters
from_cacheWhether we have dealt with a packet from a cache
blkThe block that should potentially be dropped

Definition at line 1422 of file base.cc.

References clusivity, gem5::CacheBlk::DirtyBit, invalidateBlock(), gem5::CacheBlk::isSet(), and gem5::TaggedEntry::isValid().

Referenced by access(), gem5::NoncoherentCache::handleAtomicReqMiss(), gem5::Cache::handleAtomicReqMiss(), and gem5::Cache::serviceMSHRTargets().

◆ markInService() [1/2]

void gem5::BaseCache::markInService ( MSHR mshr,
bool  pending_modified_resp 
)
inlineprotected

Mark a request as in service (sent downstream in the memory system), effectively making this MSHR the ordering point.

Definition at line 408 of file base.hh.

References Blocked_NoMSHRs, clearBlocked(), gem5::Queue< Entry >::isFull(), gem5::MSHRQueue::markInService(), and mshrQueue.

Referenced by access(), gem5::Cache::recvTimingSnoopReq(), gem5::Cache::sendMSHRQueuePacket(), sendMSHRQueuePacket(), and sendWriteQueuePacket().

◆ markInService() [2/2]

void gem5::BaseCache::markInService ( WriteQueueEntry entry)
inlineprotected

◆ memInvalidate()

void gem5::BaseCache::memInvalidate ( )
overrideprotectedvirtual

Invalidates all blocks in the cache.

@warn Dirty cache lines will not be written back to memory. Make sure to call functionalWriteback() first if you want the to write them to memory.

Reimplemented from gem5::SimObject.

Definition at line 1718 of file base.cc.

References gem5::BaseTags::forEachBlk(), invalidateVisitor(), and tags.

◆ memWriteback()

void gem5::BaseCache::memWriteback ( )
overrideprotectedvirtual

Write back dirty blocks in the cache using functional accesses.

Reimplemented from gem5::SimObject.

Definition at line 1712 of file base.cc.

References gem5::BaseTags::forEachBlk(), tags, and writebackVisitor().

◆ nextQueueReadyTime()

Tick gem5::BaseCache::nextQueueReadyTime ( ) const
protected

Find next request ready time from among possible sources.

Definition at line 1773 of file base.cc.

References gem5::MSHRQueue::canPrefetch(), isBlocked(), mshrQueue, gem5::prefetch::Base::nextPrefetchReadyTime(), gem5::Queue< Entry >::nextReadyTime(), prefetcher, and writeBuffer.

◆ recvAtomic()

Tick gem5::BaseCache::recvAtomic ( PacketPtr  pkt)
protectedvirtual

◆ recvAtomicSnoop()

virtual Tick gem5::BaseCache::recvAtomicSnoop ( PacketPtr  pkt)
protectedpure virtual

Snoop for the provided request in the cache and return the estimated time taken.

Parameters
pktThe memory request to snoop
Returns
The number of ticks required for the snoop.

Implemented in gem5::Cache, and gem5::NoncoherentCache.

◆ recvTimingReq()

void gem5::BaseCache::recvTimingReq ( PacketPtr  pkt)
protectedvirtual

◆ recvTimingResp()

void gem5::BaseCache::recvTimingResp ( PacketPtr  pkt)
protectedvirtual

Handles a response (cache line fill/write ack) from the bus.

Parameters
pktThe response packet

Reimplemented in gem5::NoncoherentCache.

Definition at line 420 of file base.cc.

References gem5::WriteAllocator::allocate(), gem5::MSHR::allocOnFill(), Blocked_NoMSHRs, Blocked_NoTargets, gem5::MSHRQueue::canPrefetch(), clearBlocked(), gem5::CacheBlk::clearCoherenceBits(), gem5::Clocked::clockEdge(), gem5::Packet::cmd, gem5::BaseCache::CacheStats::cmdStats(), gem5::curTick(), gem5::MSHRQueue::deallocate(), doWritebacks(), DPRINTF, evictBlock(), gem5::BaseTags::findBlock(), forwardLatency, gem5::Packet::getAddr(), gem5::MSHR::getTarget(), handleFill(), handleUncacheableWriteResp(), gem5::MemCmd::HardPFResp, gem5::Packet::headerDelay, isBlocked(), gem5::Packet::isClean(), gem5::Packet::isError(), gem5::MSHR::isForward, gem5::Queue< Entry >::isFull(), gem5::Packet::isInvalidate(), gem5::Packet::isRead(), gem5::Packet::isResponse(), gem5::Packet::isSecure(), gem5::CacheBlk::isSet(), gem5::TaggedEntry::isValid(), gem5::Packet::isWrite(), gem5::MSHRQueue::markPending(), gem5::System::maxRequestors(), gem5::MaxTick, gem5::BaseCache::CacheCmdStats::mshrMissLatency, mshrQueue, gem5::BaseCache::CacheCmdStats::mshrUncacheableLatency, gem5::Named::name(), gem5::prefetch::Base::nextPrefetchReadyTime(), noTargetMSHR, panic_if, gem5::Packet::payloadDelay, gem5::QueueEntry::Target::pkt, gem5::Packet::popSenderState(), ppFill, prefetcher, gem5::Packet::print(), gem5::MSHR::promoteDeferredTargets(), gem5::MSHR::promoteReadable(), gem5::MSHR::promoteWritable(), gem5::CacheBlk::ReadableBit, gem5::QueueEntry::Target::recvTime, gem5::Packet::req, schedMemSideSendEvent(), serviceMSHRTargets(), gem5::CacheBlk::setCoherenceBits(), stats, system, tags, tempBlock, gem5::MemCmd::UpgradeResp, gem5::MSHR::wasWholeLineWrite, gem5::CacheBlk::WritableBit, and writeAllocator.

Referenced by gem5::NoncoherentCache::recvTimingResp(), and gem5::Cache::recvTimingSnoopResp().

◆ recvTimingSnoopReq()

virtual void gem5::BaseCache::recvTimingSnoopReq ( PacketPtr  pkt)
protectedpure virtual

Snoops bus transactions to maintain coherence.

Parameters
pktThe current bus transaction.

Implemented in gem5::Cache, and gem5::NoncoherentCache.

◆ recvTimingSnoopResp()

virtual void gem5::BaseCache::recvTimingSnoopResp ( PacketPtr  pkt)
protectedpure virtual

Handle a snoop response.

Parameters
pktSnoop response packet

Implemented in gem5::Cache, and gem5::NoncoherentCache.

◆ regenerateBlkAddr()

Addr gem5::BaseCache::regenerateBlkAddr ( CacheBlk blk)
protected

Regenerate block address using tags.

Block address regeneration depends on whether we're using a temporary block or not.

Parameters
blkThe block to regenerate address.
Returns
The block's address.

Definition at line 182 of file base.cc.

References gem5::TempCacheBlk::getAddr(), gem5::BaseTags::regenerateBlkAddr(), tags, and tempBlock.

Referenced by gem5::Cache::cleanEvictBlk(), cmpAndSwap(), handleEvictions(), handleFill(), satisfyRequest(), updateBlockData(), updateCompressionData(), writebackBlk(), writebackVisitor(), and writecleanBlk().

◆ regProbePoints()

void gem5::BaseCache::regProbePoints ( )
overridevirtual

Registers probes.

Reimplemented from gem5::SimObject.

Definition at line 2405 of file base.cc.

References gem5::SimObject::getProbeManager(), ppDataUpdate, ppFill, ppHit, and ppMiss.

◆ satisfyRequest()

void gem5::BaseCache::satisfyRequest ( PacketPtr  pkt,
CacheBlk blk,
bool  deferred_response = false,
bool  pending_downgrade = false 
)
protectedvirtual

Perform any necessary updates to the block and perform any data exchange between the packet and the block.

The flags of the packet are also set accordingly.

Parameters
pktRequest packet from upstream that hit a block
blkCache block that the packet hit
deferred_responseWhether this request originally missed
pending_downgradeWhether the writable flag is to be removed

Reimplemented in gem5::Cache, and gem5::NoncoherentCache.

Definition at line 1012 of file base.cc.

References blkSize, gem5::CacheBlk::checkWrite(), gem5::CacheBlk::clearCoherenceBits(), gem5::Packet::cmd, cmpAndSwap(), gem5::CacheBlk::data, gem5::CacheBlk::DirtyBit, DPRINTF, gem5::BaseTags::extractBlkOffset(), gem5::Packet::getAddr(), gem5::Packet::getAtomicOp(), gem5::Packet::getOffset(), gem5::Packet::getSize(), gem5::Packet::hasRespData(), gem5::Packet::hasSharers(), invalidateBlock(), gem5::Packet::isAtomicOp(), gem5::Packet::isClean(), gem5::Packet::isInvalidate(), gem5::Packet::isLLSC(), gem5::Packet::isRead(), gem5::Packet::isRequest(), gem5::TaggedEntry::isSecure(), gem5::CacheBlk::isSet(), gem5::Packet::isUpgrade(), gem5::TaggedEntry::isValid(), gem5::Packet::isWrite(), gem5::BaseCache::DataUpdate::newData, gem5::ArmISA::offset, gem5::BaseCache::DataUpdate::oldData, ppDataUpdate, gem5::Packet::print(), regenerateBlkAddr(), gem5::Packet::setCacheResponding(), gem5::CacheBlk::setCoherenceBits(), gem5::Packet::setData(), gem5::Packet::setDataFromBlock(), gem5::MemCmd::SwapReq, tags, gem5::CacheBlk::trackLoadLocked(), updateBlockData(), and gem5::CacheBlk::WritableBit.

Referenced by access(), gem5::NoncoherentCache::satisfyRequest(), and gem5::Cache::satisfyRequest().

◆ schedMemSideSendEvent()

void gem5::BaseCache::schedMemSideSendEvent ( Tick  time)
inline

Schedule a send event for the memory-side port.

If already scheduled, this may reschedule the event at an earlier time. When the specified time is reached, the port is free to send either a response, a request, or a prefetch request.

Parameters
timeThe time when to attempt sending a packet.

Definition at line 1265 of file base.hh.

References memSidePort, and gem5::BaseCache::CacheRequestPort::schedSendEvent().

Referenced by allocateMissBuffer(), allocateWriteBuffer(), recvTimingReq(), and recvTimingResp().

◆ sendMSHRQueuePacket()

bool gem5::BaseCache::sendMSHRQueuePacket ( MSHR mshr)
virtual

◆ sendWriteQueuePacket()

bool gem5::BaseCache::sendWriteQueuePacket ( WriteQueueEntry wq_entry)

Similar to sendMSHR, but for a write-queue entry instead.

Create the packet, and send it, and if successful also mark the entry in service.

Parameters
wq_entryThe write-queue entry to turn into a packet and send
Returns
True if the port is waiting for a retry

Definition at line 1893 of file base.cc.

References DPRINTF, gem5::WriteQueueEntry::getTarget(), markInService(), memSidePort, gem5::QueueEntry::Target::pkt, gem5::Packet::print(), and gem5::RequestPort::sendTimingReq().

Referenced by gem5::WriteQueueEntry::sendPacket().

◆ serialize()

void gem5::BaseCache::serialize ( CheckpointOut cp) const
overridevirtual

Serialize the state of the caches.

We currently don't support checkpointing cache state, so this panics.

Implements gem5::Serializable.

Definition at line 1917 of file base.cc.

References isDirty(), SERIALIZE_SCALAR, and warn.

◆ serviceMSHRTargets()

virtual void gem5::BaseCache::serviceMSHRTargets ( MSHR mshr,
const PacketPtr  pkt,
CacheBlk blk 
)
protectedpure virtual

Service non-deferred MSHR targets using the received response.

Iterates through the list of targets that can be serviced with the current response.

Parameters
mshrThe MSHR that corresponds to the reponse
pktThe response packet
blkThe reference block

Implemented in gem5::Cache, and gem5::NoncoherentCache.

Referenced by recvTimingResp().

◆ setBlocked()

void gem5::BaseCache::setBlocked ( BlockedCause  cause)
inline

Marks the access path of the cache as blocked for the given cause.

This also sets the blocked flag in the response interface.

Parameters
causeThe reason for the cache blocking.

Definition at line 1227 of file base.hh.

References blocked, gem5::BaseCache::CacheStats::blockedCauses, blockedCycle, cpuSidePort, gem5::Clocked::curCycle(), DPRINTF, gem5::BaseCache::CacheResponsePort::setBlocked(), and stats.

Referenced by allocateMissBuffer(), allocateWriteBuffer(), and handleTimingReqMiss().

◆ unserialize()

void gem5::BaseCache::unserialize ( CheckpointIn cp)
overridevirtual

Unserialize an object.

Read an object's state from the current checkpoint section.

Parameters
cpCheckpoint state

Implements gem5::Serializable.

Definition at line 1937 of file base.cc.

References fatal, and UNSERIALIZE_SCALAR.

◆ updateBlockData()

void gem5::BaseCache::updateBlockData ( CacheBlk blk,
const PacketPtr  cpkt,
bool  has_old_data 
)
protected

Update the data contents of a block.

When no packet is provided no data will be written to the block, which means that this was likely triggered by an invalidation.

Parameters
blkThe block being updated.
cpktThe packet containing the new data.
has_old_dataWhether this block had data previously.

Definition at line 695 of file base.cc.

References blkSize, gem5::CacheBlk::data, gem5::TaggedEntry::isSecure(), gem5::BaseCache::DataUpdate::newData, gem5::BaseCache::DataUpdate::oldData, ppDataUpdate, regenerateBlkAddr(), and gem5::Packet::writeDataToBlock().

Referenced by access(), handleFill(), invalidateBlock(), and satisfyRequest().

◆ updateCompressionData()

bool gem5::BaseCache::updateCompressionData ( CacheBlk *&  blk,
const uint64_t *  data,
PacketList writebacks 
)
protected

When a block is overwriten, its compression information must be updated, and it may need to be recompressed.

If the compression size changes, the block may either become smaller, in which case there is no side effect, or bigger (data expansion; fat write), in which case the block might not fit in its current location anymore. If that happens, there are usually two options to be taken:

  • The co-allocated blocks must be evicted to make room for this block. Simpler, but ignores replacement data.
  • The block itself is moved elsewhere (used in policies where the CF determines the location of the block).

This implementation uses the first approach.

Notice that this is only called for writebacks, which means that L1 caches (which see regular Writes), do not support compression.

See also
CompressedTags
Parameters
blkThe block to be overwriten.
dataA pointer to the data to be compressed (blk's new data).
writebacksList for any writebacks that need to be performed.
Returns
Whether operation is successful or not.

Definition at line 902 of file base.cc.

References gem5::SectorBlk::blks, gem5::CompressionBlk::checkExpansionContraction(), gem5::compression::Base::compress(), compressor, data, gem5::CompressionBlk::DATA_CONTRACTION, gem5::CompressionBlk::DATA_EXPANSION, gem5::BaseCache::CacheStats::dataContractions, gem5::BaseCache::CacheStats::dataExpansions, DPRINTF, gem5::BaseTags::findVictim(), gem5::SectorSubBlk::getSectorBlock(), gem5::CompressionBlk::getSizeBits(), handleEvictions(), gem5::TaggedEntry::isSecure(), gem5::BaseTags::moveBlock(), moveContractions, gem5::CacheBlk::print(), regenerateBlkAddr(), replaceExpansions, gem5::CompressionBlk::setDecompressionLatency(), gem5::CompressionBlk::setSizeBits(), stats, tags, and tempBlock.

Referenced by access().

◆ writebackBlk()

PacketPtr gem5::BaseCache::writebackBlk ( CacheBlk blk)
protected

◆ writebackTempBlockAtomic()

void gem5::BaseCache::writebackTempBlockAtomic ( )
inlineprotected

Send the outstanding tempBlock writeback.

To be called after recvAtomic finishes in cases where the block we filled is in fact the tempBlock, and now needs to be written back.

Definition at line 691 of file base.hh.

References doWritebacksAtomic(), and tempBlockWriteback.

Referenced by BaseCache(), and recvAtomic().

◆ writebackVisitor()

void gem5::BaseCache::writebackVisitor ( CacheBlk blk)

◆ writecleanBlk()

PacketPtr gem5::BaseCache::writecleanBlk ( CacheBlk blk,
Request::Flags  dest,
PacketId  id 
)
protected

Create a writeclean request for the given block.

Creates a request that writes the block to the cache below without evicting the block from the current cache.

Parameters
blkThe block to write clean.
destThe destination of the write clean operation.
idUse the given packet id for the write clean operation.
Returns
The generated write clean packet.

Definition at line 1666 of file base.cc.

References gem5::Packet::allocate(), blkSize, gem5::CacheBlk::clearCoherenceBits(), compressor, gem5::CacheBlk::data, gem5::CacheBlk::DirtyBit, DPRINTF, gem5::compression::Base::getDecompressionLatency(), gem5::CacheBlk::getTaskId(), gem5::TaggedEntry::isSecure(), gem5::CacheBlk::isSet(), gem5::Packet::payloadDelay, gem5::Packet::print(), regenerateBlkAddr(), gem5::Request::SECURE, gem5::Packet::setDataFromBlock(), gem5::Packet::setHasSharers(), gem5::Packet::setWriteThrough(), gem5::Request::wbRequestorId, gem5::CacheBlk::WritableBit, and gem5::MemCmd::WriteClean.

Referenced by gem5::Cache::handleSnoop(), recvAtomic(), and sendMSHRQueuePacket().

Member Data Documentation

◆ addrRanges

const AddrRangeList gem5::BaseCache::addrRanges
protected

The address range to which the cache responds on the CPU side.

Normally this is all possible memory addresses.

Definition at line 982 of file base.hh.

Referenced by getAddrRanges(), and inRange().

◆ blkSize

const unsigned gem5::BaseCache::blkSize
protected

◆ blocked

uint8_t gem5::BaseCache::blocked
protected

Bit vector of the blocking reasons for the access path.

See also
BlockedCause

Definition at line 965 of file base.hh.

Referenced by gem5::BaseCache::CacheResponsePort::clearBlocked(), clearBlocked(), isBlocked(), setBlocked(), and gem5::BaseCache::CpuSidePort::tryTiming().

◆ blockedCycle

Cycles gem5::BaseCache::blockedCycle
protected

Stores time the cache blocked for statistics.

Definition at line 971 of file base.hh.

Referenced by clearBlocked(), and setBlocked().

◆ clusivity

const enums::Clusivity gem5::BaseCache::clusivity
protected

Clusivity with respect to the upstream cache, determining if we fill into both this cache and the cache above on a miss.

Note that we currently do not support strict clusivity policies.

Definition at line 935 of file base.hh.

Referenced by allocOnFill(), gem5::Cache::createMissPacket(), and maintainClusivity().

◆ compressor

compression::Base* gem5::BaseCache::compressor
protected

Compression method being used.

Definition at line 353 of file base.hh.

Referenced by access(), allocateBlock(), allocateWriteBuffer(), gem5::Cache::handleSnoop(), updateCompressionData(), writebackBlk(), and writecleanBlk().

◆ cpuSidePort

CpuSidePort gem5::BaseCache::cpuSidePort
protected

◆ dataLatency

const Cycles gem5::BaseCache::dataLatency
protected

The latency of data access of a cache.

It occurs when there is an access to the cache.

Definition at line 900 of file base.hh.

Referenced by calculateAccessLatency().

◆ fillLatency

const Cycles gem5::BaseCache::fillLatency
protected

The latency to fill a cache block.

Definition at line 910 of file base.hh.

Referenced by access(), and handleFill().

◆ forwardLatency

const Cycles gem5::BaseCache::forwardLatency
protected

This is the forward latency of the cache.

It occurs when there is a cache miss and a request is forwarded downstream, in particular an outbound miss.

Definition at line 907 of file base.hh.

Referenced by gem5::Cache::doTimingSupplyResponse(), gem5::Cache::handleSnoop(), recvTimingReq(), recvTimingResp(), and gem5::Cache::recvTimingSnoopResp().

◆ forwardSnoops

bool gem5::BaseCache::forwardSnoops
protected

Do we forward snoops from mem side port through to cpu side port?

Definition at line 928 of file base.hh.

Referenced by gem5::Cache::handleSnoop(), init(), gem5::Cache::isCachedAbove(), and gem5::Cache::sendMSHRQueuePacket().

◆ isReadOnly

const bool gem5::BaseCache::isReadOnly
protected

Is this cache read only, for example the instruction cache, or table-walker cache.

A cache that is read only should never see any writes, and should never get any dirty data (and hence never have to do any writebacks).

Definition at line 943 of file base.hh.

Referenced by gem5::Cache::access(), access(), gem5::Cache::createMissPacket(), handleFill(), gem5::Cache::handleSnoop(), gem5::Cache::serviceMSHRTargets(), and writebackBlk().

◆ lookupLatency

const Cycles gem5::BaseCache::lookupLatency
protected

The latency of tag lookup of a cache.

It occurs when there is an access to the cache.

Definition at line 894 of file base.hh.

Referenced by gem5::Cache::access(), recvAtomic(), gem5::Cache::recvAtomicSnoop(), and gem5::Cache::recvTimingSnoopReq().

◆ memSidePort

MemSidePort gem5::BaseCache::memSidePort
protected

◆ missCount

Counter gem5::BaseCache::missCount
protected

The number of misses to trigger an exit event.

Definition at line 977 of file base.hh.

Referenced by incMissCount().

◆ moveContractions

const bool gem5::BaseCache::moveContractions
protected

Similar to data expansions, after a block improves its compression, it may need to be moved elsewhere compatible with the new compression factor, or, if not required by the compaction method, it may be moved to co-allocate with an existing block and thus free an entry.

Definition at line 959 of file base.hh.

Referenced by updateCompressionData().

◆ mshrQueue

MSHRQueue gem5::BaseCache::mshrQueue
protected

◆ noTargetMSHR

MSHR* gem5::BaseCache::noTargetMSHR
protected

Pointer to the MSHR that has no targets.

Definition at line 974 of file base.hh.

Referenced by handleTimingReqMiss(), and recvTimingResp().

◆ numTarget

const int gem5::BaseCache::numTarget
protected

The number of targets for each MSHR.

Definition at line 925 of file base.hh.

Referenced by handleTimingReqMiss(), and gem5::Cache::recvTimingSnoopReq().

◆ order

uint64_t gem5::BaseCache::order
protected

Increasing order number assigned to each incoming request.

Definition at line 968 of file base.hh.

Referenced by allocateMissBuffer(), allocateWriteBuffer(), handleTimingReqMiss(), and gem5::Cache::recvTimingSnoopReq().

◆ pendingDelete

std::unique_ptr<Packet> gem5::BaseCache::pendingDelete
protected

Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call.

Definition at line 402 of file base.hh.

Referenced by handleTimingReqHit(), handleTimingReqMiss(), and gem5::Cache::recvTimingReq().

◆ ppDataUpdate

ProbePointArg<DataUpdate>* gem5::BaseCache::ppDataUpdate
protected

To probe when the contents of a block are updated.

Content updates include data fills, overwrites, and invalidations, which means that this probe partially overlaps with other probes.

Definition at line 372 of file base.hh.

Referenced by cmpAndSwap(), regProbePoints(), satisfyRequest(), and updateBlockData().

◆ ppFill

ProbePointArg<PacketPtr>* gem5::BaseCache::ppFill
protected

To probe when a cache fill occurs.

Definition at line 365 of file base.hh.

Referenced by recvTimingResp(), and regProbePoints().

◆ ppHit

ProbePointArg<PacketPtr>* gem5::BaseCache::ppHit
protected

To probe when a cache hit occurs.

Definition at line 359 of file base.hh.

Referenced by recvTimingReq(), and regProbePoints().

◆ ppMiss

ProbePointArg<PacketPtr>* gem5::BaseCache::ppMiss
protected

To probe when a cache miss occurs.

Definition at line 362 of file base.hh.

Referenced by recvTimingReq(), and regProbePoints().

◆ prefetcher

prefetch::Base* gem5::BaseCache::prefetcher
protected

◆ replaceExpansions

const bool gem5::BaseCache::replaceExpansions
protected

when a data expansion of a compressed block happens it will not be able to co-allocate where it is at anymore.

If true, the replacement policy is called to chose a new location for the block. Otherwise, all co-allocated blocks are evicted.

Definition at line 951 of file base.hh.

Referenced by updateCompressionData().

◆ responseLatency

const Cycles gem5::BaseCache::responseLatency
protected

The latency of sending reponse to its upper level cache/core on a linefill.

The responseLatency parameter captures this latency.

Definition at line 917 of file base.hh.

Referenced by handleUncacheableWriteResp(), gem5::NoncoherentCache::serviceMSHRTargets(), and gem5::Cache::serviceMSHRTargets().

◆ sequentialAccess

const bool gem5::BaseCache::sequentialAccess
protected

Whether tags and data are accessed sequentially.

Definition at line 922 of file base.hh.

Referenced by calculateAccessLatency().

◆ stats

gem5::BaseCache::CacheStats gem5::BaseCache::stats

◆ system

System* gem5::BaseCache::system

◆ tags

BaseTags* gem5::BaseCache::tags
protected

◆ tempBlock

TempCacheBlk* gem5::BaseCache::tempBlock
protected

Temporary cache block for occasional transitory use.

We use the tempBlock to fill when allocation fails (e.g., when there is an outstanding request that accesses the victim block) or when we want to avoid allocation (e.g., exclusive caches)

Definition at line 396 of file base.hh.

Referenced by handleFill(), invalidateBlock(), recvAtomic(), recvTimingResp(), regenerateBlkAddr(), updateCompressionData(), and ~BaseCache().

◆ tempBlockWriteback

PacketPtr gem5::BaseCache::tempBlockWriteback
protected

Writebacks from the tempBlock, resulting on the response path in atomic mode, must happen after the call to recvAtomic has finished (for the right ordering of the packets).

We therefore need to hold on to the packets, and have a method and an event to send them.

Definition at line 684 of file base.hh.

Referenced by recvAtomic(), and writebackTempBlockAtomic().

◆ writeAllocator

WriteAllocator* const gem5::BaseCache::writeAllocator
protected

The writeAllocator drive optimizations for streaming writes.

It first determines whether a WriteReq MSHR should be delayed, thus ensuring that we wait longer in cases when we are write coalescing and allowing all the bytes of the line to be written before the MSHR packet is sent downstream. This works in unison with the tracking in the MSHR to check if the entire line is written. The write mode also affects the behaviour on filling any whole-line writes. Normally the cache allocates the line when receiving the InvalidateResp, but after seeing enough consecutive lines we switch to using the tempBlock, and thus end up not allocating the line, and instead turning the whole-line write into a writeback straight away.

Definition at line 388 of file base.hh.

Referenced by coalesce(), gem5::Cache::handleAtomicReqMiss(), handleTimingReqMiss(), recvTimingResp(), and sendMSHRQueuePacket().

◆ writebackClean

const bool gem5::BaseCache::writebackClean
protected

Determine if clean lines should be written back or not.

In cases where a downstream cache is mostly inclusive we likely want it to act as a victim cache also for lines that have not been modified. Hence, we cannot simply drop the line (or send a clean evict), but rather need to send the actual data.

Definition at line 675 of file base.hh.

Referenced by gem5::Cache::cleanEvictBlk(), gem5::Cache::doWritebacks(), gem5::NoncoherentCache::evictBlock(), gem5::Cache::evictBlock(), and writebackBlk().

◆ writebackTempBlockAtomicEvent

EventFunctionWrapper gem5::BaseCache::writebackTempBlockAtomicEvent
protected

An event to writeback the tempBlock after recvAtomic finishes.

To avoid other calls to recvAtomic getting in between, we create this event with a higher priority.

Definition at line 703 of file base.hh.

Referenced by recvAtomic().

◆ writeBuffer

WriteQueue gem5::BaseCache::writeBuffer
protected

The documentation for this class was generated from the following files:

Generated on Tue Sep 21 2021 12:27:19 for gem5 by doxygen 1.8.17