gem5  v22.1.0.0
base.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __MEM_PROBES_BASE_HH__
39 #define __MEM_PROBES_BASE_HH__
40 
41 #include <memory>
42 #include <vector>
43 
44 #include "sim/probe/mem.hh"
45 #include "sim/sim_object.hh"
46 
47 namespace gem5
48 {
49 
50 struct BaseMemProbeParams;
51 
64 class BaseMemProbe : public SimObject
65 {
66  public:
67  BaseMemProbe(const BaseMemProbeParams &params);
68 
69  void regProbeListeners() override;
70 
71  protected:
75  virtual void handleRequest(const probing::PacketInfo &pkt_info) = 0;
76 
77  private:
78  class PacketListener : public ProbeListenerArgBase<probing::PacketInfo>
79  {
80  public:
82  ProbeManager *pm, const std::string &name)
84  parent(_parent) {}
85 
86  void notify(const probing::PacketInfo &pkt_info) override {
87  parent.handleRequest(pkt_info);
88  }
89 
90  protected:
92  };
93 
95 };
96 
97 } // namespace gem5
98 
99 #endif // __MEM_PROBES_BASE_HH__
void notify(const probing::PacketInfo &pkt_info) override
Definition: base.hh:86
PacketListener(BaseMemProbe &_parent, ProbeManager *pm, const std::string &name)
Definition: base.hh:81
Base class for memory system probes accepting Packet instances.
Definition: base.hh:65
virtual void handleRequest(const probing::PacketInfo &pkt_info)=0
Callback to analyse intercepted Packets.
std::vector< std::unique_ptr< PacketListener > > listeners
Definition: base.hh:94
void regProbeListeners() override
Register probe listeners for this object.
Definition: base.cc:51
BaseMemProbe(const BaseMemProbeParams &params)
Definition: base.cc:45
ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i....
Definition: probe.hh:212
const std::string name
Definition: probe.hh:138
ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners...
Definition: probe.hh:164
Abstract superclass for simulation objects.
Definition: sim_object.hh:148
STL vector class.
Definition: stl.hh:37
const Params & params() const
Definition: sim_object.hh:176
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
A struct to hold on to the essential fields from a packet, so that the packet and underlying request ...
Definition: mem.hh:59

Generated on Wed Dec 21 2022 10:22:28 for gem5 by doxygen 1.9.1