gem5  v21.1.0.2
interrupts.hh
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27 
28 #ifndef __ARCH_GENERIC_INTERRUPTS_HH__
29 #define __ARCH_GENERIC_INTERRUPTS_HH__
30 
31 #include "base/logging.hh"
32 #include "params/BaseInterrupts.hh"
33 #include "sim/sim_object.hh"
34 
35 namespace gem5
36 {
37 
38 class ThreadContext;
39 class BaseCPU;
40 
41 class BaseInterrupts : public SimObject
42 {
43  protected:
44  ThreadContext *tc = nullptr;
45 
46  public:
47  using Params = BaseInterruptsParams;
48 
50 
51  virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
52 
53  /*
54  * Functions for retrieving interrupts for the CPU to handle.
55  */
56 
57  /*
58  * Return whether there are any interrupts waiting to be recognized.
59  */
60  virtual bool checkInterrupts() const = 0;
61  /*
62  * Return an interrupt to process. This should return an interrupt exactly
63  * when checkInterrupts returns true.
64  */
65  virtual Fault getInterrupt() = 0;
66  /*
67  * Update interrupt related state after an interrupt has been processed.
68  */
69  virtual void updateIntrInfo() = 0;
70 
71  /*
72  * Old functions needed for compatability but which will be phased out
73  * eventually.
74  */
75  virtual void
76  post(int int_num, int index)
77  {
78  panic("Interrupts::post unimplemented!\n");
79  }
80 
81  virtual void
82  clear(int int_num, int index)
83  {
84  panic("Interrupts::clear unimplemented!\n");
85  }
86 
87  virtual void
89  {
90  panic("Interrupts::clearAll unimplemented!\n");
91  }
92 };
93 
94 } // namespace gem5
95 
96 #endif // __ARCH_GENERIC_INTERRUPTS_HH__
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition: interrupts.hh:44
gem5::BaseInterrupts::BaseInterrupts
BaseInterrupts(const Params &p)
Definition: interrupts.hh:49
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::BaseInterrupts::post
virtual void post(int int_num, int index)
Definition: interrupts.hh:76
gem5::BaseInterrupts::clear
virtual void clear(int int_num, int index)
Definition: interrupts.hh:82
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
sim_object.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::BaseInterrupts::updateIntrInfo
virtual void updateIntrInfo()=0
gem5::BaseInterrupts::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition: interrupts.hh:51
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseInterrupts::clearAll
virtual void clearAll()
Definition: interrupts.hh:88
gem5::BaseInterrupts::checkInterrupts
virtual bool checkInterrupts() const =0
logging.hh
gem5::BaseInterrupts::getInterrupt
virtual Fault getInterrupt()=0
gem5::BaseInterrupts::Params
BaseInterruptsParams Params
Definition: interrupts.hh:47
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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