gem5
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arch
generic
interrupts.hh
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/*
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* Copyright 2019 Google, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_GENERIC_INTERRUPTS_HH__
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#define __ARCH_GENERIC_INTERRUPTS_HH__
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#include "
base/logging.hh
"
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#include "params/BaseInterrupts.hh"
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#include "
sim/sim_object.hh
"
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namespace
gem5
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{
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class
ThreadContext;
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class
BaseCPU;
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class
BaseInterrupts
:
public
SimObject
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{
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protected
:
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ThreadContext
*
tc
=
nullptr
;
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public
:
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using
Params
= BaseInterruptsParams;
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BaseInterrupts
(
const
Params
&
p
) :
SimObject
(
p
) {}
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virtual
void
setThreadContext
(
ThreadContext
*_tc) {
tc
= _tc; }
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/*
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* Functions for retrieving interrupts for the CPU to handle.
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*/
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/*
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* Return whether there are any interrupts waiting to be recognized.
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*/
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virtual
bool
checkInterrupts
()
const
= 0;
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/*
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* Return an interrupt to process. This should return an interrupt exactly
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* when checkInterrupts returns true.
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*/
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virtual
Fault
getInterrupt
() = 0;
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/*
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* Update interrupt related state after an interrupt has been processed.
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*/
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virtual
void
updateIntrInfo
() = 0;
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/*
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* Old functions needed for compatability but which will be phased out
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* eventually.
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*/
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virtual
void
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post
(
int
int_num,
int
index
)
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{
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panic
(
"Interrupts::post unimplemented!\n"
);
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}
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virtual
void
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clear
(
int
int_num,
int
index
)
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{
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panic
(
"Interrupts::clear unimplemented!\n"
);
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}
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virtual
void
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clearAll
()
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{
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panic
(
"Interrupts::clearAll unimplemented!\n"
);
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}
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};
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}
// namespace gem5
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#endif
// __ARCH_GENERIC_INTERRUPTS_HH__
gem5::BaseInterrupts
Definition
interrupts.hh:42
gem5::BaseInterrupts::Params
BaseInterruptsParams Params
Definition
interrupts.hh:47
gem5::BaseInterrupts::updateIntrInfo
virtual void updateIntrInfo()=0
gem5::BaseInterrupts::clearAll
virtual void clearAll()
Definition
interrupts.hh:88
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition
interrupts.hh:44
gem5::BaseInterrupts::clear
virtual void clear(int int_num, int index)
Definition
interrupts.hh:82
gem5::BaseInterrupts::BaseInterrupts
BaseInterrupts(const Params &p)
Definition
interrupts.hh:49
gem5::BaseInterrupts::setThreadContext
virtual void setThreadContext(ThreadContext *_tc)
Definition
interrupts.hh:51
gem5::BaseInterrupts::post
virtual void post(int int_num, int index)
Definition
interrupts.hh:76
gem5::BaseInterrupts::checkInterrupts
virtual bool checkInterrupts() const =0
gem5::BaseInterrupts::getInterrupt
virtual Fault getInterrupt()=0
gem5::SimObject
Abstract superclass for simulation objects.
Definition
sim_object.hh:148
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition
logging.hh:188
logging.hh
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition
pra_constants.hh:47
gem5::MipsISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition
types.hh:249
sim_object.hh
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