misc_accessors.hh

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#ifndef __ARCH_ARM_REGS_MISC_ACCESSORS_HH__
#define __ARCH_ARM_REGS_MISC_ACCESSORS_HH__
 
#include "arch/arm/regs/misc_types.hh"
#include "cpu/thread_context.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
namespace misc_regs
{
 
struct FarAccessor
{
    using type = RegVal;
    static const MiscRegIndex el0 = NUM_MISCREGS;
    static const MiscRegIndex el1 = MISCREG_FAR_EL1;
    static const MiscRegIndex el2 = MISCREG_FAR_EL2;
    static const MiscRegIndex el3 = MISCREG_FAR_EL3;
};
 
struct MpamAccessor
{
    using type = MPAM;
    static const MiscRegIndex el0 = MISCREG_MPAM0_EL1;
    static const MiscRegIndex el1 = MISCREG_MPAM1_EL1;
    static const MiscRegIndex el2 = MISCREG_MPAM2_EL2;
    static const MiscRegIndex el3 = MISCREG_MPAM3_EL3;
};
 
template <typename RegAccessor>
MiscRegIndex
getRegVersion(ExceptionLevel el)
{
    switch (el) {
      case EL0:
        return RegAccessor::el0;
      case EL1:
        return RegAccessor::el1;
      case EL2:
        return RegAccessor::el2;
      case EL3:
        return RegAccessor::el3;
      default:
        panic("Invalid EL\n");
    }
}
 
template <typename RegAccessor>
typename RegAccessor::type
readRegister(ThreadContext *tc, ExceptionLevel el)
{
    return tc->readMiscReg(getRegVersion<RegAccessor>(el));
}
 
template <typename RegAccessor>
typename RegAccessor::type
readRegisterNoEffect(ThreadContext *tc, ExceptionLevel el)
{
    return tc->readMiscRegNoEffect(getRegVersion<RegAccessor>(el));
}
 
template <typename RegAccessor>
void
writeRegister(ThreadContext *tc, RegVal val, ExceptionLevel el)
{
    tc->setMiscReg(getRegVersion<RegAccessor>(el), val);
}
 
} // namespace misc_regs
} // namespace ArmISA
} // namespace gem5
 
#endif // __ARCH_ARM_REGS_MISC_ACCESSORS_HH__