gem5 v24.0.0.0
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lsq.hh File Reference
#include <cassert>
#include <cstdint>
#include <list>
#include <map>
#include <queue>
#include <vector>
#include "arch/generic/mmu.hh"
#include "arch/generic/tlb.hh"
#include "base/flags.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/utils.hh"
#include "enums/SMTQueuePolicy.hh"
#include "mem/port.hh"
#include "sim/sim_object.hh"

Go to the source code of this file.

Classes

class  gem5::o3::LSQ
 
class  gem5::o3::LSQ::DcachePort
 DcachePort class for the load/store queue. More...
 
class  gem5::o3::LSQ::LSQRequest
 Memory operation metadata. More...
 
class  gem5::o3::LSQ::SingleDataRequest
 
class  gem5::o3::LSQ::UnsquashableDirectRequest
 
class  gem5::o3::LSQ::SplitDataRequest
 

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::o3
 

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