gem5  v22.0.0.1
Public Member Functions | Protected Attributes | List of all members
gem5::o3::LSQ::SplitDataRequest Class Reference

#include <lsq.hh>

Inheritance diagram for gem5::o3::LSQ::SplitDataRequest:
gem5::o3::LSQ::LSQRequest gem5::BaseMMU::Translation gem5::Packet::SenderState

Public Member Functions

 SplitDataRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr)
virtual ~SplitDataRequest ()
virtual void markAsStaleTranslation ()
virtual void finish (const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
virtual bool recvTimingResp (PacketPtr pkt)
virtual void initiateTranslation ()
virtual void sendPacketToCache ()
virtual void buildPackets ()
virtual Cycles handleLocalAccess (gem5::ThreadContext *thread, PacketPtr pkt)
 Memory mapped IPR accesses. More...
virtual bool isCacheBlockHit (Addr blockAddr, Addr cacheBlockMask)
 Caches may probe into the load-store queue to enforce memory ordering guarantees. More...
virtual RequestPtr mainReq ()
virtual PacketPtr mainPacket ()
virtual std::string name () const
- Public Member Functions inherited from gem5::o3::LSQ::LSQRequest
void packetSent ()
 Update the status to reflect that a packet was sent. More...
void packetNotSent ()
 Update the status to reflect that a packet was not sent. More...
void sendFragmentToTranslation (int i)
bool isComplete ()
bool isInTranslation ()
bool isTranslationComplete ()
bool isTranslationBlocked ()
bool isSent ()
bool isPartialFault ()
bool isMemAccessRequired ()
void setStateToFault ()
void freeLSQEntry ()
 The LSQ entry is cleared. More...
void discard ()
 The request is discarded (e.g. More...
void packetReplied ()
void writebackScheduled ()
void writebackDone ()
void squashTranslation ()
void complete ()
void setContext (const ContextID &context_id)
 Convenience getters/setters. More...
const DynInstPtrinstruction ()
bool hasStaleTranslation () const
void setVirt (Addr vaddr, unsigned size, Request::Flags flags_, RequestorID requestor_id, Addr pc)
 Set up virtual request. More...
ContextID contextId () const
void taskId (const uint32_t &v)
uint32_t taskId () const
RequestPtr req (int idx=0)
const RequestPtr req (int idx=0) const
Addr getVaddr (int idx=0) const
PacketPtr packet (int idx=0)
bool isAnyOutstandingRequest ()
 Test if there is any in-flight translation or mem access request. More...
bool isReleased ()
 Test if the LSQRequest has been released, i.e. More...
bool isSplit () const
bool needWBToRegister () const
- Public Member Functions inherited from gem5::BaseMMU::Translation
virtual ~Translation ()
- Public Member Functions inherited from gem5::Packet::SenderState
 SenderState ()
virtual ~SenderState ()

Protected Attributes

uint32_t numFragments
uint32_t numReceivedPackets
RequestPtr _mainReq
PacketPtr _mainPacket
- Protected Attributes inherited from gem5::o3::LSQ::LSQRequest
FlagsType flags
State _state
uint32_t numTranslatedFragments
uint32_t numInTranslationFragments

Additional Inherited Members

- Public Attributes inherited from gem5::o3::LSQ::LSQRequest
const DynInstPtr _inst
uint32_t _taskId
PacketDataPtr _data
std::vector< PacketPtr_packets
std::vector< RequestPtr_reqs
std::vector< Fault_fault
uint64_t * _res
const Addr _addr
const uint32_t _size
const Request::Flags _flags
std::vector< bool > _byteEnable
uint32_t _numOutstandingPackets
AtomicOpFunctorPtr _amo_op
bool _hasStaleTranslation
- Public Attributes inherited from gem5::Packet::SenderState
- Protected Types inherited from gem5::o3::LSQ::LSQRequest
enum  Flag : FlagsStorage {
  IsLoad = 0x00000001, WriteBackToRegister = 0x00000002, Delayed = 0x00000004, IsSplit = 0x00000008,
  TranslationStarted = 0x00000010, TranslationFinished = 0x00000020, Sent = 0x00000040, Retry = 0x00000080,
  Complete = 0x00000100, TranslationSquashed = 0x00000200, Discarded = 0x00000400, LSQEntryFreed = 0x00000800,
  WritebackScheduled = 0x00001000, WritebackDone = 0x00002000, IsAtomic = 0x00004000
enum  State {
  State::NotIssued, State::Translation, State::Request, State::Fault,
typedef uint32_t FlagsStorage
typedef Flags< FlagsStorageFlagsType
- Protected Member Functions inherited from gem5::o3::LSQ::LSQRequest
void setState (const State &newState)
void markDelayed () override
 Signal that the translation has been delayed due to a hw page table walk. More...
bool isDelayed ()
LSQUnitlsqUnit ()
 LSQRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad)
 LSQRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr, bool stale_translation=false)
bool isLoad () const
bool isAtomic () const
void install ()
 Install the request in the LQ/SQ. More...
bool squashed () const override
 This function is used by the page table walker to determine if it should translate the a pending request or if the underlying request has been squashed. More...
void release (Flag reason)
 Release the LSQRequest. More...
void addReq (Addr addr, unsigned size, const std::vector< bool > &byte_enable)
 Helper function used to add a (sub)request, given its address addr, size size and byte-enable mask byteEnable. More...
virtual ~LSQRequest ()
 Destructor. More...

Detailed Description

Definition at line 614 of file lsq.hh.

Constructor & Destructor Documentation

◆ SplitDataRequest()

gem5::o3::LSQ::SplitDataRequest::SplitDataRequest ( LSQUnit port,
const DynInstPtr inst,
bool  isLoad,
const Addr addr,
const uint32_t &  size,
const Request::Flags flags_,
PacketDataPtr  data = nullptr,
uint64_t *  res = nullptr 

Definition at line 623 of file lsq.hh.

References gem5::o3::LSQ::LSQRequest::flags, and gem5::Flags< T >::set().

◆ ~SplitDataRequest()

virtual gem5::o3::LSQ::SplitDataRequest::~SplitDataRequest ( )

Definition at line 636 of file lsq.hh.

References _mainPacket, and _mainReq.

Member Function Documentation

◆ buildPackets()

void gem5::o3::LSQ::SplitDataRequest::buildPackets ( )

◆ finish()

void gem5::o3::LSQ::SplitDataRequest::finish ( const Fault fault,
const RequestPtr req,
gem5::ThreadContext tc,
BaseMMU::Mode  mode 

Implements gem5::BaseMMU::Translation.

Definition at line 903 of file

References flags, gem5::ArmISA::i, gem5::NoFault, and gem5::o3::LSQ::LSQRequest::req().

◆ handleLocalAccess()

Cycles gem5::o3::LSQ::SplitDataRequest::handleLocalAccess ( gem5::ThreadContext thread,
PacketPtr  pkt 

◆ initiateTranslation()

void gem5::o3::LSQ::SplitDataRequest::initiateTranslation ( )

Implements gem5::o3::LSQ::LSQRequest.

Definition at line 984 of file

References gem5::addrBlockAlign(), flags, gem5::ArmISA::i, and gem5::VegaISA::r.

◆ isCacheBlockHit()

bool gem5::o3::LSQ::SplitDataRequest::isCacheBlockHit ( Addr  blockAddr,
Addr  blockMask 

Caches may probe into the load-store queue to enforce memory ordering guarantees.

This method supports probes by providing a mechanism to compare snoop messages with requests tracked by the load-store queue.

Consistency models must enforce ordering constraints. TSO, for instance, must prevent memory reorderings except stores which are reordered after loads. The reordering restrictions negatively impact performance by cutting down on memory level parallelism. However, the core can regain performance by generating speculative loads. Speculative loads may issue without affecting correctness if precautions are taken to handle invalid memory orders. The load queue must squash under memory model violations. Memory model violations may occur when block ownership is granted to another core or the block cannot be accurately monitored by the load queue.

The load-store queue handles partial faults which complicates this method. Physical addresses must be compared between requests and snoops. Some requests will not have a valid physical address, since partial faults may have outstanding translations. Therefore, the existence of a valid request address must be checked before comparing block hits. We assume no pipeline squash is needed if a valid request address does not exist.

Implements gem5::o3::LSQ::LSQRequest.

Definition at line 1390 of file

References gem5::VegaISA::r.

◆ mainPacket()

PacketPtr gem5::o3::LSQ::SplitDataRequest::mainPacket ( )

Reimplemented from gem5::o3::LSQ::LSQRequest.

Definition at line 972 of file

◆ mainReq()

RequestPtr gem5::o3::LSQ::SplitDataRequest::mainReq ( )

Reimplemented from gem5::o3::LSQ::LSQRequest.

Definition at line 978 of file

◆ markAsStaleTranslation()

void gem5::o3::LSQ::SplitDataRequest::markAsStaleTranslation ( )

Implements gem5::o3::LSQ::LSQRequest.

Definition at line 1174 of file

References gem5::Complete, DPRINTF, and flags.

◆ name()

virtual std::string gem5::o3::LSQ::SplitDataRequest::name ( ) const

Reimplemented from gem5::o3::LSQ::LSQRequest.

Definition at line 660 of file lsq.hh.

◆ recvTimingResp()

bool gem5::o3::LSQ::SplitDataRequest::recvTimingResp ( PacketPtr  pkt)

◆ sendPacketToCache()

void gem5::o3::LSQ::SplitDataRequest::sendPacketToCache ( )

Implements gem5::o3::LSQ::LSQRequest.

Definition at line 1331 of file

Member Data Documentation

◆ _mainPacket

PacketPtr gem5::o3::LSQ::SplitDataRequest::_mainPacket

Definition at line 620 of file lsq.hh.

Referenced by ~SplitDataRequest().

◆ _mainReq

RequestPtr gem5::o3::LSQ::SplitDataRequest::_mainReq

Definition at line 619 of file lsq.hh.

Referenced by ~SplitDataRequest().

◆ numFragments

uint32_t gem5::o3::LSQ::SplitDataRequest::numFragments

Definition at line 617 of file lsq.hh.

◆ numReceivedPackets

uint32_t gem5::o3::LSQ::SplitDataRequest::numReceivedPackets

Definition at line 618 of file lsq.hh.

The documentation for this class was generated from the following files:

Generated on Sat Jun 18 2022 08:14:27 for gem5 by doxygen 1.8.17