#include <lsq.hh>

Inheritance diagram for gem5::o3::LSQ::SingleDataRequest:

Public Member Functions
	SingleDataRequest (LSQUnit port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)

virtual	~SingleDataRequest ()

virtual void	markAsStaleTranslation ()

virtual void	initiateTranslation ()

virtual void	finish (const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)

virtual bool	recvTimingResp (PacketPtr pkt)

virtual void	sendPacketToCache ()

virtual void	buildPackets ()

virtual Cycles	handleLocalAccess (gem5::ThreadContext *thread, PacketPtr pkt)
	Memory mapped IPR accesses.

virtual bool	isCacheBlockHit (Addr blockAddr, Addr cacheBlockMask)
	Test if the request accesses a particular cache line.

virtual std::string	name () const

Public Member Functions inherited from gem5::o3::LSQ::LSQRequest
void	packetSent ()
	Update the status to reflect that a packet was sent.

void	packetNotSent ()
	Update the status to reflect that a packet was not sent.

void	sendFragmentToTranslation (int i)

bool	isComplete ()

bool	isInTranslation ()

bool	isTranslationComplete ()

bool	isTranslationBlocked ()

bool	isSent ()

bool	isPartialFault ()

bool	isMemAccessRequired ()

void	setStateToFault ()

void	freeLSQEntry ()
	The LSQ entry is cleared.

void	discard ()
	The request is discarded (e.g.

void	packetReplied ()

void	writebackScheduled ()

void	writebackDone ()

void	squashTranslation ()

void	complete ()

void	setContext (const ContextID &context_id)
	Convenience getters/setters.

const DynInstPtr &	instruction ()

bool	hasStaleTranslation () const

void	setVirt (Addr vaddr, unsigned size, Request::Flags flags_, RequestorID requestor_id, Addr pc)
	Set up virtual request.

ContextID	contextId () const

void	taskId (const uint32_t &v)

uint32_t	taskId () const

RequestPtr	req (int idx=0)

const RequestPtr	req (int idx=0) const

Addr	getVaddr (int idx=0) const

PacketPtr	packet (int idx=0)

virtual PacketPtr	mainPacket ()

virtual RequestPtr	mainReq ()

bool	isAnyOutstandingRequest ()
	Test if there is any in-flight translation or mem access request.

bool	isReleased ()
	Test if the LSQRequest has been released, i.e.

bool	isSplit () const

bool	needWBToRegister () const

Public Member Functions inherited from gem5::BaseMMU::Translation
virtual	~Translation ()

Public Member Functions inherited from gem5::Packet::SenderState
	SenderState ()

virtual	~SenderState ()

Additional Inherited Members
Public Attributes inherited from gem5::o3::LSQ::LSQRequest
LSQUnit &	_port

const DynInstPtr	_inst

uint32_t	_taskId

PacketDataPtr	_data

std::vector< PacketPtr >	_packets

std::vector< RequestPtr >	_reqs

std::vector< Fault >	_fault

uint64_t *	_res

const Addr	_addr

const uint32_t	_size

const Request::Flags	_flags

std::vector< bool >	_byteEnable

uint32_t	_numOutstandingPackets

AtomicOpFunctorPtr	_amo_op

bool	_hasStaleTranslation

Public Attributes inherited from gem5::Packet::SenderState
SenderState *	predecessor

Protected Types inherited from gem5::o3::LSQ::LSQRequest
enum	Flag : FlagsStorage { IsLoad = 0x00000001 , WriteBackToRegister = 0x00000002 , Delayed = 0x00000004 , IsSplit = 0x00000008 , TranslationStarted = 0x00000010 , TranslationFinished = 0x00000020 , Sent = 0x00000040 , Retry = 0x00000080 , Complete = 0x00000100 , TranslationSquashed = 0x00000200 , Discarded = 0x00000400 , LSQEntryFreed = 0x00000800 , WritebackScheduled = 0x00001000 , WritebackDone = 0x00002000 , IsAtomic = 0x00004000 }

enum class	State { NotIssued , Translation , Request , Fault , PartialFault }

typedef uint32_t	FlagsStorage

typedef Flags< FlagsStorage >	FlagsType

Protected Member Functions inherited from gem5::o3::LSQ::LSQRequest
void	setState (const State &newState)

void	markDelayed () override
	Signal that the translation has been delayed due to a hw page table walk.

bool	isDelayed ()

LSQUnit *	lsqUnit ()

	LSQRequest (LSQUnit *port, const DynInstPtr &inst, bool isLoad)

	LSQRequest (LSQUnit port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t res=nullptr, AtomicOpFunctorPtr amo_op=nullptr, bool stale_translation=false)

bool	isLoad () const

bool	isAtomic () const

void	install ()
	Install the request in the LQ/SQ.

bool	squashed () const override
	This function is used by the page table walker to determine if it should translate the a pending request or if the underlying request has been squashed.

void	release (Flag reason)
	Release the LSQRequest.

void	addReq (Addr addr, unsigned size, const std::vector< bool > &byte_enable)
	Helper function used to add a (sub)request, given its address `addr`, size `size` and byte-enable mask `byteEnable`.

virtual	~LSQRequest ()
	Destructor.

Protected Attributes inherited from gem5::o3::LSQ::LSQRequest
FlagsType	flags

State	_state

uint32_t	numTranslatedFragments

uint32_t	numInTranslationFragments

Detailed Description

Definition at line 569 of file lsq.hh.

Constructor & Destructor Documentation

◆ SingleDataRequest()

gem5::o3::LSQ::SingleDataRequest::SingleDataRequest	(	LSQUnit *	port,
		const DynInstPtr &	inst,
		bool	isLoad,
		const Addr &	addr,
		const uint32_t &	size,
		const Request::Flags &	flags_,
		PacketDataPtr	data = nullptr,
		uint64_t *	res = nullptr,
		AtomicOpFunctorPtr	amo_op = nullptr )