gem5  v21.1.0.2
lsq.hh
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41 
42 #ifndef __CPU_O3_LSQ_HH__
43 #define __CPU_O3_LSQ_HH__
44 
45 #include <cassert>
46 #include <cstdint>
47 #include <list>
48 #include <map>
49 #include <queue>
50 #include <vector>
51 
52 #include "arch/generic/mmu.hh"
53 #include "arch/generic/tlb.hh"
54 #include "base/flags.hh"
55 #include "base/types.hh"
56 #include "cpu/inst_seq.hh"
57 #include "cpu/o3/dyn_inst_ptr.hh"
58 #include "cpu/utils.hh"
59 #include "enums/SMTQueuePolicy.hh"
60 #include "mem/port.hh"
61 #include "sim/sim_object.hh"
62 
63 namespace gem5
64 {
65 
66 struct O3CPUParams;
67 
68 namespace o3
69 {
70 
71 class CPU;
72 class IEW;
73 class LSQUnit;
74 
75 class LSQ
76 {
77  public:
78  class LSQRequest;
81  {
82  protected:
85 
87  LSQSenderState(LSQRequest* request, bool is_load);
88 
89  public:
93  PacketPtr mainPkt = nullptr;
97  uint8_t outstanding = 0;
99  bool isLoad = false;
101  bool needWB = false;
103  bool isSplit = false;
105  bool pktToSend = false;
110  bool deleted = false;
112 
114  bool isComplete() { return outstanding == 0; }
115  void deleteRequest() { deleted = true; }
116  bool alive() { return !deleted; }
117  LSQRequest* request() { return _request; }
118  virtual void complete() = 0;
120  };
121 
125  class DcachePort : public RequestPort
126  {
127  protected:
128 
132 
133  public:
135  DcachePort(LSQ *_lsq, CPU *_cpu);
136 
137  protected:
138 
142  virtual bool recvTimingResp(PacketPtr pkt);
143  virtual void recvTimingSnoopReq(PacketPtr pkt);
144 
145  virtual void
147  {
148  // @todo: Is there a need for potential invalidation here?
149  }
150 
152  virtual void recvReqRetry();
153 
160  virtual bool isSnooping() const { return true; }
161  };
162 
232  {
233  protected:
234  typedef uint32_t FlagsStorage;
236 
238  {
239  IsLoad = 0x00000001,
241  WbStore = 0x00000002,
242  Delayed = 0x00000004,
243  IsSplit = 0x00000008,
245  TranslationStarted = 0x00000010,
247  TranslationFinished = 0x00000020,
248  Sent = 0x00000040,
249  Retry = 0x00000080,
250  Complete = 0x00000100,
253  TranslationSquashed = 0x00000200,
255  Discarded = 0x00000400,
257  LSQEntryFreed = 0x00000800,
259  WritebackScheduled = 0x00001000,
260  WritebackDone = 0x00002000,
262  IsAtomic = 0x00004000
263  };
265 
266  enum class State
267  {
268  NotIssued,
269  Translation,
270  Request,
271  Fault,
272  PartialFault,
273  };
276  void setState(const State& newState) { _state = newState; }
277 
280 
282  uint32_t _entryIdx;
283 
284  void markDelayed() override { flags.set(Flag::Delayed); }
285  bool isDelayed() { return flags.isSet(Flag::Delayed); }
286 
287  public:
290  uint32_t _taskId;
295  uint64_t* _res;
296  const Addr _addr;
297  const uint32_t _size;
302  protected:
303  LSQUnit* lsqUnit() { return &_port; }
304  LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad);
305  LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
306  const Addr& addr, const uint32_t& size,
307  const Request::Flags& flags_, PacketDataPtr data=nullptr,
308  uint64_t* res=nullptr, AtomicOpFunctorPtr amo_op=nullptr);
309 
310  bool
311  isLoad() const
312  {
313  return flags.isSet(Flag::IsLoad);
314  }
315 
316  bool
317  isAtomic() const
318  {
319  return flags.isSet(Flag::IsAtomic);
320  }
321 
323  void install();
324 
325  bool squashed() const override;
326 
332  bool
334  {
335  return flags.isSet(Flag::LSQEntryFreed) ||
336  flags.isSet(Flag::Discarded);
337  }
338 
348  void
349  release(Flag reason)
350  {
351  assert(reason == Flag::LSQEntryFreed || reason == Flag::Discarded);
352  if (!isAnyOutstandingRequest()) {
353  delete this;
354  } else {
355  if (_senderState) {
357  }
358  flags.set(reason);
359  }
360  }
361 
368  void addRequest(Addr addr, unsigned size,
369  const std::vector<bool>& byte_enable);
370 
375  virtual ~LSQRequest();
376 
377  public:
381  void
382  setContext(const ContextID& context_id)
383  {
384  request()->setContext(context_id);
385  }
386 
387  const DynInstPtr& instruction() { return _inst; }
388 
392  void
393  setVirt(Addr vaddr, unsigned size, Request::Flags flags_,
394  RequestorID requestor_id, Addr pc)
395  {
396  request()->setVirt(vaddr, size, flags_, requestor_id, pc);
397  }
398 
399  void
400  taskId(const uint32_t& v)
401  {
402  _taskId = v;
403  for (auto& r: _requests)
404  r->taskId(v);
405  }
406 
407  uint32_t taskId() const { return _taskId; }
408  RequestPtr request(int idx = 0) { return _requests.at(idx); }
409 
410  const RequestPtr
411  request(int idx = 0) const
412  {
413  return _requests.at(idx);
414  }
415 
416  Addr getVaddr(int idx = 0) const { return request(idx)->getVaddr(); }
417  virtual void initiateTranslation() = 0;
418 
419  PacketPtr packet(int idx = 0) { return _packets.at(idx); }
420 
421  virtual PacketPtr
423  {
424  assert (_packets.size() == 1);
425  return packet();
426  }
427 
428  virtual RequestPtr
430  {
431  assert (_requests.size() == 1);
432  return request();
433  }
434 
435  void
437  {
438  _senderState = st;
439  for (auto& pkt: _packets) {
440  if (pkt)
441  pkt->senderState = st;
442  }
443  }
444 
445  const LSQSenderState*
446  senderState() const
447  {
448  return _senderState;
449  }
450 
455  void
457  {
458  assert(_senderState);
460  }
461 
465  bool
467  {
468  return numInTranslationFragments > 0 ||
470  (flags.isSet(Flag::WritebackScheduled) &&
471  !flags.isSet(Flag::WritebackDone));
472  }
473 
474  bool
475  isSplit() const
476  {
477  return flags.isSet(Flag::IsSplit);
478  }
480  virtual bool recvTimingResp(PacketPtr pkt) = 0;
481  virtual void sendPacketToCache() = 0;
482  virtual void buildPackets() = 0;
483 
487  virtual Cycles handleLocalAccess(
489 
493  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask) = 0;
494 
496  void
498  {
499  flags.set(Flag::Sent);
500  }
505  void
507  {
508  flags.set(Flag::Retry);
509  flags.clear(Flag::Sent);
510  }
511 
512  void sendFragmentToTranslation(int i);
513  bool
515  {
516  return flags.isSet(Flag::Complete);
517  }
518 
519  bool
521  {
522  return _state == State::Translation;
523  }
524 
525  bool
527  {
528  return flags.isSet(Flag::TranslationStarted) &&
529  !isInTranslation();
530  }
531 
532  bool
534  {
535  return _state == State::Translation &&
536  flags.isSet(Flag::TranslationStarted) &&
537  !flags.isSet(Flag::TranslationFinished);
538  }
539 
540  bool
542  {
543  return flags.isSet(Flag::Sent);
544  }
545 
546  bool
548  {
549  return _state == State::PartialFault;
550  }
551 
552  bool
554  {
555  return (_state == State::Request ||
556  (isPartialFault() && isLoad()));
557  }
558 
559  void
561  {
563  }
564 
568  void
570  {
571  release(Flag::LSQEntryFreed);
572  }
573 
577  void
579  {
580  release(Flag::Discarded);
581  }
582 
583  void
585  {
586  assert(_numOutstandingPackets > 0);
588  if (_numOutstandingPackets == 0 && isReleased())
589  delete this;
590  }
591 
592  void
594  {
595  assert(!flags.isSet(Flag::WritebackScheduled));
596  flags.set(Flag::WritebackScheduled);
597  }
598 
599  void
601  {
602  flags.set(Flag::WritebackDone);
603  /* If the lsq resources are already free */
604  if (isReleased()) {
605  delete this;
606  }
607  }
608 
609  void
611  {
612  assert(numInTranslationFragments == 0);
613  flags.set(Flag::TranslationSquashed);
614  /* If we are on our own, self-destruct. */
615  if (isReleased()) {
616  delete this;
617  }
618  }
619 
620  void
622  {
624  }
625 
626  virtual std::string name() const { return "LSQRequest"; }
627  };
628 
630  {
631  protected:
632  /* Given that we are inside templates, children need explicit
633  * declaration of the names in the parent class. */
636  using LSQRequest::_addr;
637  using LSQRequest::_fault;
638  using LSQRequest::_flags;
639  using LSQRequest::_size;
641  using LSQRequest::_requests;
642  using LSQRequest::_inst;
643  using LSQRequest::_packets;
644  using LSQRequest::_port;
645  using LSQRequest::_res;
646  using LSQRequest::_taskId;
648  using LSQRequest::_state;
649  using LSQRequest::flags;
650  using LSQRequest::isLoad;
652  using LSQRequest::lsqUnit;
653  using LSQRequest::request;
655  using LSQRequest::setState;
659  using LSQRequest::_amo_op;
660  public:
662  bool isLoad, const Addr& addr, const uint32_t& size,
663  const Request::Flags& flags_, PacketDataPtr data=nullptr,
664  uint64_t* res=nullptr, AtomicOpFunctorPtr amo_op=nullptr) :
665  LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
666  std::move(amo_op)) {}
667 
668  virtual ~SingleDataRequest() {}
669  virtual void initiateTranslation();
670  virtual void finish(const Fault &fault, const RequestPtr &req,
672  virtual bool recvTimingResp(PacketPtr pkt);
673  virtual void sendPacketToCache();
674  virtual void buildPackets();
675  virtual Cycles handleLocalAccess(
677  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
678  virtual std::string name() const { return "SingleDataRequest"; }
679  };
680 
681  // hardware transactional memory
682  // This class extends SingleDataRequest for the sole purpose
683  // of encapsulating hardware transactional memory command requests
685  {
686  protected:
687  /* Given that we are inside templates, children need explicit
688  * declaration of the names in the parent class. */
691  using LSQRequest::_addr;
692  using LSQRequest::_size;
694  using LSQRequest::_requests;
695  using LSQRequest::_inst;
696  using LSQRequest::_taskId;
697  using LSQRequest::flags;
698  using LSQRequest::setState;
699  public:
700  HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
701  const Request::Flags& flags_);
702  virtual ~HtmCmdRequest() {}
703  virtual void initiateTranslation();
704  virtual void finish(const Fault &fault, const RequestPtr &req,
706  virtual std::string name() const { return "HtmCmdRequest"; }
707  };
708 
710  {
711  protected:
712  /* Given that we are inside templates, children need explicit
713  * declaration of the names in the parent class. */
716  using LSQRequest::_addr;
717  using LSQRequest::_data;
718  using LSQRequest::_fault;
719  using LSQRequest::_flags;
720  using LSQRequest::_inst;
721  using LSQRequest::_packets;
722  using LSQRequest::_port;
723  using LSQRequest::_requests;
724  using LSQRequest::_res;
727  using LSQRequest::_size;
728  using LSQRequest::_state;
729  using LSQRequest::_taskId;
730  using LSQRequest::flags;
731  using LSQRequest::isLoad;
733  using LSQRequest::lsqUnit;
736  using LSQRequest::request;
738  using LSQRequest::setState;
740 
741  uint32_t numFragments;
745 
746  public:
747  SplitDataRequest(LSQUnit* port, const DynInstPtr& inst,
748  bool isLoad, const Addr& addr, const uint32_t& size,
749  const Request::Flags & flags_, PacketDataPtr data=nullptr,
750  uint64_t* res=nullptr) :
751  LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
752  nullptr),
753  numFragments(0),
755  mainReq(nullptr),
756  _mainPacket(nullptr)
757  {
758  flags.set(Flag::IsSplit);
759  }
761  {
762  if (mainReq) {
763  mainReq = nullptr;
764  }
765  if (_mainPacket) {
766  delete _mainPacket;
767  _mainPacket = nullptr;
768  }
769  }
770  virtual void finish(const Fault &fault, const RequestPtr &req,
772  virtual bool recvTimingResp(PacketPtr pkt);
773  virtual void initiateTranslation();
774  virtual void sendPacketToCache();
775  virtual void buildPackets();
776 
777  virtual Cycles handleLocalAccess(
779  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
780 
781  virtual RequestPtr mainRequest();
782  virtual PacketPtr mainPacket();
783  virtual std::string name() const { return "SplitDataRequest"; }
784  };
785 
787  LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params);
788 
790  std::string name() const;
791 
794 
796  void drainSanityCheck() const;
798  bool isDrained() const;
800  void takeOverFrom();
801 
803  int entryAmount(ThreadID num_threads);
804 
806  void tick();
807 
809  void insertLoad(const DynInstPtr &load_inst);
811  void insertStore(const DynInstPtr &store_inst);
812 
814  Fault executeLoad(const DynInstPtr &inst);
815 
817  Fault executeStore(const DynInstPtr &inst);
818 
822  void commitLoads(InstSeqNum &youngest_inst, ThreadID tid);
823 
827  void commitStores(InstSeqNum &youngest_inst, ThreadID tid);
828 
833  void writebackStores();
835  void writebackStores(ThreadID tid);
836 
840  void squash(const InstSeqNum &squashed_num, ThreadID tid);
841 
843  bool violation();
844 
849  bool violation(ThreadID tid);
850 
853 
855  int getLoadHead(ThreadID tid);
856 
859 
861  int getStoreHead(ThreadID tid);
862 
865 
867  int getCount();
869  int getCount(ThreadID tid);
870 
872  int numLoads();
874  int numLoads(ThreadID tid);
875 
877  int numStores();
879  int numStores(ThreadID tid);
880 
881 
882  // hardware transactional memory
883 
884  int numHtmStarts(ThreadID tid) const;
885  int numHtmStops(ThreadID tid) const;
886  void resetHtmStartsStops(ThreadID tid);
887  uint64_t getLatestHtmUid(ThreadID tid) const;
888  void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid);
889 
891  unsigned numFreeLoadEntries();
892 
894  unsigned numFreeStoreEntries();
895 
897  unsigned numFreeEntries(ThreadID tid);
898 
900  unsigned numFreeLoadEntries(ThreadID tid);
901 
903  unsigned numFreeStoreEntries(ThreadID tid);
904 
906  bool isFull();
911  bool isFull(ThreadID tid);
912 
914  bool isEmpty() const;
916  bool lqEmpty() const;
918  bool sqEmpty() const;
919 
921  bool lqFull();
923  bool lqFull(ThreadID tid);
924 
926  bool sqFull();
928  bool sqFull(ThreadID tid);
929 
934  bool isStalled();
939  bool isStalled(ThreadID tid);
940 
942  bool hasStoresToWB();
943 
947  bool hasStoresToWB(ThreadID tid);
948 
950  int numStoresToWB(ThreadID tid);
951 
953  bool willWB();
957  bool willWB(ThreadID tid);
958 
960  void dumpInsts() const;
962  void dumpInsts(ThreadID tid) const;
963 
967  Fault read(LSQRequest* req, int load_idx);
968 
972  Fault write(LSQRequest* req, uint8_t *data, int store_idx);
973 
977  void recvReqRetry();
978 
979  void completeDataAccess(PacketPtr pkt);
986  bool recvTimingResp(PacketPtr pkt);
987 
988  void recvTimingSnoopReq(PacketPtr pkt);
989 
990  Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
991  unsigned int size, Addr addr, Request::Flags flags,
992  uint64_t *res, AtomicOpFunctorPtr amo_op,
993  const std::vector<bool>& byte_enable);
994 
997 
1000 
1002  bool cacheBlocked() const;
1004  void cacheBlocked(bool v);
1006  bool cachePortAvailable(bool is_load) const;
1008  void cachePortBusy(bool is_load);
1009 
1011 
1012  protected:
1023 
1024 
1026  SMTQueuePolicy lsqPolicy;
1027 
1033  static uint32_t
1034  maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries,
1035  uint32_t numThreads, uint32_t SMTThreshold)
1036  {
1037  if (pol == SMTQueuePolicy::Dynamic) {
1038  return entries;
1039  } else if (pol == SMTQueuePolicy::Partitioned) {
1040  //@todo:make work if part_amt doesnt divide evenly.
1041  return entries / numThreads;
1042  } else if (pol == SMTQueuePolicy::Threshold) {
1043  //Divide up by threshold amount
1044  //@todo: Should threads check the max and the total
1045  //amount of the LSQ
1046  return SMTThreshold;
1047  }
1048  return 0;
1049  }
1050 
1053 
1055  unsigned LQEntries;
1057  unsigned SQEntries;
1058 
1060  unsigned maxLQEntries;
1061 
1063  unsigned maxSQEntries;
1064 
1067 
1070 
1073 };
1074 
1075 } // namespace o3
1076 } // namespace gem5
1077 
1078 #endif // __CPU_O3_LSQ_HH__
gem5::o3::LSQ::LSQRequest::release
void release(Flag reason)
Release the LSQRequest.
Definition: lsq.hh:349
gem5::o3::LSQ::LSQRequest::State::Translation
@ Translation
gem5::o3::LSQ::LQEntries
unsigned LQEntries
Total Size of LQ Entries.
Definition: lsq.hh:1055
gem5::o3::LSQ::LSQSenderState::inst
DynInstPtr inst
Instruction which initiated the access to memory.
Definition: lsq.hh:91
gem5::o3::LSQ::LSQRequest::_amo_op
AtomicOpFunctorPtr _amo_op
Definition: lsq.hh:301
gem5::o3::LSQ::lsqPolicy
SMTQueuePolicy lsqPolicy
The LSQ policy for SMT mode.
Definition: lsq.hh:1026
gem5::o3::LSQ::DcachePort::isSnooping
virtual bool isSnooping() const
As this CPU requires snooping to maintain the load store queue change the behaviour from the base CPU...
Definition: lsq.hh:160
gem5::o3::LSQ::LSQSenderState::isComplete
bool isComplete()
Completes a packet and returns whether the access is finished.
Definition: lsq.hh:114
gem5::o3::LSQ::LSQRequest::isAtomic
bool isAtomic() const
Definition: lsq.hh:317
gem5::o3::LSQ::insertStore
void insertStore(const DynInstPtr &store_inst)
Inserts a store into the LSQ.
Definition: lsq.cc:237
gem5::o3::LSQ::LSQRequest::Retry
@ Retry
Definition: lsq.hh:249
gem5::o3::LSQ::LSQRequest::_res
uint64_t * _res
Definition: lsq.hh:295
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:231
gem5::o3::LSQ::DcachePort::lsq
LSQ * lsq
Pointer to LSQ.
Definition: lsq.hh:130
utils.hh
gem5::o3::LSQ::SingleDataRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq.cc:941
gem5::o3::LSQ::commitLoads
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
Commits loads up until the given sequence number for a specific thread.
Definition: lsq.cc:261
gem5::o3::LSQ::LSQRequest::_addr
const Addr _addr
Definition: lsq.hh:296
gem5::o3::LSQ::numStoresToWB
int numStoresToWB(ThreadID tid)
Returns the number of stores a specific thread has to write back.
Definition: lsq.cc:727
gem5::o3::LSQ::LSQSenderState::complete
virtual void complete()=0
gem5::o3::LSQ::cacheBlocked
bool cacheBlocked() const
Is D-cache blocked?
Definition: lsq.cc:194
gem5::o3::LSQ::DcachePort::recvFunctionalSnoop
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
Definition: lsq.hh:146
gem5::o3::LSQ::LSQRequest::isTranslationComplete
bool isTranslationComplete()
Definition: lsq.hh:526
gem5::o3::LSQ::LSQRequest::_taskId
uint32_t _taskId
Definition: lsq.hh:290
gem5::o3::LSQ::LSQRequest::_data
PacketDataPtr _data
Definition: lsq.hh:291
gem5::o3::LSQ::LSQRequest::_byteEnable
std::vector< bool > _byteEnable
Definition: lsq.hh:299
gem5::o3::LSQ::SplitDataRequest::SplitDataRequest
SplitDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr)
Definition: lsq.hh:747
gem5::o3::LSQ::numFreeEntries
unsigned numFreeEntries(ThreadID tid)
Returns the number of free entries for a specific thread.
gem5::o3::LSQ::SplitDataRequest::name
virtual std::string name() const
Definition: lsq.hh:783
gem5::o3::LSQ::numThreads
ThreadID numThreads
Number of Threads.
Definition: lsq.hh:1072
gem5::o3::LSQ::LSQRequest::taskId
void taskId(const uint32_t &v)
Definition: lsq.hh:400
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::o3::LSQ::dumpInsts
void dumpInsts() const
Debugging function to print out all instructions.
Definition: lsq.cc:755
gem5::o3::LSQ::SplitDataRequest::~SplitDataRequest
virtual ~SplitDataRequest()
Definition: lsq.hh:760
gem5::o3::LSQ::LSQSenderState::deleteRequest
void deleteRequest()
Definition: lsq.hh:115
gem5::o3::LSQ::LSQRequest::isInTranslation
bool isInTranslation()
Definition: lsq.hh:520
gem5::o3::LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq.cc:464
gem5::o3::LSQ::SplitDataRequest::buildPackets
virtual void buildPackets()
Definition: lsq.cc:1196
gem5::o3::LSQ::writebackStores
void writebackStores()
Attempts to write back stores until all cache ports are used or the interface becomes blocked.
Definition: lsq.cc:273
gem5::o3::LSQ::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets the pointer to the list of active threads.
Definition: lsq.cc:138
gem5::o3::LSQ::read
Fault read(LSQRequest *req, int load_idx)
Executes a read operation, using the load specified at the load index.
Definition: lsq.cc:1424
gem5::o3::LSQ::lqEmpty
bool lqEmpty() const
Returns if all of the LQs are empty.
Definition: lsq.cc:594
gem5::o3::LSQ::LSQRequest::Discarded
@ Discarded
Request discarded.
Definition: lsq.hh:255
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::Flags::set
void set(Type mask)
Set all flag's bits matching the given mask.
Definition: flags.hh:116
gem5::o3::LSQ::_cacheBlocked
bool _cacheBlocked
D-cache is blocked.
Definition: lsq.hh:1014
gem5::o3::LSQ::SingleDataRequest::buildPackets
virtual void buildPackets()
Definition: lsq.cc:1163
gem5::o3::LSQ::LSQSenderState::needWB
bool needWB
Whether or not the instruction will need to writeback.
Definition: lsq.hh:101
gem5::o3::LSQ::LSQRequest::install
void install()
Install the request in the LQ/SQ.
Definition: lsq.cc:1077
gem5::o3::LSQ::SplitDataRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq.cc:974
gem5::o3::LSQ::LSQRequest::setState
void setState(const State &newState)
Definition: lsq.hh:276
gem5::Flags::clear
void clear()
Clear all flag's bits.
Definition: flags.hh:102
gem5::o3::LSQ::SplitDataRequest::handleLocalAccess
virtual Cycles handleLocalAccess(gem5::ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
Definition: lsq.cc:1287
gem5::o3::LSQ::DcachePort
DcachePort class for the load/store queue.
Definition: lsq.hh:125
gem5::o3::LSQ::LSQRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)=0
Test if the request accesses a particular cache line.
gem5::Complete
@ Complete
Definition: misc.hh:59
gem5::o3::LSQ::LSQRequest::isMemAccessRequired
bool isMemAccessRequired()
Definition: lsq.hh:553
gem5::o3::LSQ::getStoreHeadSeqNum
InstSeqNum getStoreHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the store queue.
Definition: lsq.cc:340
tlb.hh
gem5::o3::LSQ::LSQRequest::buildPackets
virtual void buildPackets()=0
gem5::o3::LSQ::numLoads
int numLoads()
Returns the total number of loads in the load queue.
Definition: lsq.cc:481
gem5::o3::LSQ::LSQRequest::isPartialFault
bool isPartialFault()
Definition: lsq.hh:547
gem5::o3::LSQ::SplitDataRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Caches may probe into the load-store queue to enforce memory ordering guarantees.
Definition: lsq.cc:1328
gem5::o3::LSQ::LSQRequest::State::PartialFault
@ PartialFault
gem5::o3::LSQ::cachePortAvailable
bool cachePortAvailable(bool is_load) const
Is any store port available to use?
Definition: lsq.cc:206
gem5::o3::LSQ::LSQSenderState::_request
LSQRequest * _request
The senderState needs to know the LSQRequest who owns it.
Definition: lsq.hh:84
gem5::o3::LSQ::LSQSenderState::outstanding
uint8_t outstanding
Number of outstanding packets to complete.
Definition: lsq.hh:97
gem5::o3::LSQ::LSQRequest::request
const RequestPtr request(int idx=0) const
Definition: lsq.hh:411
gem5::o3::LSQ
Definition: lsq.hh:75
gem5::o3::LSQ::LSQRequest::WritebackDone
@ WritebackDone
Definition: lsq.hh:260
gem5::o3::LSQ::LSQRequest::squashed
bool squashed() const override
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: lsq.cc:1088
gem5::o3::LSQ::LSQRequest::instruction
const DynInstPtr & instruction()
Definition: lsq.hh:387
gem5::o3::LSQ::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt)
Definition: lsq.cc:448
gem5::o3::LSQ::LSQRequest::sendPacketToCache
virtual void sendPacketToCache()=0
gem5::o3::LSQ::LSQRequest::LSQEntryFreed
@ LSQEntryFreed
LSQ resources freed.
Definition: lsq.hh:257
gem5::o3::LSQ::SplitDataRequest::_mainPacket
PacketPtr _mainPacket
Definition: lsq.hh:744
std::vector
STL vector class.
Definition: stl.hh:37
gem5::o3::LSQ::getStoreHead
int getStoreHead(ThreadID tid)
Returns the head index of the store queue.
Definition: lsq.cc:334
gem5::o3::LSQ::LSQRequest::mainPacket
virtual PacketPtr mainPacket()
Definition: lsq.hh:422
gem5::o3::LSQ::SingleDataRequest::name
virtual std::string name() const
Definition: lsq.hh:678
gem5::o3::LSQ::LSQRequest::getVaddr
Addr getVaddr(int idx=0) const
Definition: lsq.hh:416
gem5::PacketDataPtr
uint8_t * PacketDataPtr
Definition: packet.hh:71
gem5::o3::LSQ::SplitDataRequest::sendPacketToCache
virtual void sendPacketToCache()
Definition: lsq.cc:1269
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::o3::LSQ::name
std::string name() const
Returns the name of the LSQ.
Definition: lsq.cc:132
gem5::o3::LSQ::LSQRequest::Sent
@ Sent
Definition: lsq.hh:248
gem5::o3::LSQ::LSQRequest::~LSQRequest
virtual ~LSQRequest()
Destructor.
Definition: lsq.cc:1104
gem5::o3::LSQ::dcachePort
DcachePort dcachePort
Data port.
Definition: lsq.hh:1066
gem5::o3::LSQ::DcachePort::recvTimingSnoopReq
virtual void recvTimingSnoopReq(PacketPtr pkt)
Receive a timing snoop request from the peer.
Definition: lsq.cc:1356
gem5::o3::LSQ::isEmpty
bool isEmpty() const
Returns if the LSQ is empty (both LQ and SQ are empty).
Definition: lsq.cc:588
gem5::o3::LSQ::DcachePort::DcachePort
DcachePort(LSQ *_lsq, CPU *_cpu)
Default constructor.
Definition: lsq.cc:77
gem5::o3::LSQ::activeThreads
std::list< ThreadID > * activeThreads
List of Active Threads in System.
Definition: lsq.hh:1052
gem5::o3::LSQ::SplitDataRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Definition: lsq.cc:1136
gem5::o3::LSQ::LSQRequest::IsAtomic
@ IsAtomic
True if this is an atomic request.
Definition: lsq.hh:262
gem5::o3::LSQ::SingleDataRequest::sendPacketToCache
virtual void sendPacketToCache()
Definition: lsq.cc:1261
gem5::o3::LSQ::LSQRequest::setVirt
void setVirt(Addr vaddr, unsigned size, Request::Flags flags_, RequestorID requestor_id, Addr pc)
Set up virtual request.
Definition: lsq.hh:393
gem5::o3::LSQ::isStalled
bool isStalled()
Returns if the LSQ is stalled due to a memory operation that must be replayed.
Definition: lsq.cc:680
gem5::o3::LSQ::executeStore
Fault executeStore(const DynInstPtr &inst)
Executes a store.
Definition: lsq.cc:253
gem5::o3::LSQ::LSQRequest::State::Request
@ Request
gem5::o3::LSQ::LSQSenderState::LSQSenderState
LSQSenderState(LSQRequest *request, bool is_load)
Default constructor.
Definition: lsq.cc:67
gem5::o3::LSQ::cacheStorePorts
int cacheStorePorts
The number of cache ports available each cycle (stores only).
Definition: lsq.hh:1016
gem5::RefCountingPtr< DynInst >
gem5::o3::LSQ::sqFull
bool sqFull()
Returns if any of the SQs are full.
Definition: lsq.cc:653
gem5::o3::LSQ::resetHtmStartsStops
void resetHtmStartsStops(ThreadID tid)
Definition: lsq.cc:369
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::o3::LSQ::violation
bool violation()
Returns whether or not there was a memory ordering violation.
Definition: lsq.cc:297
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::LSQ::completeDataAccess
void completeDataAccess(PacketPtr pkt)
Definition: lsq.cc:403
gem5::o3::LSQ::numHtmStarts
int numHtmStarts(ThreadID tid) const
Definition: lsq.cc:352
gem5::o3::LSQ::SingleDataRequest::SingleDataRequest
SingleDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)
Definition: lsq.hh:661
gem5::o3::LSQ::LSQRequest::_size
const uint32_t _size
Definition: lsq.hh:297
gem5::o3::LSQ::numStores
int numStores()
Returns the total number of stores in the store queue.
Definition: lsq.cc:498
gem5::o3::LSQ::LSQRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)=0
gem5::o3::LSQ::LSQRequest::packetReplied
void packetReplied()
Definition: lsq.hh:584
gem5::Flags< FlagsStorage >
gem5::o3::LSQUnit
Class that implements the actual LQ and SQ for each specific thread.
Definition: lsq_unit.hh:90
gem5::o3::LSQ::HtmCmdRequest::HtmCmdRequest
HtmCmdRequest(LSQUnit *port, const DynInstPtr &inst, const Request::Flags &flags_)
Definition: lsq.cc:1372
gem5::o3::LSQ::SQEntries
unsigned SQEntries
Total Size of SQ Entries.
Definition: lsq.hh:1057
gem5::o3::LSQ::tick
void tick()
Ticks the LSQ.
Definition: lsq.cc:183
gem5::o3::LSQ::LSQRequest::_inst
const DynInstPtr _inst
Definition: lsq.hh:289
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::LSQ::LSQRequest::packetSent
void packetSent()
Update the status to reflect that a packet was sent.
Definition: lsq.hh:497
gem5::o3::LSQ::write
Fault write(LSQRequest *req, uint8_t *data, int store_idx)
Executes a store operation, using the store specified at the store index.
Definition: lsq.cc:1432
gem5::o3::LSQ::LSQRequest::setStateToFault
void setStateToFault()
Definition: lsq.hh:560
gem5::o3::LSQ::SplitDataRequest::numFragments
uint32_t numFragments
Definition: lsq.hh:741
gem5::o3::LSQ::LSQRequest::squashTranslation
void squashTranslation()
Definition: lsq.hh:610
gem5::o3::LSQ::maxSQEntries
unsigned maxSQEntries
Max SQ Size - Used to Enforce Sharing Policies.
Definition: lsq.hh:1063
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::o3::LSQ::LSQRequest::isTranslationBlocked
bool isTranslationBlocked()
Definition: lsq.hh:533
gem5::o3::LSQ::LSQRequest::discard
void discard()
The request is discarded (e.g.
Definition: lsq.hh:578
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::LSQ::SplitDataRequest
Definition: lsq.hh:709
gem5::Flags::isSet
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition: flags.hh:83
gem5::o3::LSQ::isDrained
bool isDrained() const
Has the LSQ drained?
Definition: lsq.cc:154
gem5::o3::LSQ::LSQSenderState::isSplit
bool isSplit
Whether or not this access is split in two.
Definition: lsq.hh:103
gem5::o3::LSQ::LSQRequest::discardSenderState
void discardSenderState()
Mark senderState as discarded.
Definition: lsq.hh:456
sim_object.hh
gem5::o3::LSQ::LSQRequest::_packets
std::vector< PacketPtr > _packets
Definition: lsq.hh:292
gem5::o3::LSQ::iewStage
IEW * iewStage
The IEW stage pointer.
Definition: lsq.hh:999
gem5::o3::LSQ::HtmCmdRequest::name
virtual std::string name() const
Definition: lsq.hh:706
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::LSQ::LSQRequest::State::Fault
@ Fault
gem5::o3::LSQ::LSQRequest::Delayed
@ Delayed
Definition: lsq.hh:242
gem5::o3::LSQ::LSQRequest::_entryIdx
uint32_t _entryIdx
LQ/SQ entry idx.
Definition: lsq.hh:282
gem5::o3::LSQ::LSQRequest::State
State
Definition: lsq.hh:266
gem5::o3::LSQ::LSQRequest::packetNotSent
void packetNotSent()
Update the status to reflect that a packet was not sent.
Definition: lsq.hh:506
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::o3::LSQ::LSQRequest::flags
FlagsType flags
Definition: lsq.hh:264
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::LSQ::LSQRequest::packet
PacketPtr packet(int idx=0)
Definition: lsq.hh:419
gem5::o3::LSQ::getLatestHtmUid
uint64_t getLatestHtmUid(ThreadID tid) const
Definition: lsq.cc:376
gem5::o3::LSQ::LSQRequest::State::NotIssued
@ NotIssued
gem5::o3::LSQ::LSQRequest::IsSplit
@ IsSplit
Definition: lsq.hh:243
mmu.hh
gem5::o3::LSQ::LSQRequest::_numOutstandingPackets
uint32_t _numOutstandingPackets
Definition: lsq.hh:300
gem5::o3::LSQ::willWB
bool willWB()
Returns if the LSQ will write back to memory this cycle.
Definition: lsq.cc:733
gem5::o3::LSQ::numFreeLoadEntries
unsigned numFreeLoadEntries()
Returns the number of free load entries.
Definition: lsq.cc:515
gem5::o3::LSQ::SplitDataRequest::mainReq
RequestPtr mainReq
Definition: lsq.hh:743
port.hh
gem5::o3::LSQ::LSQRequest::Complete
@ Complete
Definition: lsq.hh:250
gem5::o3::LSQ::cachePortBusy
void cachePortBusy(bool is_load)
Another store port is in use.
Definition: lsq.cc:218
gem5::o3::LSQ::LSQSenderState::alive
bool alive()
Definition: lsq.hh:116
gem5::o3::LSQ::HtmCmdRequest::~HtmCmdRequest
virtual ~HtmCmdRequest()
Definition: lsq.hh:702
gem5::o3::LSQ::DcachePort::recvReqRetry
virtual void recvReqRetry()
Handles doing a retry of the previous send.
Definition: lsq.cc:1367
gem5::o3::LSQ::LSQRequest::name
virtual std::string name() const
Definition: lsq.hh:626
gem5::o3::LSQ::LSQRequest::isReleased
bool isReleased()
Test if the LSQRequest has been released, i.e.
Definition: lsq.hh:333
gem5::o3::LSQ::LSQRequest::request
RequestPtr request(int idx=0)
Definition: lsq.hh:408
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::o3::LSQ::LSQRequest::senderState
void senderState(LSQSenderState *st)
Definition: lsq.hh:436
gem5::o3::LSQ::SplitDataRequest::mainPacket
virtual PacketPtr mainPacket()
Definition: lsq.cc:962
gem5::o3::LSQ::LSQSenderState::pktToSend
bool pktToSend
Whether or not there is a packet that needs sending.
Definition: lsq.hh:105
gem5::o3::LSQ::LSQRequest::isDelayed
bool isDelayed()
Definition: lsq.hh:285
gem5::o3::LSQ::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: lsq.cc:385
gem5::o3::LSQ::DcachePort::cpu
CPU * cpu
Definition: lsq.hh:131
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::LSQ::LSQRequest::_flags
const Request::Flags _flags
Definition: lsq.hh:298
dyn_inst_ptr.hh
gem5::o3::LSQ::SingleDataRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Test if the request accesses a particular cache line.
Definition: lsq.cc:1307
gem5::o3::LSQ::entryAmount
int entryAmount(ThreadID num_threads)
Number of entries needed for the given amount of threads.
gem5::o3::LSQ::getMemDepViolator
DynInstPtr getMemDepViolator(ThreadID tid)
Gets the instruction that caused the memory ordering violation.
Definition: lsq.cc:316
gem5::o3::LSQ::LSQRequest::complete
void complete()
Definition: lsq.hh:621
flags.hh
gem5::o3::LSQ::LSQSenderState::contextId
ContextID contextId()
Definition: lsq.cc:72
gem5::o3::LSQ::LSQRequest::TranslationFinished
@ TranslationFinished
True if there are un-replied outbound translations.
Definition: lsq.hh:247
gem5::o3::LSQ::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squash instructions from a thread until the specified sequence number.
Definition: lsq.cc:291
gem5::o3::LSQ::sqEmpty
bool sqEmpty() const
Returns if all of the SQs are empty.
Definition: lsq.cc:610
gem5::o3::LSQ::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: lsq.cc:145
gem5::o3::LSQ::LSQRequest::isSent
bool isSent()
Definition: lsq.hh:541
gem5::o3::LSQ::SingleDataRequest::~SingleDataRequest
virtual ~SingleDataRequest()
Definition: lsq.hh:668
gem5::o3::LSQ::maxLSQAllocation
static uint32_t maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries, uint32_t numThreads, uint32_t SMTThreshold)
Auxiliary function to calculate per-thread max LSQ allocation limit.
Definition: lsq.hh:1034
gem5::o3::LSQ::LSQRequest::senderState
const LSQSenderState * senderState() const
Definition: lsq.hh:446
gem5::o3::LSQ::LSQSenderState::pendingPacket
PacketPtr pendingPacket
A second packet from a split store that needs sending.
Definition: lsq.hh:95
gem5::o3::LSQ::SingleDataRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Definition: lsq.cc:1124
gem5::o3::LSQ::recvReqRetry
void recvReqRetry()
Retry the previous send that failed.
Definition: lsq.cc:392
gem5::o3::LSQ::LSQRequest::FlagsType
Flags< FlagsStorage > FlagsType
Definition: lsq.hh:235
gem5::o3::LSQ::SingleDataRequest::handleLocalAccess
virtual Cycles handleLocalAccess(gem5::ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
Definition: lsq.cc:1280
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::o3::LSQ::LSQRequest::_port
LSQUnit & _port
Definition: lsq.hh:288
gem5::o3::LSQ::HtmCmdRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq.cc:1400
gem5::o3::LSQ::LSQSenderState::isLoad
bool isLoad
Whether or not it is a load.
Definition: lsq.hh:99
gem5::o3::LSQ::LSQRequest::writebackScheduled
void writebackScheduled()
Definition: lsq.hh:593
gem5::o3::LSQ::insertLoad
void insertLoad(const DynInstPtr &load_inst)
Inserts a load into the LSQ.
Definition: lsq.cc:229
gem5::o3::LSQ::LSQSenderState
Derived class to hold any sender state the LSQ needs.
Definition: lsq.hh:80
gem5::o3::LSQ::LSQRequest::LSQRequest
LSQRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad)
Definition: lsq.cc:1042
gem5::o3::LSQ::LSQRequest::lsqUnit
LSQUnit * lsqUnit()
Definition: lsq.hh:303
gem5::o3::LSQ::cpu
CPU * cpu
The CPU pointer.
Definition: lsq.hh:996
gem5::o3::LSQ::LSQRequest::mainRequest
virtual RequestPtr mainRequest()
Definition: lsq.hh:429
gem5::o3::LSQ::hasStoresToWB
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
Definition: lsq.cc:705
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
types.hh
gem5::o3::LSQ::getLoadHead
int getLoadHead(ThreadID tid)
Returns the head index of the load queue for a specific thread.
Definition: lsq.cc:322
gem5::o3::LSQ::SplitDataRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
Definition: lsq.cc:893
gem5::o3::LSQ::LSQRequest::_requests
std::vector< RequestPtr > _requests
Definition: lsq.hh:293
gem5::o3::LSQ::maxLQEntries
unsigned maxLQEntries
Max LQ Size - Used to Enforce Sharing Policies.
Definition: lsq.hh:1060
gem5::o3::LSQ::SplitDataRequest::mainRequest
virtual RequestPtr mainRequest()
Definition: lsq.cc:968
gem5::o3::LSQ::LSQRequest::markDelayed
void markDelayed() override
Signal that the translation has been delayed due to a hw page table walk.
Definition: lsq.hh:284
gem5::o3::LSQ::getLoadHeadSeqNum
InstSeqNum getLoadHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the load queue.
Definition: lsq.cc:328
gem5::o3::LSQ::LSQRequest::TranslationSquashed
@ TranslationSquashed
Ownership tracking flags.
Definition: lsq.hh:253
gem5::o3::LSQ::HtmCmdRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
Definition: lsq.cc:1417
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::o3::LSQ::LSQSenderState::mainPkt
PacketPtr mainPkt
The main packet from a split load, used during writeback.
Definition: lsq.hh:93
gem5::o3::LSQ::numFreeStoreEntries
unsigned numFreeStoreEntries()
Returns the number of free store entries.
Definition: lsq.cc:532
gem5::o3::LSQ::LSQRequest::isAnyOutstandingRequest
bool isAnyOutstandingRequest()
Test if there is any in-flight translation or mem access request.
Definition: lsq.hh:466
gem5::o3::LSQ::LSQRequest::initiateTranslation
virtual void initiateTranslation()=0
gem5::o3::LSQ::usedStorePorts
int usedStorePorts
The number of used cache ports in this cycle by stores.
Definition: lsq.hh:1018
gem5::o3::LSQ::LSQ
LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params)
Constructs an LSQ with the given parameters.
Definition: lsq.cc:81
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::LSQ::LSQRequest::FlagsStorage
uint32_t FlagsStorage
Definition: lsq.hh:234
gem5::o3::LSQ::LSQRequest::handleLocalAccess
virtual Cycles handleLocalAccess(gem5::ThreadContext *thread, PacketPtr pkt)=0
Memory mapped IPR accesses.
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::o3::LSQ::SingleDataRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
Definition: lsq.cc:861
gem5::o3::LSQ::LSQRequest::taskId
uint32_t taskId() const
Definition: lsq.hh:407
gem5::o3::LSQ::HtmCmdRequest
Definition: lsq.hh:684
gem5::o3::LSQ::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable)
Definition: lsq.cc:774
gem5::o3::LSQ::LSQRequest::numTranslatedFragments
uint32_t numTranslatedFragments
Definition: lsq.hh:278
gem5::o3::LSQ::LSQRequest::writebackDone
void writebackDone()
Definition: lsq.hh:600
gem5::o3::LSQ::DcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
Definition: lsq.cc:1350
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::o3::LSQ::LSQRequest::IsLoad
@ IsLoad
Definition: lsq.hh:239
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:1010
gem5::o3::LSQ::LSQRequest::isLoad
bool isLoad() const
Definition: lsq.hh:311
gem5::o3::LSQ::LSQRequest::WritebackScheduled
@ WritebackScheduled
Store written back.
Definition: lsq.hh:259
gem5::o3::LSQ::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: lsq.cc:172
gem5::o3::LSQ::commitStores
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
Commits stores up until the given sequence number for a specific thread.
Definition: lsq.cc:267
gem5::o3::LSQ::LSQSenderState::deleted
bool deleted
Has the request been deleted? LSQ entries can be squashed before the response comes back.
Definition: lsq.hh:110
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::o3::LSQ::LSQSenderState::writebackDone
void writebackDone()
Definition: lsq.hh:119
std::list< ThreadID >
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::o3::LSQ::LSQRequest::WbStore
@ WbStore
True if this is a store/atomic that writes registers (SC).
Definition: lsq.hh:241
gem5::o3::LSQ::LSQRequest::Flag
Flag
Definition: lsq.hh:237
gem5::o3::LSQ::lqFull
bool lqFull()
Returns if any of the LQs are full.
Definition: lsq.cc:626
gem5::o3::LSQ::LSQRequest::TranslationStarted
@ TranslationStarted
True if any translation has been sent to TLB.
Definition: lsq.hh:245
gem5::ArmISA::st
Bitfield< 31, 28 > st
Definition: misc_types.hh:155
gem5::o3::LSQ::numHtmStops
int numHtmStops(ThreadID tid) const
Definition: lsq.cc:360
gem5::o3::LSQ::LSQRequest::setContext
void setContext(const ContextID &context_id)
Convenience getters/setters.
Definition: lsq.hh:382
gem5::o3::LSQ::LSQRequest::isComplete
bool isComplete()
Definition: lsq.hh:514
gem5::o3::LSQ::LSQRequest::sendFragmentToTranslation
void sendFragmentToTranslation(int i)
Definition: lsq.cc:1116
gem5::o3::LSQ::LSQRequest::_fault
std::vector< Fault > _fault
Definition: lsq.hh:294
gem5::o3::LSQ::LSQRequest::addRequest
void addRequest(Addr addr, unsigned size, const std::vector< bool > &byte_enable)
Helper function used to add a (sub)request, given its address addr, size size and byte-enable mask by...
Definition: lsq.cc:1091
gem5::o3::LSQ::executeLoad
Fault executeLoad(const DynInstPtr &inst)
Executes a load.
Definition: lsq.cc:245
gem5::o3::LSQ::LSQRequest::numInTranslationFragments
uint32_t numInTranslationFragments
Definition: lsq.hh:279
gem5::o3::LSQ::LSQSenderState::request
LSQRequest * request()
Definition: lsq.hh:117
gem5::o3::LSQ::usedLoadPorts
int usedLoadPorts
The number of used cache ports in this cycle by loads.
Definition: lsq.hh:1022
gem5::o3::LSQ::thread
std::vector< LSQUnit > thread
The LSQ units for individual threads.
Definition: lsq.hh:1069
gem5::o3::LSQ::isFull
bool isFull()
Returns if the LSQ is full (either LQ or SQ is full).
Definition: lsq.cc:561
gem5::o3::LSQ::LSQRequest::isSplit
bool isSplit() const
Definition: lsq.hh:475
gem5::o3::LSQ::LSQRequest::_state
State _state
Definition: lsq.hh:274
gem5::o3::LSQ::SplitDataRequest::numReceivedPackets
uint32_t numReceivedPackets
Definition: lsq.hh:742
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::LSQ::SingleDataRequest
Definition: lsq.hh:629
gem5::o3::LSQ::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Handles writing back and completing the load or store that has returned from memory.
Definition: lsq.cc:411
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::LSQ::LSQRequest::_senderState
LSQSenderState * _senderState
Definition: lsq.hh:275
gem5::o3::LSQ::cacheLoadPorts
int cacheLoadPorts
The number of cache ports available each cycle (loads only).
Definition: lsq.hh:1020
gem5::o3::LSQ::LSQRequest::freeLSQEntry
void freeLSQEntry()
The LSQ entry is cleared.
Definition: lsq.hh:569

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