gem5  v21.2.1.1
lsq.hh
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41 
42 #ifndef __CPU_O3_LSQ_HH__
43 #define __CPU_O3_LSQ_HH__
44 
45 #include <cassert>
46 #include <cstdint>
47 #include <list>
48 #include <map>
49 #include <queue>
50 #include <vector>
51 
52 #include "arch/generic/mmu.hh"
53 #include "arch/generic/tlb.hh"
54 #include "base/flags.hh"
55 #include "base/types.hh"
56 #include "cpu/inst_seq.hh"
57 #include "cpu/o3/dyn_inst_ptr.hh"
58 #include "cpu/utils.hh"
59 #include "enums/SMTQueuePolicy.hh"
60 #include "mem/port.hh"
61 #include "sim/sim_object.hh"
62 
63 namespace gem5
64 {
65 
66 struct O3CPUParams;
67 
68 namespace o3
69 {
70 
71 class CPU;
72 class IEW;
73 class LSQUnit;
74 
75 class LSQ
76 {
77  public:
78  class LSQRequest;
79 
83  class DcachePort : public RequestPort
84  {
85  protected:
86 
88  LSQ *lsq;
89  CPU *cpu;
90 
91  public:
93  DcachePort(LSQ *_lsq, CPU *_cpu);
94 
95  protected:
96 
100  virtual bool recvTimingResp(PacketPtr pkt);
101  virtual void recvTimingSnoopReq(PacketPtr pkt);
102 
103  virtual void
105  {
106  // @todo: Is there a need for potential invalidation here?
107  }
108 
110  virtual void recvReqRetry();
111 
118  virtual bool isSnooping() const { return true; }
119  };
120 
190  {
191  protected:
192  typedef uint32_t FlagsStorage;
194 
196  {
197  IsLoad = 0x00000001,
202  WriteBackToRegister = 0x00000002,
203  Delayed = 0x00000004,
204  IsSplit = 0x00000008,
206  TranslationStarted = 0x00000010,
208  TranslationFinished = 0x00000020,
209  Sent = 0x00000040,
210  Retry = 0x00000080,
211  Complete = 0x00000100,
214  TranslationSquashed = 0x00000200,
216  Discarded = 0x00000400,
218  LSQEntryFreed = 0x00000800,
220  WritebackScheduled = 0x00001000,
221  WritebackDone = 0x00002000,
223  IsAtomic = 0x00004000
224  };
226 
227  enum class State
228  {
229  NotIssued,
230  Translation,
231  Request,
232  Fault,
233  PartialFault,
234  };
236  void setState(const State& newState) { _state = newState; }
237 
240 
241 
242  void markDelayed() override { flags.set(Flag::Delayed); }
243  bool isDelayed() { return flags.isSet(Flag::Delayed); }
244 
245  public:
248  uint32_t _taskId;
253  uint64_t* _res;
254  const Addr _addr;
255  const uint32_t _size;
260 
261  protected:
262  LSQUnit* lsqUnit() { return &_port; }
263  LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad);
264  LSQRequest(LSQUnit* port, const DynInstPtr& inst, bool isLoad,
265  const Addr& addr, const uint32_t& size,
266  const Request::Flags& flags_, PacketDataPtr data=nullptr,
267  uint64_t* res=nullptr, AtomicOpFunctorPtr amo_op=nullptr);
268 
269  bool
270  isLoad() const
271  {
272  return flags.isSet(Flag::IsLoad);
273  }
274 
275  bool
276  isAtomic() const
277  {
278  return flags.isSet(Flag::IsAtomic);
279  }
280 
282  void install();
283 
284  bool squashed() const override;
285 
286 
296  void
297  release(Flag reason)
298  {
299  assert(reason == Flag::LSQEntryFreed || reason == Flag::Discarded);
300  if (!isAnyOutstandingRequest()) {
301  delete this;
302  } else {
303  flags.set(reason);
304  }
305  }
306 
313  void addReq(Addr addr, unsigned size,
314  const std::vector<bool>& byte_enable);
315 
320  virtual ~LSQRequest();
321 
322  public:
326  void
327  setContext(const ContextID& context_id)
328  {
329  req()->setContext(context_id);
330  }
331 
332  const DynInstPtr& instruction() { return _inst; }
333 
337  void
338  setVirt(Addr vaddr, unsigned size, Request::Flags flags_,
339  RequestorID requestor_id, Addr pc)
340  {
341  req()->setVirt(vaddr, size, flags_, requestor_id, pc);
342  }
343 
344  ContextID contextId() const;
345 
346  void
347  taskId(const uint32_t& v)
348  {
349  _taskId = v;
350  for (auto& r: _reqs)
351  r->taskId(v);
352  }
353 
354  uint32_t taskId() const { return _taskId; }
355 
356  RequestPtr req(int idx = 0) { return _reqs.at(idx); }
357  const RequestPtr req(int idx = 0) const { return _reqs.at(idx); }
358 
359  Addr getVaddr(int idx = 0) const { return req(idx)->getVaddr(); }
360  virtual void initiateTranslation() = 0;
361 
362  PacketPtr packet(int idx = 0) { return _packets.at(idx); }
363 
364  virtual PacketPtr
366  {
367  assert (_packets.size() == 1);
368  return packet();
369  }
370 
371  virtual RequestPtr
373  {
374  assert (_reqs.size() == 1);
375  return req();
376  }
377 
381  bool
383  {
384  return numInTranslationFragments > 0 ||
386  (flags.isSet(Flag::WritebackScheduled) &&
387  !flags.isSet(Flag::WritebackDone));
388  }
389 
395  bool
397  {
398  return flags.isSet(Flag::LSQEntryFreed) ||
399  flags.isSet(Flag::Discarded);
400  }
401 
402  bool
403  isSplit() const
404  {
405  return flags.isSet(Flag::IsSplit);
406  }
407 
408  bool
410  {
411  return flags.isSet(Flag::WriteBackToRegister);
412  }
414  virtual bool recvTimingResp(PacketPtr pkt) = 0;
415  virtual void sendPacketToCache() = 0;
416  virtual void buildPackets() = 0;
417 
421  virtual Cycles handleLocalAccess(
423 
427  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask) = 0;
428 
430  void
432  {
433  flags.set(Flag::Sent);
434  }
439  void
441  {
442  flags.set(Flag::Retry);
443  flags.clear(Flag::Sent);
444  }
445 
446  void sendFragmentToTranslation(int i);
447  bool
449  {
450  return flags.isSet(Flag::Complete);
451  }
452 
453  bool
455  {
456  return _state == State::Translation;
457  }
458 
459  bool
461  {
462  return flags.isSet(Flag::TranslationStarted) &&
463  !isInTranslation();
464  }
465 
466  bool
468  {
469  return _state == State::Translation &&
470  flags.isSet(Flag::TranslationStarted) &&
471  !flags.isSet(Flag::TranslationFinished);
472  }
473 
474  bool
476  {
477  return flags.isSet(Flag::Sent);
478  }
479 
480  bool
482  {
483  return _state == State::PartialFault;
484  }
485 
486  bool
488  {
489  return (_state == State::Request ||
490  (isPartialFault() && isLoad()));
491  }
492 
493  void
495  {
497  }
498 
502  void
504  {
505  release(Flag::LSQEntryFreed);
506  }
507 
511  void
513  {
514  release(Flag::Discarded);
515  }
516 
517  void
519  {
520  assert(_numOutstandingPackets > 0);
522  if (_numOutstandingPackets == 0 && isReleased())
523  delete this;
524  }
525 
526  void
528  {
529  assert(!flags.isSet(Flag::WritebackScheduled));
530  flags.set(Flag::WritebackScheduled);
531  }
532 
533  void
535  {
536  flags.set(Flag::WritebackDone);
537  /* If the lsq resources are already free */
538  if (isReleased()) {
539  delete this;
540  }
541  }
542 
543  void
545  {
546  assert(numInTranslationFragments == 0);
547  flags.set(Flag::TranslationSquashed);
548  /* If we are on our own, self-destruct. */
549  if (isReleased()) {
550  delete this;
551  }
552  }
553 
554  void
556  {
558  }
559 
560  virtual std::string name() const { return "LSQRequest"; }
561  };
562 
564  {
565  public:
567  bool isLoad, const Addr& addr, const uint32_t& size,
568  const Request::Flags& flags_, PacketDataPtr data=nullptr,
569  uint64_t* res=nullptr, AtomicOpFunctorPtr amo_op=nullptr) :
570  LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
571  std::move(amo_op)) {}
572 
573  virtual ~SingleDataRequest() {}
574  virtual void initiateTranslation();
575  virtual void finish(const Fault &fault, const RequestPtr &req,
577  virtual bool recvTimingResp(PacketPtr pkt);
578  virtual void sendPacketToCache();
579  virtual void buildPackets();
580  virtual Cycles handleLocalAccess(
582  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
583  virtual std::string name() const { return "SingleDataRequest"; }
584  };
585 
586  // hardware transactional memory
587  // This class extends SingleDataRequest for the sole purpose
588  // of encapsulating hardware transactional memory command requests
590  {
591  public:
592  HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
593  const Request::Flags& flags_);
594  virtual ~HtmCmdRequest() {}
595  virtual void initiateTranslation();
596  virtual void finish(const Fault &fault, const RequestPtr &req,
598  virtual std::string name() const { return "HtmCmdRequest"; }
599  };
600 
602  {
603  protected:
604  uint32_t numFragments;
608 
609  public:
610  SplitDataRequest(LSQUnit* port, const DynInstPtr& inst,
611  bool isLoad, const Addr& addr, const uint32_t& size,
612  const Request::Flags & flags_, PacketDataPtr data=nullptr,
613  uint64_t* res=nullptr) :
614  LSQRequest(port, inst, isLoad, addr, size, flags_, data, res,
615  nullptr),
616  numFragments(0),
618  _mainReq(nullptr),
619  _mainPacket(nullptr)
620  {
621  flags.set(Flag::IsSplit);
622  }
624  {
625  if (_mainReq) {
626  _mainReq = nullptr;
627  }
628  if (_mainPacket) {
629  delete _mainPacket;
630  _mainPacket = nullptr;
631  }
632  }
633  virtual void finish(const Fault &fault, const RequestPtr &req,
635  virtual bool recvTimingResp(PacketPtr pkt);
636  virtual void initiateTranslation();
637  virtual void sendPacketToCache();
638  virtual void buildPackets();
639 
640  virtual Cycles handleLocalAccess(
642  virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask);
643 
644  virtual RequestPtr mainReq();
645  virtual PacketPtr mainPacket();
646  virtual std::string name() const { return "SplitDataRequest"; }
647  };
648 
650  LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params);
651 
653  std::string name() const;
654 
657 
659  void drainSanityCheck() const;
661  bool isDrained() const;
663  void takeOverFrom();
664 
666  int entryAmount(ThreadID num_threads);
667 
669  void tick();
670 
672  void insertLoad(const DynInstPtr &load_inst);
674  void insertStore(const DynInstPtr &store_inst);
675 
677  Fault executeLoad(const DynInstPtr &inst);
678 
680  Fault executeStore(const DynInstPtr &inst);
681 
685  void commitLoads(InstSeqNum &youngest_inst, ThreadID tid);
686 
690  void commitStores(InstSeqNum &youngest_inst, ThreadID tid);
691 
696  void writebackStores();
698  void writebackStores(ThreadID tid);
699 
703  void squash(const InstSeqNum &squashed_num, ThreadID tid);
704 
706  bool violation();
707 
712  bool violation(ThreadID tid);
713 
716 
718  int getLoadHead(ThreadID tid);
719 
722 
724  int getStoreHead(ThreadID tid);
725 
728 
730  int getCount();
732  int getCount(ThreadID tid);
733 
735  int numLoads();
737  int numLoads(ThreadID tid);
738 
740  int numStores();
742  int numStores(ThreadID tid);
743 
744 
745  // hardware transactional memory
746 
747  int numHtmStarts(ThreadID tid) const;
748  int numHtmStops(ThreadID tid) const;
749  void resetHtmStartsStops(ThreadID tid);
750  uint64_t getLatestHtmUid(ThreadID tid) const;
751  void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid);
752 
754  unsigned numFreeLoadEntries();
755 
757  unsigned numFreeStoreEntries();
758 
760  unsigned numFreeEntries(ThreadID tid);
761 
763  unsigned numFreeLoadEntries(ThreadID tid);
764 
766  unsigned numFreeStoreEntries(ThreadID tid);
767 
769  bool isFull();
774  bool isFull(ThreadID tid);
775 
777  bool isEmpty() const;
779  bool lqEmpty() const;
781  bool sqEmpty() const;
782 
784  bool lqFull();
786  bool lqFull(ThreadID tid);
787 
789  bool sqFull();
791  bool sqFull(ThreadID tid);
792 
797  bool isStalled();
802  bool isStalled(ThreadID tid);
803 
805  bool hasStoresToWB();
806 
810  bool hasStoresToWB(ThreadID tid);
811 
813  int numStoresToWB(ThreadID tid);
814 
816  bool willWB();
820  bool willWB(ThreadID tid);
821 
823  void dumpInsts() const;
825  void dumpInsts(ThreadID tid) const;
826 
830  Fault read(LSQRequest* request, int load_idx);
831 
835  Fault write(LSQRequest* request, uint8_t *data, int store_idx);
836 
840  void recvReqRetry();
841 
842  void completeDataAccess(PacketPtr pkt);
849  bool recvTimingResp(PacketPtr pkt);
850 
851  void recvTimingSnoopReq(PacketPtr pkt);
852 
853  Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
854  unsigned int size, Addr addr, Request::Flags flags,
855  uint64_t *res, AtomicOpFunctorPtr amo_op,
856  const std::vector<bool>& byte_enable);
857 
860 
863 
865  bool cacheBlocked() const;
867  void cacheBlocked(bool v);
869  bool cachePortAvailable(bool is_load) const;
871  void cachePortBusy(bool is_load);
872 
874 
875  protected:
886 
887 
889  SMTQueuePolicy lsqPolicy;
890 
896  static uint32_t
897  maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries,
898  uint32_t numThreads, uint32_t SMTThreshold)
899  {
900  if (pol == SMTQueuePolicy::Dynamic) {
901  return entries;
902  } else if (pol == SMTQueuePolicy::Partitioned) {
903  //@todo:make work if part_amt doesnt divide evenly.
904  return entries / numThreads;
905  } else if (pol == SMTQueuePolicy::Threshold) {
906  //Divide up by threshold amount
907  //@todo: Should threads check the max and the total
908  //amount of the LSQ
909  return SMTThreshold;
910  }
911  return 0;
912  }
913 
916 
918  unsigned LQEntries;
920  unsigned SQEntries;
921 
923  unsigned maxLQEntries;
924 
926  unsigned maxSQEntries;
927 
930 
933 
936 };
937 
938 } // namespace o3
939 } // namespace gem5
940 
941 #endif // __CPU_O3_LSQ_HH__
gem5::o3::LSQ::LSQRequest::release
void release(Flag reason)
Release the LSQRequest.
Definition: lsq.hh:297
gem5::o3::LSQ::LSQRequest::State::Translation
@ Translation
gem5::o3::LSQ::LQEntries
unsigned LQEntries
Total Size of LQ Entries.
Definition: lsq.hh:918
gem5::o3::LSQ::LSQRequest::_amo_op
AtomicOpFunctorPtr _amo_op
Definition: lsq.hh:259
gem5::o3::LSQ::lsqPolicy
SMTQueuePolicy lsqPolicy
The LSQ policy for SMT mode.
Definition: lsq.hh:889
gem5::o3::LSQ::DcachePort::isSnooping
virtual bool isSnooping() const
As this CPU requires snooping to maintain the load store queue change the behaviour from the base CPU...
Definition: lsq.hh:118
gem5::o3::LSQ::LSQRequest::isAtomic
bool isAtomic() const
Definition: lsq.hh:276
gem5::o3::LSQ::insertStore
void insertStore(const DynInstPtr &store_inst)
Inserts a store into the LSQ.
Definition: lsq.cc:227
gem5::o3::LSQ::LSQRequest::Retry
@ Retry
Definition: lsq.hh:210
gem5::o3::LSQ::LSQRequest::_res
uint64_t * _res
Definition: lsq.hh:253
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:189
gem5::o3::LSQ::LSQRequest::req
const RequestPtr req(int idx=0) const
Definition: lsq.hh:357
gem5::o3::LSQ::DcachePort::lsq
LSQ * lsq
Pointer to LSQ.
Definition: lsq.hh:88
utils.hh
gem5::o3::LSQ::SingleDataRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq.cc:931
gem5::o3::LSQ::commitLoads
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
Commits loads up until the given sequence number for a specific thread.
Definition: lsq.cc:251
gem5::o3::LSQ::LSQRequest::_addr
const Addr _addr
Definition: lsq.hh:254
gem5::o3::LSQ::numStoresToWB
int numStoresToWB(ThreadID tid)
Returns the number of stores a specific thread has to write back.
Definition: lsq.cc:717
gem5::o3::LSQ::cacheBlocked
bool cacheBlocked() const
Is D-cache blocked?
Definition: lsq.cc:184
gem5::o3::LSQ::DcachePort::recvFunctionalSnoop
virtual void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the peer.
Definition: lsq.hh:104
gem5::o3::LSQ::LSQRequest::isTranslationComplete
bool isTranslationComplete()
Definition: lsq.hh:460
gem5::o3::LSQ::LSQRequest::_taskId
uint32_t _taskId
Definition: lsq.hh:248
gem5::o3::LSQ::LSQRequest::_data
PacketDataPtr _data
Definition: lsq.hh:249
gem5::o3::LSQ::LSQRequest::_byteEnable
std::vector< bool > _byteEnable
Definition: lsq.hh:257
gem5::o3::LSQ::SplitDataRequest::SplitDataRequest
SplitDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr)
Definition: lsq.hh:610
gem5::o3::LSQ::numFreeEntries
unsigned numFreeEntries(ThreadID tid)
Returns the number of free entries for a specific thread.
gem5::o3::LSQ::SplitDataRequest::name
virtual std::string name() const
Definition: lsq.hh:646
gem5::o3::LSQ::numThreads
ThreadID numThreads
Number of Threads.
Definition: lsq.hh:935
gem5::o3::LSQ::LSQRequest::taskId
void taskId(const uint32_t &v)
Definition: lsq.hh:347
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::o3::LSQ::dumpInsts
void dumpInsts() const
Debugging function to print out all instructions.
Definition: lsq.cc:745
gem5::o3::LSQ::SplitDataRequest::~SplitDataRequest
virtual ~SplitDataRequest()
Definition: lsq.hh:623
gem5::o3::LSQ::LSQRequest::isInTranslation
bool isInTranslation()
Definition: lsq.hh:454
gem5::o3::LSQ::getCount
int getCount()
Returns the number of instructions in all of the queues.
Definition: lsq.cc:454
gem5::o3::LSQ::SplitDataRequest::buildPackets
virtual void buildPackets()
Definition: lsq.cc:1187
gem5::o3::LSQ::writebackStores
void writebackStores()
Attempts to write back stores until all cache ports are used or the interface becomes blocked.
Definition: lsq.cc:263
gem5::o3::LSQ::setActiveThreads
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets the pointer to the list of active threads.
Definition: lsq.cc:128
gem5::o3::LSQ::lqEmpty
bool lqEmpty() const
Returns if all of the LQs are empty.
Definition: lsq.cc:584
gem5::o3::LSQ::LSQRequest::Discarded
@ Discarded
Request discarded.
Definition: lsq.hh:216
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::Flags::set
void set(Type mask)
Set all flag's bits matching the given mask.
Definition: flags.hh:116
gem5::o3::LSQ::_cacheBlocked
bool _cacheBlocked
D-cache is blocked.
Definition: lsq.hh:877
gem5::o3::LSQ::SingleDataRequest::buildPackets
virtual void buildPackets()
Definition: lsq.cc:1155
gem5::o3::LSQ::LSQRequest::install
void install()
Install the request in the LQ/SQ.
Definition: lsq.cc:1069
gem5::o3::LSQ::SplitDataRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq.cc:964
gem5::o3::LSQ::LSQRequest::setState
void setState(const State &newState)
Definition: lsq.hh:236
gem5::Flags::clear
void clear()
Clear all flag's bits.
Definition: flags.hh:102
gem5::o3::LSQ::SplitDataRequest::handleLocalAccess
virtual Cycles handleLocalAccess(gem5::ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
Definition: lsq.cc:1278
gem5::o3::LSQ::DcachePort
DcachePort class for the load/store queue.
Definition: lsq.hh:83
gem5::o3::LSQ::LSQRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)=0
Test if the request accesses a particular cache line.
gem5::Complete
@ Complete
Definition: misc.hh:57
gem5::o3::LSQ::LSQRequest::isMemAccessRequired
bool isMemAccessRequired()
Definition: lsq.hh:487
gem5::o3::LSQ::getStoreHeadSeqNum
InstSeqNum getStoreHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the store queue.
Definition: lsq.cc:330
tlb.hh
gem5::o3::LSQ::LSQRequest::buildPackets
virtual void buildPackets()=0
gem5::o3::LSQ::numLoads
int numLoads()
Returns the total number of loads in the load queue.
Definition: lsq.cc:471
gem5::o3::LSQ::LSQRequest::isPartialFault
bool isPartialFault()
Definition: lsq.hh:481
gem5::o3::LSQ::SplitDataRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Caches may probe into the load-store queue to enforce memory ordering guarantees.
Definition: lsq.cc:1319
gem5::o3::LSQ::LSQRequest::State::PartialFault
@ PartialFault
gem5::o3::LSQ::cachePortAvailable
bool cachePortAvailable(bool is_load) const
Is any store port available to use?
Definition: lsq.cc:196
gem5::o3::LSQ
Definition: lsq.hh:75
gem5::o3::LSQ::LSQRequest::WritebackDone
@ WritebackDone
Definition: lsq.hh:221
gem5::o3::LSQ::LSQRequest::squashed
bool squashed() const override
This function is used by the page table walker to determine if it should translate the a pending requ...
Definition: lsq.cc:1080
gem5::o3::LSQ::LSQRequest::instruction
const DynInstPtr & instruction()
Definition: lsq.hh:332
gem5::o3::LSQ::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt)
Definition: lsq.cc:438
gem5::o3::LSQ::LSQRequest::sendPacketToCache
virtual void sendPacketToCache()=0
gem5::o3::LSQ::LSQRequest::LSQEntryFreed
@ LSQEntryFreed
LSQ resources freed.
Definition: lsq.hh:218
gem5::o3::LSQ::SplitDataRequest::_mainPacket
PacketPtr _mainPacket
Definition: lsq.hh:607
std::vector
STL vector class.
Definition: stl.hh:37
gem5::o3::LSQ::getStoreHead
int getStoreHead(ThreadID tid)
Returns the head index of the store queue.
Definition: lsq.cc:324
gem5::o3::LSQ::LSQRequest::mainPacket
virtual PacketPtr mainPacket()
Definition: lsq.hh:365
gem5::o3::LSQ::SingleDataRequest::name
virtual std::string name() const
Definition: lsq.hh:583
gem5::o3::LSQ::LSQRequest::getVaddr
Addr getVaddr(int idx=0) const
Definition: lsq.hh:359
gem5::PacketDataPtr
uint8_t * PacketDataPtr
Definition: packet.hh:71
gem5::o3::LSQ::SplitDataRequest::sendPacketToCache
virtual void sendPacketToCache()
Definition: lsq.cc:1260
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::o3::LSQ::LSQRequest::needWBToRegister
bool needWBToRegister() const
Definition: lsq.hh:409
gem5::o3::LSQ::name
std::string name() const
Returns the name of the LSQ.
Definition: lsq.cc:122
gem5::o3::LSQ::LSQRequest::Sent
@ Sent
Definition: lsq.hh:209
gem5::o3::LSQ::LSQRequest::~LSQRequest
virtual ~LSQRequest()
Destructor.
Definition: lsq.cc:1096
gem5::o3::LSQ::dcachePort
DcachePort dcachePort
Data port.
Definition: lsq.hh:929
gem5::o3::LSQ::DcachePort::recvTimingSnoopReq
virtual void recvTimingSnoopReq(PacketPtr pkt)
Receive a timing snoop request from the peer.
Definition: lsq.cc:1347
gem5::o3::LSQ::isEmpty
bool isEmpty() const
Returns if the LSQ is empty (both LQ and SQ are empty).
Definition: lsq.cc:578
gem5::o3::LSQ::DcachePort::DcachePort
DcachePort(LSQ *_lsq, CPU *_cpu)
Default constructor.
Definition: lsq.cc:67
gem5::o3::LSQ::activeThreads
std::list< ThreadID > * activeThreads
List of Active Threads in System.
Definition: lsq.hh:915
gem5::o3::LSQ::LSQRequest::contextId
ContextID contextId() const
Definition: lsq.cc:1106
gem5::o3::LSQ::SplitDataRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Definition: lsq.cc:1130
gem5::o3::LSQ::LSQRequest::IsAtomic
@ IsAtomic
True if this is an atomic request.
Definition: lsq.hh:223
gem5::o3::LSQ::SingleDataRequest::sendPacketToCache
virtual void sendPacketToCache()
Definition: lsq.cc:1252
gem5::o3::LSQ::LSQRequest::setVirt
void setVirt(Addr vaddr, unsigned size, Request::Flags flags_, RequestorID requestor_id, Addr pc)
Set up virtual request.
Definition: lsq.hh:338
gem5::o3::LSQ::isStalled
bool isStalled()
Returns if the LSQ is stalled due to a memory operation that must be replayed.
Definition: lsq.cc:670
gem5::o3::LSQ::executeStore
Fault executeStore(const DynInstPtr &inst)
Executes a store.
Definition: lsq.cc:243
gem5::o3::LSQ::LSQRequest::State::Request
@ Request
gem5::o3::LSQ::cacheStorePorts
int cacheStorePorts
The number of cache ports available each cycle (stores only).
Definition: lsq.hh:879
gem5::RefCountingPtr< DynInst >
gem5::o3::LSQ::sqFull
bool sqFull()
Returns if any of the SQs are full.
Definition: lsq.cc:643
gem5::o3::LSQ::resetHtmStartsStops
void resetHtmStartsStops(ThreadID tid)
Definition: lsq.cc:359
gem5::o3::LSQ::LSQRequest::req
RequestPtr req(int idx=0)
Definition: lsq.hh:356
gem5::o3::LSQ::write
Fault write(LSQRequest *request, uint8_t *data, int store_idx)
Executes a store operation, using the store specified at the store index.
Definition: lsq.cc:1423
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::o3::LSQ::violation
bool violation()
Returns whether or not there was a memory ordering violation.
Definition: lsq.cc:287
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::LSQ::completeDataAccess
void completeDataAccess(PacketPtr pkt)
Definition: lsq.cc:393
gem5::o3::LSQ::numHtmStarts
int numHtmStarts(ThreadID tid) const
Definition: lsq.cc:342
gem5::o3::LSQ::SingleDataRequest::SingleDataRequest
SingleDataRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad, const Addr &addr, const uint32_t &size, const Request::Flags &flags_, PacketDataPtr data=nullptr, uint64_t *res=nullptr, AtomicOpFunctorPtr amo_op=nullptr)
Definition: lsq.hh:566
gem5::o3::LSQ::LSQRequest::_size
const uint32_t _size
Definition: lsq.hh:255
gem5::o3::LSQ::numStores
int numStores()
Returns the total number of stores in the store queue.
Definition: lsq.cc:488
gem5::o3::LSQ::LSQRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)=0
gem5::o3::LSQ::LSQRequest::packetReplied
void packetReplied()
Definition: lsq.hh:518
gem5::Flags< FlagsStorage >
gem5::o3::LSQUnit
Class that implements the actual LQ and SQ for each specific thread.
Definition: lsq_unit.hh:89
gem5::o3::LSQ::HtmCmdRequest::HtmCmdRequest
HtmCmdRequest(LSQUnit *port, const DynInstPtr &inst, const Request::Flags &flags_)
Definition: lsq.cc:1363
gem5::o3::LSQ::SQEntries
unsigned SQEntries
Total Size of SQ Entries.
Definition: lsq.hh:920
gem5::o3::LSQ::tick
void tick()
Ticks the LSQ.
Definition: lsq.cc:173
gem5::o3::LSQ::LSQRequest::_inst
const DynInstPtr _inst
Definition: lsq.hh:247
inst_seq.hh
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::LSQ::LSQRequest::packetSent
void packetSent()
Update the status to reflect that a packet was sent.
Definition: lsq.hh:431
gem5::o3::LSQ::LSQRequest::setStateToFault
void setStateToFault()
Definition: lsq.hh:494
gem5::o3::LSQ::SplitDataRequest::numFragments
uint32_t numFragments
Definition: lsq.hh:604
gem5::o3::LSQ::LSQRequest::squashTranslation
void squashTranslation()
Definition: lsq.hh:544
gem5::o3::LSQ::maxSQEntries
unsigned maxSQEntries
Max SQ Size - Used to Enforce Sharing Policies.
Definition: lsq.hh:926
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::o3::LSQ::LSQRequest::isTranslationBlocked
bool isTranslationBlocked()
Definition: lsq.hh:467
gem5::o3::LSQ::LSQRequest::discard
void discard()
The request is discarded (e.g.
Definition: lsq.hh:512
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::LSQ::SplitDataRequest
Definition: lsq.hh:601
gem5::Flags::isSet
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition: flags.hh:83
gem5::o3::LSQ::isDrained
bool isDrained() const
Has the LSQ drained?
Definition: lsq.cc:144
sim_object.hh
gem5::o3::LSQ::LSQRequest::_packets
std::vector< PacketPtr > _packets
Definition: lsq.hh:250
gem5::o3::LSQ::iewStage
IEW * iewStage
The IEW stage pointer.
Definition: lsq.hh:862
gem5::o3::LSQ::HtmCmdRequest::name
virtual std::string name() const
Definition: lsq.hh:598
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::o3::LSQ::LSQRequest::State::Fault
@ Fault
gem5::o3::LSQ::LSQRequest::Delayed
@ Delayed
Definition: lsq.hh:203
gem5::o3::LSQ::LSQRequest::State
State
Definition: lsq.hh:227
gem5::o3::LSQ::LSQRequest::packetNotSent
void packetNotSent()
Update the status to reflect that a packet was not sent.
Definition: lsq.hh:440
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::ArmISA::v
Bitfield< 28 > v
Definition: misc_types.hh:54
gem5::o3::LSQ::LSQRequest::flags
FlagsType flags
Definition: lsq.hh:225
gem5::o3::LSQ::SplitDataRequest::mainReq
virtual RequestPtr mainReq()
Definition: lsq.cc:958
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::o3::LSQ::LSQRequest::packet
PacketPtr packet(int idx=0)
Definition: lsq.hh:362
gem5::o3::LSQ::getLatestHtmUid
uint64_t getLatestHtmUid(ThreadID tid) const
Definition: lsq.cc:366
gem5::o3::LSQ::LSQRequest::State::NotIssued
@ NotIssued
gem5::o3::LSQ::LSQRequest::IsSplit
@ IsSplit
Definition: lsq.hh:204
mmu.hh
gem5::o3::LSQ::LSQRequest::_numOutstandingPackets
uint32_t _numOutstandingPackets
Definition: lsq.hh:258
gem5::o3::LSQ::willWB
bool willWB()
Returns if the LSQ will write back to memory this cycle.
Definition: lsq.cc:723
gem5::o3::LSQ::numFreeLoadEntries
unsigned numFreeLoadEntries()
Returns the number of free load entries.
Definition: lsq.cc:505
port.hh
gem5::o3::LSQ::LSQRequest::_reqs
std::vector< RequestPtr > _reqs
Definition: lsq.hh:251
gem5::o3::LSQ::LSQRequest::Complete
@ Complete
Definition: lsq.hh:211
gem5::o3::LSQ::cachePortBusy
void cachePortBusy(bool is_load)
Another store port is in use.
Definition: lsq.cc:208
gem5::o3::LSQ::HtmCmdRequest::~HtmCmdRequest
virtual ~HtmCmdRequest()
Definition: lsq.hh:594
gem5::o3::LSQ::DcachePort::recvReqRetry
virtual void recvReqRetry()
Handles doing a retry of the previous send.
Definition: lsq.cc:1358
gem5::o3::LSQ::LSQRequest::name
virtual std::string name() const
Definition: lsq.hh:560
gem5::o3::LSQ::LSQRequest::isReleased
bool isReleased()
Test if the LSQRequest has been released, i.e.
Definition: lsq.hh:396
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:457
gem5::o3::LSQ::SplitDataRequest::mainPacket
virtual PacketPtr mainPacket()
Definition: lsq.cc:952
gem5::o3::LSQ::LSQRequest::isDelayed
bool isDelayed()
Definition: lsq.hh:243
gem5::o3::LSQ::setLastRetiredHtmUid
void setLastRetiredHtmUid(ThreadID tid, uint64_t htmUid)
Definition: lsq.cc:375
gem5::o3::LSQ::DcachePort::cpu
CPU * cpu
Definition: lsq.hh:89
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::o3::LSQ::LSQRequest::_flags
const Request::Flags _flags
Definition: lsq.hh:256
dyn_inst_ptr.hh
gem5::o3::LSQ::SingleDataRequest::isCacheBlockHit
virtual bool isCacheBlockHit(Addr blockAddr, Addr cacheBlockMask)
Test if the request accesses a particular cache line.
Definition: lsq.cc:1298
gem5::o3::LSQ::entryAmount
int entryAmount(ThreadID num_threads)
Number of entries needed for the given amount of threads.
gem5::o3::LSQ::getMemDepViolator
DynInstPtr getMemDepViolator(ThreadID tid)
Gets the instruction that caused the memory ordering violation.
Definition: lsq.cc:306
gem5::o3::LSQ::LSQRequest::complete
void complete()
Definition: lsq.hh:555
flags.hh
gem5::o3::LSQ::LSQRequest::TranslationFinished
@ TranslationFinished
True if there are un-replied outbound translations.
Definition: lsq.hh:208
gem5::o3::LSQ::squash
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squash instructions from a thread until the specified sequence number.
Definition: lsq.cc:281
gem5::o3::LSQ::sqEmpty
bool sqEmpty() const
Returns if all of the SQs are empty.
Definition: lsq.cc:600
gem5::o3::LSQ::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: lsq.cc:135
gem5::o3::LSQ::LSQRequest::isSent
bool isSent()
Definition: lsq.hh:475
gem5::o3::LSQ::SingleDataRequest::~SingleDataRequest
virtual ~SingleDataRequest()
Definition: lsq.hh:573
gem5::o3::LSQ::maxLSQAllocation
static uint32_t maxLSQAllocation(SMTQueuePolicy pol, uint32_t entries, uint32_t numThreads, uint32_t SMTThreshold)
Auxiliary function to calculate per-thread max LSQ allocation limit.
Definition: lsq.hh:897
gem5::o3::LSQ::read
Fault read(LSQRequest *request, int load_idx)
Executes a read operation, using the load specified at the load index.
Definition: lsq.cc:1414
gem5::o3::LSQ::SingleDataRequest::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Definition: lsq.cc:1120
gem5::o3::LSQ::recvReqRetry
void recvReqRetry()
Retry the previous send that failed.
Definition: lsq.cc:382
gem5::o3::LSQ::LSQRequest::FlagsType
Flags< FlagsStorage > FlagsType
Definition: lsq.hh:193
gem5::o3::LSQ::SingleDataRequest::handleLocalAccess
virtual Cycles handleLocalAccess(gem5::ThreadContext *thread, PacketPtr pkt)
Memory mapped IPR accesses.
Definition: lsq.cc:1271
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::o3::LSQ::LSQRequest::_port
LSQUnit & _port
Definition: lsq.hh:246
gem5::o3::LSQ::HtmCmdRequest::initiateTranslation
virtual void initiateTranslation()
Definition: lsq.cc:1371
gem5::o3::LSQ::LSQRequest::writebackScheduled
void writebackScheduled()
Definition: lsq.hh:527
gem5::o3::LSQ::insertLoad
void insertLoad(const DynInstPtr &load_inst)
Inserts a load into the LSQ.
Definition: lsq.cc:219
gem5::o3::LSQ::LSQRequest::LSQRequest
LSQRequest(LSQUnit *port, const DynInstPtr &inst, bool isLoad)
Definition: lsq.cc:1032
gem5::o3::LSQ::LSQRequest::lsqUnit
LSQUnit * lsqUnit()
Definition: lsq.hh:262
gem5::o3::LSQ::cpu
CPU * cpu
The CPU pointer.
Definition: lsq.hh:859
gem5::o3::LSQ::hasStoresToWB
bool hasStoresToWB()
Returns whether or not there are any stores to write back to memory.
Definition: lsq.cc:695
std
Overload hash function for BasicBlockRange type.
Definition: types.hh:111
types.hh
gem5::o3::LSQ::getLoadHead
int getLoadHead(ThreadID tid)
Returns the head index of the load queue for a specific thread.
Definition: lsq.cc:312
gem5::o3::LSQ::SplitDataRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
Definition: lsq.cc:883
gem5::o3::LSQ::maxLQEntries
unsigned maxLQEntries
Max LQ Size - Used to Enforce Sharing Policies.
Definition: lsq.hh:923
gem5::o3::LSQ::LSQRequest::markDelayed
void markDelayed() override
Signal that the translation has been delayed due to a hw page table walk.
Definition: lsq.hh:242
gem5::o3::LSQ::getLoadHeadSeqNum
InstSeqNum getLoadHeadSeqNum(ThreadID tid)
Returns the sequence number of the head of the load queue.
Definition: lsq.cc:318
gem5::o3::LSQ::LSQRequest::TranslationSquashed
@ TranslationSquashed
Ownership tracking flags.
Definition: lsq.hh:214
gem5::o3::LSQ::HtmCmdRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
Definition: lsq.cc:1407
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::o3::LSQ::numFreeStoreEntries
unsigned numFreeStoreEntries()
Returns the number of free store entries.
Definition: lsq.cc:522
gem5::o3::LSQ::SplitDataRequest::_mainReq
RequestPtr _mainReq
Definition: lsq.hh:606
gem5::o3::LSQ::LSQRequest::isAnyOutstandingRequest
bool isAnyOutstandingRequest()
Test if there is any in-flight translation or mem access request.
Definition: lsq.hh:382
gem5::o3::LSQ::LSQRequest::initiateTranslation
virtual void initiateTranslation()=0
gem5::o3::LSQ::usedStorePorts
int usedStorePorts
The number of used cache ports in this cycle by stores.
Definition: lsq.hh:881
gem5::o3::LSQ::LSQ
LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params)
Constructs an LSQ with the given parameters.
Definition: lsq.cc:71
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::o3::LSQ::LSQRequest::FlagsStorage
uint32_t FlagsStorage
Definition: lsq.hh:192
gem5::o3::LSQ::LSQRequest::handleLocalAccess
virtual Cycles handleLocalAccess(gem5::ThreadContext *thread, PacketPtr pkt)=0
Memory mapped IPR accesses.
gem5::MipsISA::r
r
Definition: pra_constants.hh:98
gem5::o3::LSQ::SingleDataRequest::finish
virtual void finish(const Fault &fault, const RequestPtr &req, gem5::ThreadContext *tc, BaseMMU::Mode mode)
Definition: lsq.cc:851
gem5::o3::LSQ::LSQRequest::taskId
uint32_t taskId() const
Definition: lsq.hh:354
gem5::o3::LSQ::HtmCmdRequest
Definition: lsq.hh:589
gem5::o3::LSQ::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable)
Definition: lsq.cc:764
gem5::o3::LSQ::LSQRequest::numTranslatedFragments
uint32_t numTranslatedFragments
Definition: lsq.hh:238
gem5::o3::LSQ::LSQRequest::writebackDone
void writebackDone()
Definition: lsq.hh:534
gem5::o3::LSQ::DcachePort::recvTimingResp
virtual bool recvTimingResp(PacketPtr pkt)
Timing version of receive.
Definition: lsq.cc:1341
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::o3::LSQ::LSQRequest::IsLoad
@ IsLoad
Definition: lsq.hh:197
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:873
gem5::o3::LSQ::LSQRequest::isLoad
bool isLoad() const
Definition: lsq.hh:270
gem5::o3::LSQ::LSQRequest::WritebackScheduled
@ WritebackScheduled
Store written back.
Definition: lsq.hh:220
gem5::o3::LSQ::takeOverFrom
void takeOverFrom()
Takes over execution from another CPU's thread.
Definition: lsq.cc:162
gem5::o3::LSQ::commitStores
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
Commits stores up until the given sequence number for a specific thread.
Definition: lsq.cc:257
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
std::list< ThreadID >
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::o3::LSQ::LSQRequest::addReq
void addReq(Addr addr, unsigned size, const std::vector< bool > &byte_enable)
Helper function used to add a (sub)request, given its address addr, size size and byte-enable mask by...
Definition: lsq.cc:1083
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::o3::LSQ::LSQRequest::Flag
Flag
Definition: lsq.hh:195
gem5::o3::LSQ::lqFull
bool lqFull()
Returns if any of the LQs are full.
Definition: lsq.cc:616
gem5::o3::LSQ::LSQRequest::TranslationStarted
@ TranslationStarted
True if any translation has been sent to TLB.
Definition: lsq.hh:206
gem5::o3::LSQ::numHtmStops
int numHtmStops(ThreadID tid) const
Definition: lsq.cc:350
gem5::o3::LSQ::LSQRequest::setContext
void setContext(const ContextID &context_id)
Convenience getters/setters.
Definition: lsq.hh:327
gem5::o3::LSQ::LSQRequest::mainReq
virtual RequestPtr mainReq()
Definition: lsq.hh:372
gem5::o3::LSQ::LSQRequest::isComplete
bool isComplete()
Definition: lsq.hh:448
gem5::o3::LSQ::LSQRequest::sendFragmentToTranslation
void sendFragmentToTranslation(int i)
Definition: lsq.cc:1112
gem5::o3::LSQ::LSQRequest::_fault
std::vector< Fault > _fault
Definition: lsq.hh:252
gem5::o3::LSQ::executeLoad
Fault executeLoad(const DynInstPtr &inst)
Executes a load.
Definition: lsq.cc:235
gem5::o3::LSQ::LSQRequest::numInTranslationFragments
uint32_t numInTranslationFragments
Definition: lsq.hh:239
gem5::o3::LSQ::usedLoadPorts
int usedLoadPorts
The number of used cache ports in this cycle by loads.
Definition: lsq.hh:885
gem5::o3::LSQ::thread
std::vector< LSQUnit > thread
The LSQ units for individual threads.
Definition: lsq.hh:932
gem5::o3::LSQ::isFull
bool isFull()
Returns if the LSQ is full (either LQ or SQ is full).
Definition: lsq.cc:551
gem5::o3::LSQ::LSQRequest::isSplit
bool isSplit() const
Definition: lsq.hh:403
gem5::o3::LSQ::LSQRequest::_state
State _state
Definition: lsq.hh:235
gem5::o3::LSQ::SplitDataRequest::numReceivedPackets
uint32_t numReceivedPackets
Definition: lsq.hh:605
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::LSQ::SingleDataRequest
Definition: lsq.hh:563
gem5::o3::LSQ::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Handles writing back and completing the load or store that has returned from memory.
Definition: lsq.cc:401
gem5::o3::LSQ::LSQRequest::WriteBackToRegister
@ WriteBackToRegister
True if this request needs to writeBack to register.
Definition: lsq.hh:202
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::LSQ::cacheLoadPorts
int cacheLoadPorts
The number of cache ports available each cycle (loads only).
Definition: lsq.hh:883
gem5::o3::LSQ::LSQRequest::freeLSQEntry
void freeLSQEntry()
The LSQ entry is cleared.
Definition: lsq.hh:503

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