gem5  v21.1.0.2
integer.cc
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1 /*
2  * Copyright (c) 2009 The University of Edinburgh
3  * Copyright (c) 2021 IBM Corporation
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5  *
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29 
31 
32 namespace gem5
33 {
34 
35 using namespace PowerISA;
36 
37 std::string
39 {
40  std::stringstream ss;
41  bool printDest = true;
42  bool printSrcs = true;
43  bool printSecondSrc = true;
44 
45  // Generate the correct mnemonic
46  std::string myMnemonic(mnemonic);
47 
48  // Special cases
49  if (myMnemonic == "mtcrf" ||
50  myMnemonic == "mtxer" ||
51  myMnemonic == "mtlr" ||
52  myMnemonic == "mtctr" ||
53  myMnemonic == "mttar" ||
54  myMnemonic == "mttb" ||
55  myMnemonic == "mttbu") {
56  printDest = false;
57  } else if (myMnemonic == "mfcr" ||
58  myMnemonic == "mfxer" ||
59  myMnemonic == "mflr" ||
60  myMnemonic == "mfctr" ||
61  myMnemonic == "mftar" ||
62  myMnemonic == "mftb" ||
63  myMnemonic == "mftbu") {
64  printSrcs = false;
65  }
66 
67  // Additional characters depending on isa bits being set
68  if (oe)
69  myMnemonic = myMnemonic + "o";
70  if (rc)
71  myMnemonic = myMnemonic + ".";
72  ccprintf(ss, "%-10s ", myMnemonic);
73 
74  // Print the first destination only
75  if (_numDestRegs > 0 && printDest)
76  printReg(ss, destRegIdx(0));
77 
78  // Print the (possibly) two source registers
79  if (_numSrcRegs > 0 && printSrcs) {
80  if (_numDestRegs > 0 && printDest)
81  ss << ", ";
82  printReg(ss, srcRegIdx(0));
83  if (_numSrcRegs > 1 && printSecondSrc) {
84  ss << ", ";
85  printReg(ss, srcRegIdx(1));
86  }
87  }
88 
89  return ss.str();
90 }
91 
92 
93 std::string
95 {
96  std::stringstream ss;
97 
98  ccprintf(ss, "%-10s ", mnemonic);
99 
100  // Print the first destination only
101  if (_numDestRegs > 0)
102  printReg(ss, destRegIdx(0));
103 
104  // Print the source register
105  if (_numSrcRegs > 0) {
106  if (_numDestRegs > 0)
107  ss << ", ";
108  printReg(ss, srcRegIdx(0));
109  }
110 
111  // Print the immediate value last
112  ss << ", " << (int32_t)si;
113 
114  return ss.str();
115 }
116 
117 
118 std::string
120  Addr pc, const Loader::SymbolTable *symtab) const
121 {
122  std::stringstream ss;
123  bool printSecondSrc = true;
124  bool printThirdSrc = false;
125 
126  // Generate the correct mnemonic
127  std::string myMnemonic(mnemonic);
128 
129  // Special cases
130  if (myMnemonic == "addme" ||
131  myMnemonic == "addze" ||
132  myMnemonic == "subfme" ||
133  myMnemonic == "subfze" ||
134  myMnemonic == "neg") {
135  printSecondSrc = false;
136  } else if (myMnemonic == "maddhd" ||
137  myMnemonic == "maddhdu" ||
138  myMnemonic == "maddld") {
139  printThirdSrc = true;
140  }
141 
142  // Additional characters depending on isa bits being set
143  if (oe)
144  myMnemonic = myMnemonic + "o";
145  if (rc)
146  myMnemonic = myMnemonic + ".";
147  ccprintf(ss, "%-10s ", myMnemonic);
148 
149  // Print the first destination only
150  if (_numDestRegs > 0)
151  printReg(ss, destRegIdx(0));
152 
153  // Print the first source register
154  if (_numSrcRegs > 0) {
155  if (_numDestRegs > 0)
156  ss << ", ";
157  printReg(ss, srcRegIdx(0));
158 
159  // Print the second source register
160  if (_numSrcRegs > 1 && printSecondSrc) {
161  ss << ", ";
162  printReg(ss, srcRegIdx(1));
163 
164  // Print the third source register
165  if (_numSrcRegs > 2 && printThirdSrc) {
166  ss << ", ";
167  printReg(ss, srcRegIdx(2));
168  }
169  }
170  }
171 
172  return ss.str();
173 }
174 
175 
176 std::string
178  Addr pc, const Loader::SymbolTable *symtab) const
179 {
180  std::stringstream ss;
181  bool negateImm = false;
182 
183  // Generate the correct mnemonic
184  std::string myMnemonic(mnemonic);
185 
186  // Special cases
187  if (myMnemonic == "addi") {
188  if (_numSrcRegs == 0) {
189  myMnemonic = "li";
190  } else if (si < 0) {
191  myMnemonic = "subi";
192  negateImm = true;
193  }
194  } else if (myMnemonic == "addis") {
195  if (_numSrcRegs == 0) {
196  myMnemonic = "lis";
197  } else if (si < 0) {
198  myMnemonic = "subis";
199  negateImm = true;
200  }
201  } else if (myMnemonic == "addic" && si < 0) {
202  myMnemonic = "subic";
203  negateImm = true;
204  } else if (myMnemonic == "addic_") {
205  if (si < 0) {
206  myMnemonic = "subic.";
207  negateImm = true;
208  } else {
209  myMnemonic = "addic.";
210  }
211  }
212 
213  ccprintf(ss, "%-10s ", myMnemonic);
214 
215  // Print the first destination only
216  if (_numDestRegs > 0)
217  printReg(ss, destRegIdx(0));
218 
219  // Print the source register
220  if (_numSrcRegs > 0) {
221  if (_numDestRegs > 0)
222  ss << ", ";
223  printReg(ss, srcRegIdx(0));
224  }
225 
226  // Print the immediate value
227  if (negateImm)
228  ss << ", " << -si;
229  else
230  ss << ", " << si;
231 
232  return ss.str();
233 }
234 
235 
236 std::string
238  Addr pc, const Loader::SymbolTable *symtab) const
239 {
240  std::stringstream ss;
241  bool printSrcs = true;
242  bool printDisp = true;
243  bool negateDisp = false;
244 
245  // Generate the correct mnemonic
246  std::string myMnemonic(mnemonic);
247 
248  // Special cases
249  if (myMnemonic == "addpcis") {
250  printSrcs = false;
251  if (d == 0) {
252  myMnemonic = "lnia";
253  printDisp = false;
254  } else if (d < 0) {
255  myMnemonic = "subpcis";
256  negateDisp = true;
257  }
258  }
259 
260  ccprintf(ss, "%-10s ", myMnemonic);
261 
262  // Print the first destination only
263  if (_numDestRegs > 0)
264  printReg(ss, destRegIdx(0));
265 
266  // Print the source register
267  if (_numSrcRegs > 0 && printSrcs) {
268  if (_numDestRegs > 0)
269  ss << ", ";
270  printReg(ss, srcRegIdx(0));
271  }
272 
273  // Print the displacement
274  if (printDisp)
275  ss << ", " << (negateDisp ? -d : d);
276 
277  return ss.str();
278 }
279 
280 
281 std::string
283  Addr pc, const Loader::SymbolTable *symtab) const
284 {
285  std::stringstream ss;
286  bool printSecondSrc = true;
287 
288  // Generate the correct mnemonic
289  std::string myMnemonic(mnemonic);
290 
291  // Special cases
292  if (myMnemonic == "or" && srcRegIdx(0) == srcRegIdx(1)) {
293  myMnemonic = "mr";
294  printSecondSrc = false;
295  } else if (myMnemonic == "extsb" ||
296  myMnemonic == "extsh" ||
297  myMnemonic == "extsw" ||
298  myMnemonic == "cntlzw" ||
299  myMnemonic == "cntlzd" ||
300  myMnemonic == "cnttzw" ||
301  myMnemonic == "cnttzd") {
302  printSecondSrc = false;
303  }
304 
305  // Additional characters depending on isa bits being set
306  if (rc)
307  myMnemonic = myMnemonic + ".";
308  ccprintf(ss, "%-10s ", myMnemonic);
309 
310  // Print the first destination only
311  if (_numDestRegs > 0)
312  printReg(ss, destRegIdx(0));
313 
314  // Print the first source register
315  if (_numSrcRegs > 0) {
316  if (_numDestRegs > 0)
317  ss << ", ";
318  printReg(ss, srcRegIdx(0));
319 
320  // Print the second source register
321  if (printSecondSrc) {
322 
323  // If the instruction updates the CR, the destination register
324  // Ra is read and thus, it becomes the second source register
325  // due to its higher precedence over Rb. In this case, it must
326  // be skipped.
327  if (rc) {
328  if (_numSrcRegs > 2) {
329  ss << ", ";
330  printReg(ss, srcRegIdx(2));
331  }
332  } else {
333  if (_numSrcRegs > 1) {
334  ss << ", ";
335  printReg(ss, srcRegIdx(1));
336  }
337  }
338  }
339  }
340 
341  return ss.str();
342 }
343 
344 
345 std::string
347  Addr pc, const Loader::SymbolTable *symtab) const
348 {
349  std::stringstream ss;
350  bool printRegs = true;
351 
352  // Generate the correct mnemonic
353  std::string myMnemonic(mnemonic);
354 
355  // Special cases
356  if (myMnemonic == "ori" &&
357  destRegIdx(0).index() == 0 && srcRegIdx(0).index() == 0) {
358  myMnemonic = "nop";
359  printRegs = false;
360  } else if (myMnemonic == "xori" &&
361  destRegIdx(0).index() == 0 && srcRegIdx(0).index() == 0) {
362  myMnemonic = "xnop";
363  printRegs = false;
364  } else if (myMnemonic == "andi_") {
365  myMnemonic = "andi.";
366  } else if (myMnemonic == "andis_") {
367  myMnemonic = "andis.";
368  }
369 
370  ccprintf(ss, "%-10s ", myMnemonic);
371 
372  if (printRegs) {
373 
374  // Print the first destination only
375  if (_numDestRegs > 0)
376  printReg(ss, destRegIdx(0));
377 
378  // Print the source register
379  if (_numSrcRegs > 0) {
380  if (_numDestRegs > 0)
381  ss << ", ";
382  printReg(ss, srcRegIdx(0));
383  }
384 
385  // Print the immediate value
386  ss << ", " << ui;
387  }
388 
389  return ss.str();
390 }
391 
392 
393 std::string
395  Addr pc, const Loader::SymbolTable *symtab) const
396 {
397  std::stringstream ss;
398  bool printFieldPrefix = false;
399  bool printLength = true;
400 
401  // Generate the correct mnemonic
402  std::string myMnemonic(mnemonic);
403 
404  // Special cases
405  if (myMnemonic == "cmp" ||
406  myMnemonic == "cmpl") {
407  myMnemonic += l ? "d" : "w";
408  printFieldPrefix = true;
409  printLength = false;
410  }
411 
412  ccprintf(ss, "%-10s ", myMnemonic);
413 
414  // Print the first destination only
415  if (printFieldPrefix) {
416  if (bf > 0)
417  ss << "cr" << (int) bf;
418  } else {
419  ss << (int) bf;
420  }
421 
422  // Print the length
423  if (printLength) {
424  if (!printFieldPrefix || bf > 0)
425  ss << ", ";
426  ss << (int) l;
427  }
428 
429  // Print the first source register
430  if (_numSrcRegs > 0) {
431  if (!printFieldPrefix || bf > 0 || printLength)
432  ss << ", ";
433  printReg(ss, srcRegIdx(0));
434 
435  // Print the second source register
436  if (_numSrcRegs > 1) {
437  ss << ", ";
438  printReg(ss, srcRegIdx(1));
439  }
440  }
441 
442  return ss.str();
443 }
444 
445 
446 std::string
448  Addr pc, const Loader::SymbolTable *symtab) const
449 {
450  std::stringstream ss;
451  bool printFieldPrefix = false;
452  bool printLength = true;
453 
454  // Generate the correct mnemonic
455  std::string myMnemonic(mnemonic);
456 
457  // Special cases
458  if (myMnemonic == "cmpi") {
459  myMnemonic = l ? "cmpdi" : "cmpwi";
460  printFieldPrefix = true;
461  printLength = false;
462  }
463 
464  ccprintf(ss, "%-10s ", myMnemonic);
465 
466  // Print the first destination only
467  if (printFieldPrefix) {
468  if (bf > 0)
469  ss << "cr" << (int) bf;
470  } else {
471  ss << (int) bf;
472  }
473 
474  // Print the length
475  if (printLength) {
476  if (!printFieldPrefix || bf > 0)
477  ss << ", ";
478  ss << (int) l;
479  }
480 
481  // Print the first source register
482  if (_numSrcRegs > 0) {
483  if (!printFieldPrefix || bf > 0 || printLength)
484  ss << ", ";
485  printReg(ss, srcRegIdx(0));
486  }
487 
488  // Print the immediate value
489  ss << ", " << si;
490 
491  return ss.str();
492 }
493 
494 
495 std::string
497  Addr pc, const Loader::SymbolTable *symtab) const
498 {
499  std::stringstream ss;
500  bool printFieldPrefix = false;
501  bool printLength = true;
502 
503  // Generate the correct mnemonic
504  std::string myMnemonic(mnemonic);
505 
506  // Special cases
507  if (myMnemonic == "cmpli") {
508  myMnemonic = l ? "cmpldi" : "cmplwi";
509  printFieldPrefix = true;
510  printLength = false;
511  }
512 
513  ccprintf(ss, "%-10s ", myMnemonic);
514 
515  // Print the first destination only
516  if (printFieldPrefix) {
517  if (bf > 0)
518  ss << "cr" << (int) bf;
519  } else {
520  ss << (int) bf;
521  }
522 
523  // Print the length
524  if (printLength) {
525  if (!printFieldPrefix || bf > 0)
526  ss << ", ";
527  ss << (int) l;
528  }
529 
530  // Print the first source register
531  if (_numSrcRegs > 0) {
532  if (!printFieldPrefix || bf > 0 || printLength)
533  ss << ", ";
534  printReg(ss, srcRegIdx(0));
535  }
536 
537  // Print the immediate value
538  ss << ", " << ui;
539 
540  return ss.str();
541 }
542 
543 
544 std::string
546  Addr pc, const loader::SymbolTable *symtab) const
547 {
548  std::stringstream ss;
549  bool printSecondSrc = true;
550  bool printShift = false;
551 
552  // Generate the correct mnemonic
553  std::string myMnemonic(mnemonic);
554 
555  // Special cases
556  if (myMnemonic == "srawi") {
557  printSecondSrc = false;
558  printShift = true;
559  }
560 
561  // Additional characters depending on isa bits being set
562  if (rc)
563  myMnemonic = myMnemonic + ".";
564  ccprintf(ss, "%-10s ", myMnemonic);
565 
566  // Print the first destination only
567  if (_numDestRegs > 0)
568  printReg(ss, destRegIdx(0));
569 
570  // Print the first source register
571  if (_numSrcRegs > 0) {
572  if (_numDestRegs > 0)
573  ss << ", ";
574  printReg(ss, srcRegIdx(0));
575 
576  // Print the second source register
577  if (printSecondSrc) {
578 
579  // If the instruction updates the CR, the destination register
580  // Ra is read and thus, it becomes the second source register
581  // due to its higher precedence over Rb. In this case, it must
582  // be skipped.
583  if (rc) {
584  if (_numSrcRegs > 2) {
585  ss << ", ";
586  printReg(ss, srcRegIdx(2));
587  }
588  } else {
589  if (_numSrcRegs > 1) {
590  ss << ", ";
591  printReg(ss, srcRegIdx(1));
592  }
593  }
594  }
595  }
596 
597  // Print the shift value
598  if (printShift)
599  ss << ", " << (int) sh;
600 
601  return ss.str();
602 }
603 
604 
605 std::string
607  Addr pc, const Loader::SymbolTable *symtab) const
608 {
609  std::stringstream ss;
610  bool printSecondSrc = true;
611  bool printShift = false;
612 
613  // Generate the correct mnemonic
614  std::string myMnemonic(mnemonic);
615 
616  // Special cases
617  if (myMnemonic == "sradi" ||
618  myMnemonic == "extswsli") {
619  printSecondSrc = false;
620  printShift = true;
621  }
622 
623  // Additional characters depending on isa bits being set
624  if (rc)
625  myMnemonic = myMnemonic + ".";
626  ccprintf(ss, "%-10s ", myMnemonic);
627 
628  // Print the first destination only
629  if (_numDestRegs > 0)
630  printReg(ss, destRegIdx(0));
631 
632  // Print the first source register
633  if (_numSrcRegs > 0) {
634  if (_numDestRegs > 0)
635  ss << ", ";
636  printReg(ss, srcRegIdx(0));
637 
638  // Print the second source register
639  if (printSecondSrc) {
640 
641  // If the instruction updates the CR, the destination register
642  // Ra is read and thus, it becomes the second source register
643  // due to its higher precedence over Rb. In this case, it must
644  // be skipped.
645  if (rc) {
646  if (_numSrcRegs > 2) {
647  ss << ", ";
648  printReg(ss, srcRegIdx(2));
649  }
650  } else {
651  if (_numSrcRegs > 1) {
652  ss << ", ";
653  printReg(ss, srcRegIdx(1));
654  }
655  }
656  }
657  }
658 
659  // Print the shift value
660  if (printShift)
661  ss << ", " << (int) sh;
662 
663  return ss.str();
664 }
665 
666 
667 std::string
669  Addr pc, const loader::SymbolTable *symtab) const
670 {
671  std::stringstream ss;
672  bool printSecondSrc = true;
673  bool printShift = true;
674  bool printMaskBeg = true;
675  bool printMaskEnd = true;
676 
677  // Generate the correct mnemonic
678  std::string myMnemonic(mnemonic);
679 
680  // Special cases
681  if (myMnemonic == "rlwinm") {
682  if (mb == 0 && me == 31) {
683  myMnemonic = "rotlwi";
684  printMaskBeg = false;
685  printMaskEnd = false;
686  } else if (sh == 0 && me == 31) {
687  myMnemonic = "clrlwi";
688  printShift = false;
689  printMaskEnd = false;
690  }
691  printSecondSrc = false;
692  } else if (myMnemonic == "rlwnm") {
693  if (mb == 0 && me == 31) {
694  myMnemonic = "rotlw";
695  printMaskBeg = false;
696  printMaskEnd = false;
697  }
698  printShift = false;
699  } else if (myMnemonic == "rlwimi") {
700  printSecondSrc = false;
701  }
702 
703  // Additional characters depending on isa bits being set
704  if (rc)
705  myMnemonic = myMnemonic + ".";
706  ccprintf(ss, "%-10s ", myMnemonic);
707 
708  // Print the first destination only
709  if (_numDestRegs > 0)
710  printReg(ss, destRegIdx(0));
711 
712  // Print the first source register
713  if (_numSrcRegs > 0) {
714  if (_numDestRegs > 0)
715  ss << ", ";
716  printReg(ss, srcRegIdx(0));
717 
718  // Print the second source register
719  if (printSecondSrc) {
720 
721  // If the instruction updates the CR, the destination register
722  // Ra is read and thus, it becomes the second source register
723  // due to its higher precedence over Rb. In this case, it must
724  // be skipped.
725  if (rc) {
726  if (_numSrcRegs > 2) {
727  ss << ", ";
728  printReg(ss, srcRegIdx(2));
729  }
730  } else {
731  if (_numSrcRegs > 1) {
732  ss << ", ";
733  printReg(ss, srcRegIdx(1));
734  }
735  }
736  }
737  }
738 
739  // Print the shift value
740  if (printShift)
741  ss << ", " << (int) sh;
742 
743  // Print the mask bounds
744  if (printMaskBeg)
745  ss << ", " << (int) mb;
746  if (printMaskEnd)
747  ss << ", " << (int) me;
748 
749  return ss.str();
750 }
751 
752 std::string
754  Addr pc, const Loader::SymbolTable *symtab) const
755 {
756  std::stringstream ss;
757  bool printSecondSrc = false;
758  bool printShift = true;
759  bool printMaskBeg = true;
760 
761  // Generate the correct mnemonic
762  std::string myMnemonic(mnemonic);
763 
764  // Special cases
765  if (myMnemonic == "rldicl") {
766  if (mb == 0) {
767  myMnemonic = "rotldi";
768  printMaskBeg = false;
769  } else if (sh == 0) {
770  myMnemonic = "clrldi";
771  printShift = false;
772  }
773  } else if (myMnemonic == "rldcl") {
774  if (mb == 0) {
775  myMnemonic = "rotld";
776  printMaskBeg = false;
777  }
778  printSecondSrc = true;
779  printShift = false;
780  } else if (myMnemonic == "rldcr") {
781  printSecondSrc = true;
782  printShift = false;
783  }
784 
785  // Additional characters depending on isa bits being set
786  if (rc)
787  myMnemonic = myMnemonic + ".";
788  ccprintf(ss, "%-10s ", myMnemonic);
789 
790  // Print the first destination only
791  if (_numDestRegs > 0)
792  printReg(ss, destRegIdx(0));
793 
794  // Print the first source register
795  if (_numSrcRegs > 0) {
796  if (_numDestRegs > 0)
797  ss << ", ";
798  printReg(ss, srcRegIdx(0));
799 
800  // Print the second source register
801  if (printSecondSrc) {
802 
803  // If the instruction updates the CR, the destination register
804  // Ra is read and thus, it becomes the second source register
805  // due to its higher precedence over Rb. In this case, it must
806  // be skipped.
807  if (rc) {
808  if (_numSrcRegs > 2) {
809  ss << ", ";
810  printReg(ss, srcRegIdx(2));
811  }
812  } else {
813  if (_numSrcRegs > 1) {
814  ss << ", ";
815  printReg(ss, srcRegIdx(1));
816  }
817  }
818  }
819  }
820 
821  // Print the shift amount
822  if (printShift)
823  ss << ", " << (int) sh;
824 
825  // Print the mask bound
826  if (printMaskBeg)
827  ss << ", " << (int) mb;
828 
829  return ss.str();
830 }
831 
832 
833 std::string
835  Addr pc, const Loader::SymbolTable *symtab) const
836 {
837  std::string ext;
838  std::stringstream ss;
839  bool printSrcs = true;
840  bool printCond = false;
841 
842  // Generate the correct mnemonic
843  std::string myMnemonic(mnemonic);
844 
845  // Special cases
846  if (myMnemonic == "tw" &&
847  (srcRegIdx(0).index() == 0) && (srcRegIdx(1).index() == 0)) {
848  myMnemonic = "trap";
849  printSrcs = false;
850  } else {
851  ext = suffix();
852  if (!ext.empty() &&
853  (myMnemonic == "tw" || myMnemonic == "td")) {
854  myMnemonic += ext;
855  } else {
856  printCond = true;
857  }
858  }
859 
860  ccprintf(ss, "%-10s ", myMnemonic);
861 
862  // Print the trap condition
863  if (printCond)
864  ss << (int) to;
865 
866  // Print the source registers
867  if (printSrcs) {
868  if (_numSrcRegs > 0) {
869  if (printCond)
870  ss << ", ";
871  printReg(ss, srcRegIdx(0));
872  }
873 
874  if (_numSrcRegs > 1) {
875  ss << ", ";
876  printReg(ss, srcRegIdx(1));
877  }
878  }
879 
880  return ss.str();
881 }
882 
883 
884 std::string
886  Addr pc, const Loader::SymbolTable *symtab) const
887 {
888  std::string ext;
889  std::stringstream ss;
890  bool printCond = false;
891 
892  // Generate the correct mnemonic
893  std::string myMnemonic(mnemonic);
894 
895  // Special cases
896  ext = suffix();
897  if (!ext.empty()) {
898  if (myMnemonic == "twi") {
899  myMnemonic = "tw" + ext + "i";
900  } else if (myMnemonic == "tdi") {
901  myMnemonic = "td" + ext + "i";
902  } else {
903  printCond = true;
904  }
905  } else {
906  printCond = true;
907  }
908 
909  ccprintf(ss, "%-10s ", myMnemonic);
910 
911  // Print the trap condition
912  if (printCond)
913  ss << (int) to;
914 
915  // Print the source registers
916  if (_numSrcRegs > 0) {
917  if (printCond)
918  ss << ", ";
919  printReg(ss, srcRegIdx(0));
920  }
921 
922  // Print the immediate value
923  ss << ", " << si;
924 
925  return ss.str();
926 }
927 
928 } // namespace gem5
gem5::PowerISA::IntRotateOp::mb
uint8_t mb
Definition: integer.hh:638
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::PowerISA::IntShiftOp::sh
uint8_t sh
Definition: integer.hh:593
gem5::PowerISA::IntConcatRotateOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:753
gem5::PowerISA::PowerStaticInst::printReg
void printReg(std::ostream &os, RegId reg) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:40
integer.hh
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::PowerISA::IntImmArithOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:177
gem5::PowerISA::IntTrapOp::to
uint8_t to
Definition: integer.hh:727
gem5::PowerISA::IntArithOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:119
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::PowerISA::IntImmCompLogicOp::ui
uint32_t ui
Definition: integer.hh:464
gem5::PowerISA::IntImmCompOp::si
int32_t si
Definition: integer.hh:443
gem5::PowerISA::IntConcatShiftOp::sh
uint8_t sh
Definition: integer.hh:615
gem5::PowerISA::IntCompOp::bf
uint8_t bf
Definition: integer.hh:421
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::PowerISA::IntImmLogicOp::ui
uint32_t ui
Definition: integer.hh:571
gem5::PowerISA::IntCompOp::l
bool l
Definition: integer.hh:420
gem5::PowerISA::IntDispArithOp::d
int64_t d
Definition: integer.hh:399
gem5::PowerISA::IntTrapOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:834
gem5::PowerISA::IntImmTrapOp::si
int32_t si
Definition: integer.hh:783
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::PowerISA::IntImmCompLogicOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:496
gem5::ArmISA::ext
Bitfield< 12 > ext
Definition: misc_types.hh:427
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::PowerISA::IntRotateOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: integer.cc:668
gem5::PowerISA::IntConcatRotateOp::mb
uint8_t mb
Definition: integer.hh:686
gem5::PowerISA::IntImmCompOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:447
gem5::PowerISA::IntRotateOp::me
uint8_t me
Definition: integer.hh:639
gem5::PowerISA::IntConcatShiftOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:606
gem5::PowerISA::IntImmOp::si
int32_t si
Definition: integer.hh:112
gem5::PowerISA::IntOp::rc
bool rc
Definition: integer.hh:58
gem5::StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:112
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::PowerISA::IntCompOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:394
gem5::PowerISA::IntLogicOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:282
gem5::PowerISA::IntImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: integer.cc:94
gem5::PowerISA::IntShiftOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: integer.cc:545
gem5::PowerISA::IntTrapOp::suffix
std::string suffix() const
Definition: integer.hh:751
gem5::PowerISA::IntImmArithOp::si
int32_t si
Definition: integer.hh:378
gem5::PowerISA::IntOp::oe
bool oe
Definition: integer.hh:59
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:109
gem5::PowerISA::IntDispArithOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:237
gem5::PowerISA::IntOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: integer.cc:38
gem5::PowerISA::IntImmLogicOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:346
gem5::PowerISA::IntImmTrapOp::generateDisassembly
std::string generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const override
Definition: integer.cc:885

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