gem5  v21.1.0.2
static_inst.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2009 The University of Edinburgh
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
31 
32 #include "cpu/reg_class.hh"
33 
34 namespace gem5
35 {
36 
37 using namespace PowerISA;
38 
39 void
40 PowerStaticInst::printReg(std::ostream &os, RegId reg) const
41 {
42  switch (reg.classValue()) {
43  case IntRegClass:
44  ccprintf(os, "r%d", reg.index());
45  break;
46  case FloatRegClass:
47  ccprintf(os, "f%d", reg.index());
48  break;
49  case MiscRegClass:
50  switch (reg.index()) {
51  case 0: ccprintf(os, "cr"); break;
52  case 1: ccprintf(os, "xer"); break;
53  case 2: ccprintf(os, "lr"); break;
54  case 3: ccprintf(os, "ctr"); break;
55  default: ccprintf(os, "unknown_reg");
56  break;
57  }
58  break;
59  default:
60  panic("printReg: Unrecognized register class.");
61  }
62 }
63 
64 std::string
66  Addr pc, const loader::SymbolTable *symtab) const
67 {
68  std::stringstream ss;
69 
70  ccprintf(ss, "%-10s ", mnemonic);
71 
72  return ss.str();
73 }
74 
75 } // namespace gem5
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::PowerISA::PowerStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:65
gem5::PowerISA::PowerStaticInst::printReg
void printReg(std::ostream &os, RegId reg) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:40
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:65
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
reg_class.hh
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
static_inst.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

Generated on Tue Sep 21 2021 12:24:35 for gem5 by doxygen 1.8.17