gem5  v21.1.0.2
priv.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2006-2007 The Regents of The University of Michigan
3  * All rights reserved
4  * Copyright 2017 Google Inc.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __ARCH_SPARC_INSTS_PRIV_HH__
31 #define __ARCH_SPARC_INSTS_PRIV_HH__
32 
34 
35 namespace gem5
36 {
37 
38 namespace SparcISA
39 {
40 
44 class Priv : public SparcStaticInst
45 {
46  protected:
48  std::string generateDisassembly(
49  Addr pc, const loader::SymbolTable *symtab) const override;
50 };
51 
52 class PrivReg : public Priv
53 {
54  protected:
55  PrivReg(const char *mnem, ExtMachInst _machInst,
56  OpClass __opClass, char const * _regName) :
57  Priv(mnem, _machInst, __opClass), regName(_regName)
58  {}
59 
60  char const *regName;
61 };
62 
63 // This class is for instructions that explicitly read control
64 // registers. It provides a special generateDisassembly function.
65 class RdPriv : public PrivReg
66 {
67  protected:
68  using PrivReg::PrivReg;
69  std::string generateDisassembly(
70  Addr pc, const loader::SymbolTable *symtab) const override;
71 };
72 
73 // This class is for instructions that explicitly write control
74 // registers. It provides a special generateDisassembly function.
75 class WrPriv : public PrivReg
76 {
77  protected:
78  using PrivReg::PrivReg;
79  std::string generateDisassembly(
80  Addr pc, const loader::SymbolTable *symtab) const override;
81 };
82 
86 class PrivImm : public Priv
87 {
88  protected:
89  // Constructor
90  PrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
91  Priv(mnem, _machInst, __opClass), imm(bits(_machInst, 12, 0))
92  {}
93 
94  int32_t imm;
95 };
96 
97 // This class is for instructions that explicitly write control
98 // registers. It provides a special generateDisassembly function.
99 class WrPrivImm : public PrivImm
100 {
101  protected:
102  // Constructor
103  WrPrivImm(const char *mnem, ExtMachInst _machInst,
104  OpClass __opClass, char const *_regName) :
105  PrivImm(mnem, _machInst, __opClass), regName(_regName)
106  {}
107 
108  std::string generateDisassembly(
109  Addr pc, const loader::SymbolTable *symtab) const override;
110 
111  char const *regName;
112 };
113 
114 } // namespace SparcISA
115 } // namespace gem5
116 
117 #endif //__ARCH_SPARC_INSTS_PRIV_HH__
gem5::SparcISA::WrPrivImm
Definition: priv.hh:99
gem5::SparcISA::SparcStaticInst
Base class for all SPARC static instructions.
Definition: static_inst.hh:91
gem5::SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:42
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::SparcISA::PrivImm::PrivImm
PrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Definition: priv.hh:90
gem5::SparcISA::PrivImm::imm
int32_t imm
Definition: priv.hh:94
gem5::SparcISA::WrPrivImm::regName
const char * regName
Definition: priv.hh:111
gem5::SparcISA::WrPrivImm::WrPrivImm
WrPrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, char const *_regName)
Definition: priv.hh:103
gem5::SparcISA::WrPriv::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:62
gem5::SparcISA::PrivImm
Base class for privelege mode operations with immediates.
Definition: priv.hh:86
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::SparcISA::Priv
Base class for privelege mode operations.
Definition: priv.hh:44
gem5::SparcISA::PrivReg
Definition: priv.hh:52
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::Priv::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:39
gem5::SparcISA::SparcStaticInst::SparcStaticInst
SparcStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:96
gem5::SparcISA::WrPrivImm::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:82
gem5::SparcISA::RdPriv
Definition: priv.hh:65
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::PrivReg::PrivReg
PrivReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, char const *_regName)
Definition: priv.hh:55
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::WrPriv
Definition: priv.hh:75
gem5::SparcISA::RdPriv::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:49
gem5::SparcISA::PrivReg::regName
const char * regName
Definition: priv.hh:60

Generated on Tue Sep 21 2021 12:24:51 for gem5 by doxygen 1.8.17