gem5  v21.1.0.2
priv.cc
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29 
30 #include "arch/sparc/insts/priv.hh"
31 
32 namespace gem5
33 {
34 
35 namespace SparcISA
36 {
37 
38 std::string
40 {
41  std::stringstream response;
42 
43  printMnemonic(response, mnemonic);
44 
45  return response.str();
46 }
47 
48 std::string
50 {
51  std::stringstream response;
52 
53  printMnemonic(response, mnemonic);
54 
55  ccprintf(response, " %%%s, ", regName);
56  printDestReg(response, 0);
57 
58  return response.str();
59 }
60 
61 std::string
63 {
64  std::stringstream response;
65 
66  printMnemonic(response, mnemonic);
67 
68  ccprintf(response, " ");
69  // If the first reg is %g0, don't print it.
70  // This improves readability
71  if (srcRegIdx(0).index() != 0) {
72  printSrcReg(response, 0);
73  ccprintf(response, ", ");
74  }
75  printSrcReg(response, 1);
76  ccprintf(response, ", %%%s", regName);
77 
78  return response.str();
79 }
80 
81 std::string
83  Addr pc, const loader::SymbolTable *symtab) const
84 {
85  std::stringstream response;
86 
87  printMnemonic(response, mnemonic);
88 
89  ccprintf(response, " ");
90  // If the first reg is %g0, don't print it.
91  // This improves readability
92  if (srcRegIdx(0).index() != 0) {
93  printSrcReg(response, 0);
94  ccprintf(response, ", ");
95  }
96  ccprintf(response, "%#x, %%%s", imm, regName);
97 
98  return response.str();
99 }
100 
101 } // namespace SparcISA
102 } // namespace gem5
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::SparcISA::SparcStaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg) const
Definition: static_inst.cc:88
priv.hh
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::SparcISA::PrivImm::imm
int32_t imm
Definition: priv.hh:94
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::SparcISA::WrPrivImm::regName
const char * regName
Definition: priv.hh:111
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::SparcISA::WrPriv::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:62
gem5::SparcISA::SparcStaticInst::printDestReg
void printDestReg(std::ostream &os, int reg) const
Definition: static_inst.cc:95
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::Priv::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:39
gem5::SparcISA::WrPrivImm::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:82
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::SparcStaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:63
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::SparcISA::RdPriv::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: priv.cc:49
gem5::SparcISA::PrivReg::regName
const char * regName
Definition: priv.hh:60

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