gem5  v21.1.0.2
mem.cc
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28 
29 #include "arch/sparc/insts/mem.hh"
30 
31 namespace gem5
32 {
33 
34 namespace SparcISA
35 {
36 
37 std::string
39 {
40  std::stringstream response;
41  bool load = flags[IsLoad];
42  bool store = flags[IsStore];
43 
44  printMnemonic(response, mnemonic);
45  if (store) {
46  printReg(response, srcRegIdx(0));
47  ccprintf(response, ", ");
48  }
49  ccprintf(response, "[");
50  if (srcRegIdx(!store ? 0 : 1).index() != 0) {
51  printSrcReg(response, !store ? 0 : 1);
52  ccprintf(response, " + ");
53  }
54  printSrcReg(response, !store ? 1 : 2);
55  ccprintf(response, "]");
56  if (load) {
57  ccprintf(response, ", ");
58  printReg(response, destRegIdx(0));
59  }
60 
61  return response.str();
62 }
63 
64 std::string
66 {
67  std::stringstream response;
68  bool load = flags[IsLoad];
69  bool save = flags[IsStore];
70 
71  printMnemonic(response, mnemonic);
72  if (save) {
73  printReg(response, srcRegIdx(0));
74  ccprintf(response, ", ");
75  }
76  ccprintf(response, "[");
77  if (srcRegIdx(!save ? 0 : 1).index() != 0) {
78  printReg(response, srcRegIdx(!save ? 0 : 1));
79  ccprintf(response, " + ");
80  }
81  if (imm >= 0)
82  ccprintf(response, "%#x]", imm);
83  else
84  ccprintf(response, "-%#x]", -imm);
85  if (load) {
86  ccprintf(response, ", ");
87  printReg(response, destRegIdx(0));
88  }
89 
90  return response.str();
91 }
92 
93 } // namespace SparcISA
94 } // namespace gem5
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::SparcISA::MemImm::imm
const int32_t imm
Definition: mem.hh:72
gem5::SparcISA::SparcStaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg) const
Definition: static_inst.cc:88
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::SparcISA::Mem::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:38
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::SparcISA::MemImm::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: mem.cc:65
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::SparcStaticInst::printReg
static void printReg(std::ostream &os, RegId reg)
Definition: static_inst.cc:102
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::SparcStaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:63
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
mem.hh

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