gem5  v21.2.1.1
static_inst.cc
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29 
31 
32 #include "arch/sparc/pcstate.hh"
33 #include "arch/sparc/regs/int.hh"
34 #include "arch/sparc/regs/misc.hh"
35 #include "base/bitunion.hh"
36 
37 namespace gem5
38 {
39 
40 namespace SparcISA
41 {
42 
43 const char *CondTestAbbrev[] =
44 {
45  [Never] = "nev",
46  [Equal] = "e",
47  [LessOrEqual] = "le",
48  [Less] = "l",
49  [LessOrEqualUnsigned] = "leu",
50  [CarrySet] = "c",
51  [Negative] = "n",
52  [OverflowSet] = "o",
53  [Always] = "a",
54  [NotEqual] = "ne",
55  [Greater] = "g",
56  [GreaterOrEqual] = "ge",
57  [GreaterUnsigned] = "gu",
58  [CarryClear] = "cc",
59  [Positive] = "p",
60  [OverflowClear] = "oc"
61 };
62 
63 void
64 SparcStaticInst::printMnemonic(std::ostream &os, const char *mnemonic)
65 {
66  ccprintf(os, "\t%s ", mnemonic);
67 }
68 
69 void
70 SparcStaticInst::printRegArray(std::ostream &os, const RegId *indexArray,
71  int num) const
72 {
73  if (num <= 0)
74  return;
75  printReg(os, indexArray[0]);
76  for (int x = 1; x < num; x++) {
77  os << ", ";
78  printReg(os, indexArray[x]);
79  }
80 }
81 
82 void
84 {
85  pcState.as<PCState>().advance();
86 }
87 
88 void
90 {
91  PCState pc = tc->pcState().as<PCState>();
92  pc.advance();
93  tc->pcState(pc);
94 }
95 
96 void
97 SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
98 {
99  if (_numSrcRegs > reg)
101 }
102 
103 void
104 SparcStaticInst::printDestReg(std::ostream &os, int reg) const
105 {
106  if (_numDestRegs > reg)
108 }
109 
110 void
112 {
113  const int MaxGlobal = 8;
114  const int MaxOutput = 16;
115  const int MaxLocal = 24;
116  const int MaxInput = 32;
117  const int MaxMicroReg = 40;
118  RegIndex reg_idx = reg.index();
119  if (reg.is(IntRegClass)) {
120  // If we used a register from the next or previous window,
121  // take out the offset.
122  while (reg_idx >= MaxMicroReg)
123  reg_idx -= MaxMicroReg;
124  if (reg_idx == FramePointerReg)
125  ccprintf(os, "%%fp");
126  else if (reg_idx == StackPointerReg)
127  ccprintf(os, "%%sp");
128  else if (reg_idx < MaxGlobal)
129  ccprintf(os, "%%g%d", reg_idx);
130  else if (reg_idx < MaxOutput)
131  ccprintf(os, "%%o%d", reg_idx - MaxGlobal);
132  else if (reg_idx < MaxLocal)
133  ccprintf(os, "%%l%d", reg_idx - MaxOutput);
134  else if (reg_idx < MaxInput)
135  ccprintf(os, "%%i%d", reg_idx - MaxLocal);
136  else if (reg_idx < MaxMicroReg)
137  ccprintf(os, "%%u%d", reg_idx - MaxInput);
138  // The fake int regs that are really control regs
139  else {
140  switch (reg_idx - MaxMicroReg) {
141  case 1:
142  ccprintf(os, "%%y");
143  break;
144  case 2:
145  ccprintf(os, "%%ccr");
146  break;
147  case 3:
148  ccprintf(os, "%%cansave");
149  break;
150  case 4:
151  ccprintf(os, "%%canrestore");
152  break;
153  case 5:
154  ccprintf(os, "%%cleanwin");
155  break;
156  case 6:
157  ccprintf(os, "%%otherwin");
158  break;
159  case 7:
160  ccprintf(os, "%%wstate");
161  break;
162  }
163  }
164  } else if (reg.is(FloatRegClass)) {
165  ccprintf(os, "%%f%d", reg_idx);
166  } else {
167  switch (reg_idx) {
168  case MISCREG_ASI:
169  ccprintf(os, "%%asi");
170  break;
171  case MISCREG_FPRS:
172  ccprintf(os, "%%fprs");
173  break;
174  case MISCREG_PCR:
175  ccprintf(os, "%%pcr");
176  break;
177  case MISCREG_PIC:
178  ccprintf(os, "%%pic");
179  break;
180  case MISCREG_GSR:
181  ccprintf(os, "%%gsr");
182  break;
183  case MISCREG_SOFTINT:
184  ccprintf(os, "%%softint");
185  break;
186  case MISCREG_SOFTINT_SET:
187  ccprintf(os, "%%softint_set");
188  break;
189  case MISCREG_SOFTINT_CLR:
190  ccprintf(os, "%%softint_clr");
191  break;
192  case MISCREG_TICK_CMPR:
193  ccprintf(os, "%%tick_cmpr");
194  break;
195  case MISCREG_STICK:
196  ccprintf(os, "%%stick");
197  break;
198  case MISCREG_STICK_CMPR:
199  ccprintf(os, "%%stick_cmpr");
200  break;
201  case MISCREG_TPC:
202  ccprintf(os, "%%tpc");
203  break;
204  case MISCREG_TNPC:
205  ccprintf(os, "%%tnpc");
206  break;
207  case MISCREG_TSTATE:
208  ccprintf(os, "%%tstate");
209  break;
210  case MISCREG_TT:
211  ccprintf(os, "%%tt");
212  break;
213  case MISCREG_TICK:
214  ccprintf(os, "%%tick");
215  break;
216  case MISCREG_TBA:
217  ccprintf(os, "%%tba");
218  break;
219  case MISCREG_PSTATE:
220  ccprintf(os, "%%pstate");
221  break;
222  case MISCREG_TL:
223  ccprintf(os, "%%tl");
224  break;
225  case MISCREG_PIL:
226  ccprintf(os, "%%pil");
227  break;
228  case MISCREG_CWP:
229  ccprintf(os, "%%cwp");
230  break;
231  case MISCREG_GL:
232  ccprintf(os, "%%gl");
233  break;
234  case MISCREG_HPSTATE:
235  ccprintf(os, "%%hpstate");
236  break;
237  case MISCREG_HTSTATE:
238  ccprintf(os, "%%htstate");
239  break;
240  case MISCREG_HINTP:
241  ccprintf(os, "%%hintp");
242  break;
243  case MISCREG_HTBA:
244  ccprintf(os, "%%htba");
245  break;
246  case MISCREG_HSTICK_CMPR:
247  ccprintf(os, "%%hstick_cmpr");
248  break;
249  case MISCREG_HVER:
250  ccprintf(os, "%%hver");
251  break;
253  ccprintf(os, "%%strand_sts_reg");
254  break;
255  case MISCREG_FSR:
256  ccprintf(os, "%%fsr");
257  break;
258  default:
259  ccprintf(os, "%%ctrl%d", reg_idx);
260  }
261  }
262 }
263 
264 std::string
266  Addr pc, const loader::SymbolTable *symtab) const
267 {
268  std::stringstream ss;
269 
271 
272  // just print the first two source regs... if there's
273  // a third one, it's a read-modify-write dest (Rc),
274  // e.g. for CMOVxx
275  if (_numSrcRegs > 0)
276  printReg(ss, srcRegIdx(0));
277  if (_numSrcRegs > 1) {
278  ss << ",";
279  printReg(ss, srcRegIdx(1));
280  }
281 
282  // just print the first dest... if there's a second one,
283  // it's generally implicit
284  if (_numDestRegs > 0) {
285  if (_numSrcRegs > 0)
286  ss << ",";
287  printReg(ss, destRegIdx(0));
288  }
289 
290  return ss.str();
291 }
292 
293 bool
294 SparcStaticInst::passesFpCondition(uint32_t fcc, uint32_t condition)
295 {
296  bool u = (fcc == 3);
297  bool g = (fcc == 2);
298  bool l = (fcc == 1);
299  bool e = (fcc == 0);
300 
301  switch (condition) {
302  case FAlways:
303  return 1;
304  case FNever:
305  return 0;
306  case FUnordered:
307  return u;
308  case FGreater:
309  return g;
310  case FUnorderedOrGreater:
311  return u || g;
312  case FLess:
313  return l;
314  case FUnorderedOrLess:
315  return u || l;
316  case FLessOrGreater:
317  return l || g;
318  case FNotEqual:
319  return l || g || u;
320  case FEqual:
321  return e;
322  case FUnorderedOrEqual:
323  return u || e;
324  case FGreaterOrEqual:
325  return g || e;
327  return u || g || e;
328  case FLessOrEqual:
329  return l || e;
331  return u || l || e;
332  case FOrdered:
333  return e || l || g;
334  }
335  panic("Tried testing condition nonexistant condition code %d", condition);
336 }
337 
338 bool
339 SparcStaticInst::passesCondition(uint32_t codes, uint32_t condition)
340 {
341  BitUnion32(CondCodes)
342  Bitfield<0> c;
343  Bitfield<1> v;
344  Bitfield<2> z;
345  Bitfield<3> n;
346  EndBitUnion(CondCodes)
347  CondCodes condCodes = codes;
348 
349  switch (condition) {
350  case Always:
351  return true;
352  case Never:
353  return false;
354  case NotEqual:
355  return !condCodes.z;
356  case Equal:
357  return condCodes.z;
358  case Greater:
359  return !(condCodes.z | (condCodes.n ^ condCodes.v));
360  case LessOrEqual:
361  return condCodes.z | (condCodes.n ^ condCodes.v);
362  case GreaterOrEqual:
363  return !(condCodes.n ^ condCodes.v);
364  case Less:
365  return (condCodes.n ^ condCodes.v);
366  case GreaterUnsigned:
367  return !(condCodes.c | condCodes.z);
368  case LessOrEqualUnsigned:
369  return (condCodes.c | condCodes.z);
370  case CarryClear:
371  return !condCodes.c;
372  case CarrySet:
373  return condCodes.c;
374  case Positive:
375  return !condCodes.n;
376  case Negative:
377  return condCodes.n;
378  case OverflowClear:
379  return !condCodes.v;
380  case OverflowSet:
381  return condCodes.v;
382  }
383  panic("Tried testing condition nonexistant "
384  "condition code %d", condition);
385 }
386 
387 } // namespace SparcISA
388 } // namespace gem5
gem5::SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: misc.hh:45
gem5::SparcISA::MISCREG_TICK_CMPR
@ MISCREG_TICK_CMPR
Definition: misc.hh:54
gem5::SparcISA::z
Bitfield< 6 > z
Definition: misc.hh:142
gem5::SparcISA::FGreaterOrEqual
@ FGreaterOrEqual
Definition: static_inst.hh:83
gem5::SparcISA::OverflowSet
@ OverflowSet
Definition: static_inst.hh:65
gem5::SparcISA::FUnorderedOrGreater
@ FUnorderedOrGreater
Definition: static_inst.hh:76
gem5::SparcISA::Less
@ Less
Definition: static_inst.hh:57
misc.hh
gem5::SparcISA::FUnorderedOrLessOrEqual
@ FUnorderedOrLessOrEqual
Definition: static_inst.hh:86
gem5::SparcISA::Never
@ Never
Definition: static_inst.hh:51
gem5::SparcISA::FUnorderedOrLess
@ FUnorderedOrLess
Definition: static_inst.hh:78
gem5::SparcISA::CarryClear
@ CarryClear
Definition: static_inst.hh:60
gem5::SparcISA::FAlways
@ FAlways
Definition: static_inst.hh:72
gem5::SparcISA::v
Bitfield< 5 > v
Definition: misc.hh:143
pcstate.hh
gem5::SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: misc.hh:62
gem5::SparcISA::SparcStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:265
gem5::SparcISA::CarrySet
@ CarrySet
Definition: static_inst.hh:61
gem5::SparcISA::NotEqual
@ NotEqual
Definition: static_inst.hh:52
gem5::PCStateBase::as
Target & as()
Definition: pcstate.hh:72
gem5::ThreadContext::pcState
virtual const PCStateBase & pcState() const =0
gem5::SparcISA::SparcStaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg) const
Definition: static_inst.cc:97
gem5::SparcISA::Equal
@ Equal
Definition: static_inst.hh:53
gem5::SparcISA::n
Bitfield< 7 > n
Definition: misc.hh:140
gem5::SparcISA::MISCREG_STICK
@ MISCREG_STICK
Definition: misc.hh:55
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::SparcISA::FramePointerReg
const int FramePointerReg
Definition: int.hh:74
gem5::SparcISA::FLess
@ FLess
Definition: static_inst.hh:77
gem5::SparcISA::MISCREG_SOFTINT_SET
@ MISCREG_SOFTINT_SET
Definition: misc.hh:51
gem5::loader::SymbolTable
Definition: symtab.hh:65
BitUnion32
#define BitUnion32(name)
Definition: bitunion.hh:495
gem5::SparcISA::FUnorderedOrEqual
@ FUnorderedOrEqual
Definition: static_inst.hh:82
gem5::SparcISA::MISCREG_HVER
@ MISCREG_HVER
Definition: misc.hh:81
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::OverflowClear
@ OverflowClear
Definition: static_inst.hh:64
gem5::SparcISA::MISCREG_FPRS
@ MISCREG_FPRS
Definition: misc.hh:47
gem5::SparcISA::SparcStaticInst::printRegArray
void printRegArray(std::ostream &os, const RegId *indexArray, int num) const
Definition: static_inst.cc:70
gem5::SparcISA::MISCREG_HINTP
@ MISCREG_HINTP
Definition: misc.hh:79
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:236
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::SparcISA::LessOrEqual
@ LessOrEqual
Definition: static_inst.hh:55
gem5::SparcISA::MISCREG_HSTICK_CMPR
@ MISCREG_HSTICK_CMPR
Definition: misc.hh:83
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:59
gem5::SparcISA::LessOrEqualUnsigned
@ LessOrEqualUnsigned
Definition: static_inst.hh:59
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::SparcISA::EndBitUnion
EndBitUnion(HPSTATE) BitUnion16(PSTATE) Bitfield< 1 > ie
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:246
gem5::SparcISA::GreaterUnsigned
@ GreaterUnsigned
Definition: static_inst.hh:58
gem5::SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: misc.hh:66
bitunion.hh
gem5::SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: misc.hh:61
gem5::SparcISA::SparcStaticInst::advancePC
void advancePC(PCStateBase &pcState) const override
Definition: static_inst.cc:83
gem5::SparcISA::SparcStaticInst::printDestReg
void printDestReg(std::ostream &os, int reg) const
Definition: static_inst.cc:104
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::SparcISA::FGreater
@ FGreater
Definition: static_inst.hh:75
int.hh
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::SparcISA::GreaterOrEqual
@ GreaterOrEqual
Definition: static_inst.hh:56
gem5::SparcISA::FLessOrGreater
@ FLessOrGreater
Definition: static_inst.hh:79
gem5::MipsISA::g
Bitfield< 4 > g
Definition: dt_constants.hh:86
gem5::SparcISA::MISCREG_PCR
@ MISCREG_PCR
Definition: misc.hh:48
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::FOrdered
@ FOrdered
Definition: static_inst.hh:87
gem5::SparcISA::FNotEqual
@ FNotEqual
Definition: static_inst.hh:80
gem5::SparcISA::SparcStaticInst::printReg
static void printReg(std::ostream &os, RegId reg)
Definition: static_inst.cc:111
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SparcISA::CondTestAbbrev
const char * CondTestAbbrev[]
Definition: static_inst.cc:43
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::ArmISA::u
Bitfield< 22 > u
Definition: misc_types.hh:353
gem5::SparcISA::MISCREG_GSR
@ MISCREG_GSR
Definition: misc.hh:50
gem5::SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: misc.hh:80
gem5::SparcISA::FUnorderedOrGreaterOrEqual
@ FUnorderedOrGreaterOrEqual
Definition: static_inst.hh:84
gem5::SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: misc.hh:60
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::SparcISA::FUnordered
@ FUnordered
Definition: static_inst.hh:74
gem5::SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: misc.hh:46
gem5::SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: misc.hh:64
gem5::SparcISA::FEqual
@ FEqual
Definition: static_inst.hh:81
gem5::SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: misc.hh:86
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::SparcISA::SparcStaticInst::passesCondition
static bool passesCondition(uint32_t codes, uint32_t condition)
Definition: static_inst.cc:339
gem5::SparcISA::Greater
@ Greater
Definition: static_inst.hh:54
gem5::StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:111
static_inst.hh
gem5::GenericISA::DelaySlotUPCState
Definition: pcstate.hh:530
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::FLessOrEqual
@ FLessOrEqual
Definition: static_inst.hh:85
gem5::SparcISA::Positive
@ Positive
Definition: static_inst.hh:62
gem5::SparcISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:73
gem5::SparcISA::MISCREG_SOFTINT_CLR
@ MISCREG_SOFTINT_CLR
Definition: misc.hh:52
gem5::SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: misc.hh:78
gem5::SparcISA::SparcStaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:64
gem5::SparcISA::MISCREG_PIL
@ MISCREG_PIL
Definition: misc.hh:67
gem5::SparcISA::MISCREG_STRAND_STS_REG
@ MISCREG_STRAND_STS_REG
Definition: misc.hh:82
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::SparcISA::FNever
@ FNever
Definition: static_inst.hh:73
gem5::SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: misc.hh:74
gem5::SparcISA::Negative
@ Negative
Definition: static_inst.hh:63
gem5::SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: misc.hh:59
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:280
gem5::SparcISA::MISCREG_PIC
@ MISCREG_PIC
Definition: misc.hh:49
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:108
gem5::SparcISA::Always
@ Always
Definition: static_inst.hh:50
gem5::SparcISA::MISCREG_STICK_CMPR
@ MISCREG_STICK_CMPR
Definition: misc.hh:56
gem5::SparcISA::SparcStaticInst::passesFpCondition
static bool passesFpCondition(uint32_t fcc, uint32_t condition)
Definition: static_inst.cc:294
gem5::SparcISA::c
Bitfield< 4 > c
Definition: misc.hh:144
gem5::SparcISA::MISCREG_SOFTINT
@ MISCREG_SOFTINT
Definition: misc.hh:53
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:113
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178

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