gem5  v21.1.0.2
static_inst.cc
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29 
31 
32 #include "arch/sparc/regs/int.hh"
33 #include "arch/sparc/regs/misc.hh"
34 #include "base/bitunion.hh"
35 
36 namespace gem5
37 {
38 
39 namespace SparcISA
40 {
41 
42 const char *CondTestAbbrev[] =
43 {
44  [Never] = "nev",
45  [Equal] = "e",
46  [LessOrEqual] = "le",
47  [Less] = "l",
48  [LessOrEqualUnsigned] = "leu",
49  [CarrySet] = "c",
50  [Negative] = "n",
51  [OverflowSet] = "o",
52  [Always] = "a",
53  [NotEqual] = "ne",
54  [Greater] = "g",
55  [GreaterOrEqual] = "ge",
56  [GreaterUnsigned] = "gu",
57  [CarryClear] = "cc",
58  [Positive] = "p",
59  [OverflowClear] = "oc"
60 };
61 
62 void
63 SparcStaticInst::printMnemonic(std::ostream &os, const char *mnemonic)
64 {
65  ccprintf(os, "\t%s ", mnemonic);
66 }
67 
68 void
69 SparcStaticInst::printRegArray(std::ostream &os, const RegId *indexArray,
70  int num) const
71 {
72  if (num <= 0)
73  return;
74  printReg(os, indexArray[0]);
75  for (int x = 1; x < num; x++) {
76  os << ", ";
77  printReg(os, indexArray[x]);
78  }
79 }
80 
81 void
83 {
84  pcState.advance();
85 }
86 
87 void
88 SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
89 {
90  if (_numSrcRegs > reg)
92 }
93 
94 void
95 SparcStaticInst::printDestReg(std::ostream &os, int reg) const
96 {
97  if (_numDestRegs > reg)
99 }
100 
101 void
103 {
104  const int MaxGlobal = 8;
105  const int MaxOutput = 16;
106  const int MaxLocal = 24;
107  const int MaxInput = 32;
108  const int MaxMicroReg = 40;
109  RegIndex reg_idx = reg.index();
110  if (reg.is(IntRegClass)) {
111  // If we used a register from the next or previous window,
112  // take out the offset.
113  while (reg_idx >= MaxMicroReg)
114  reg_idx -= MaxMicroReg;
115  if (reg_idx == FramePointerReg)
116  ccprintf(os, "%%fp");
117  else if (reg_idx == StackPointerReg)
118  ccprintf(os, "%%sp");
119  else if (reg_idx < MaxGlobal)
120  ccprintf(os, "%%g%d", reg_idx);
121  else if (reg_idx < MaxOutput)
122  ccprintf(os, "%%o%d", reg_idx - MaxGlobal);
123  else if (reg_idx < MaxLocal)
124  ccprintf(os, "%%l%d", reg_idx - MaxOutput);
125  else if (reg_idx < MaxInput)
126  ccprintf(os, "%%i%d", reg_idx - MaxLocal);
127  else if (reg_idx < MaxMicroReg)
128  ccprintf(os, "%%u%d", reg_idx - MaxInput);
129  // The fake int regs that are really control regs
130  else {
131  switch (reg_idx - MaxMicroReg) {
132  case 1:
133  ccprintf(os, "%%y");
134  break;
135  case 2:
136  ccprintf(os, "%%ccr");
137  break;
138  case 3:
139  ccprintf(os, "%%cansave");
140  break;
141  case 4:
142  ccprintf(os, "%%canrestore");
143  break;
144  case 5:
145  ccprintf(os, "%%cleanwin");
146  break;
147  case 6:
148  ccprintf(os, "%%otherwin");
149  break;
150  case 7:
151  ccprintf(os, "%%wstate");
152  break;
153  }
154  }
155  } else if (reg.is(FloatRegClass)) {
156  ccprintf(os, "%%f%d", reg_idx);
157  } else {
158  switch (reg_idx) {
159  case MISCREG_ASI:
160  ccprintf(os, "%%asi");
161  break;
162  case MISCREG_FPRS:
163  ccprintf(os, "%%fprs");
164  break;
165  case MISCREG_PCR:
166  ccprintf(os, "%%pcr");
167  break;
168  case MISCREG_PIC:
169  ccprintf(os, "%%pic");
170  break;
171  case MISCREG_GSR:
172  ccprintf(os, "%%gsr");
173  break;
174  case MISCREG_SOFTINT:
175  ccprintf(os, "%%softint");
176  break;
177  case MISCREG_SOFTINT_SET:
178  ccprintf(os, "%%softint_set");
179  break;
180  case MISCREG_SOFTINT_CLR:
181  ccprintf(os, "%%softint_clr");
182  break;
183  case MISCREG_TICK_CMPR:
184  ccprintf(os, "%%tick_cmpr");
185  break;
186  case MISCREG_STICK:
187  ccprintf(os, "%%stick");
188  break;
189  case MISCREG_STICK_CMPR:
190  ccprintf(os, "%%stick_cmpr");
191  break;
192  case MISCREG_TPC:
193  ccprintf(os, "%%tpc");
194  break;
195  case MISCREG_TNPC:
196  ccprintf(os, "%%tnpc");
197  break;
198  case MISCREG_TSTATE:
199  ccprintf(os, "%%tstate");
200  break;
201  case MISCREG_TT:
202  ccprintf(os, "%%tt");
203  break;
204  case MISCREG_TICK:
205  ccprintf(os, "%%tick");
206  break;
207  case MISCREG_TBA:
208  ccprintf(os, "%%tba");
209  break;
210  case MISCREG_PSTATE:
211  ccprintf(os, "%%pstate");
212  break;
213  case MISCREG_TL:
214  ccprintf(os, "%%tl");
215  break;
216  case MISCREG_PIL:
217  ccprintf(os, "%%pil");
218  break;
219  case MISCREG_CWP:
220  ccprintf(os, "%%cwp");
221  break;
222  case MISCREG_GL:
223  ccprintf(os, "%%gl");
224  break;
225  case MISCREG_HPSTATE:
226  ccprintf(os, "%%hpstate");
227  break;
228  case MISCREG_HTSTATE:
229  ccprintf(os, "%%htstate");
230  break;
231  case MISCREG_HINTP:
232  ccprintf(os, "%%hintp");
233  break;
234  case MISCREG_HTBA:
235  ccprintf(os, "%%htba");
236  break;
237  case MISCREG_HSTICK_CMPR:
238  ccprintf(os, "%%hstick_cmpr");
239  break;
240  case MISCREG_HVER:
241  ccprintf(os, "%%hver");
242  break;
244  ccprintf(os, "%%strand_sts_reg");
245  break;
246  case MISCREG_FSR:
247  ccprintf(os, "%%fsr");
248  break;
249  default:
250  ccprintf(os, "%%ctrl%d", reg_idx);
251  }
252  }
253 }
254 
255 std::string
257  Addr pc, const loader::SymbolTable *symtab) const
258 {
259  std::stringstream ss;
260 
262 
263  // just print the first two source regs... if there's
264  // a third one, it's a read-modify-write dest (Rc),
265  // e.g. for CMOVxx
266  if (_numSrcRegs > 0)
267  printReg(ss, srcRegIdx(0));
268  if (_numSrcRegs > 1) {
269  ss << ",";
270  printReg(ss, srcRegIdx(1));
271  }
272 
273  // just print the first dest... if there's a second one,
274  // it's generally implicit
275  if (_numDestRegs > 0) {
276  if (_numSrcRegs > 0)
277  ss << ",";
278  printReg(ss, destRegIdx(0));
279  }
280 
281  return ss.str();
282 }
283 
284 bool
285 SparcStaticInst::passesFpCondition(uint32_t fcc, uint32_t condition)
286 {
287  bool u = (fcc == 3);
288  bool g = (fcc == 2);
289  bool l = (fcc == 1);
290  bool e = (fcc == 0);
291 
292  switch (condition) {
293  case FAlways:
294  return 1;
295  case FNever:
296  return 0;
297  case FUnordered:
298  return u;
299  case FGreater:
300  return g;
301  case FUnorderedOrGreater:
302  return u || g;
303  case FLess:
304  return l;
305  case FUnorderedOrLess:
306  return u || l;
307  case FLessOrGreater:
308  return l || g;
309  case FNotEqual:
310  return l || g || u;
311  case FEqual:
312  return e;
313  case FUnorderedOrEqual:
314  return u || e;
315  case FGreaterOrEqual:
316  return g || e;
318  return u || g || e;
319  case FLessOrEqual:
320  return l || e;
322  return u || l || e;
323  case FOrdered:
324  return e || l || g;
325  }
326  panic("Tried testing condition nonexistant condition code %d", condition);
327 }
328 
329 bool
330 SparcStaticInst::passesCondition(uint32_t codes, uint32_t condition)
331 {
332  BitUnion32(CondCodes)
333  Bitfield<0> c;
334  Bitfield<1> v;
335  Bitfield<2> z;
336  Bitfield<3> n;
337  EndBitUnion(CondCodes)
338  CondCodes condCodes = codes;
339 
340  switch (condition) {
341  case Always:
342  return true;
343  case Never:
344  return false;
345  case NotEqual:
346  return !condCodes.z;
347  case Equal:
348  return condCodes.z;
349  case Greater:
350  return !(condCodes.z | (condCodes.n ^ condCodes.v));
351  case LessOrEqual:
352  return condCodes.z | (condCodes.n ^ condCodes.v);
353  case GreaterOrEqual:
354  return !(condCodes.n ^ condCodes.v);
355  case Less:
356  return (condCodes.n ^ condCodes.v);
357  case GreaterUnsigned:
358  return !(condCodes.c | condCodes.z);
359  case LessOrEqualUnsigned:
360  return (condCodes.c | condCodes.z);
361  case CarryClear:
362  return !condCodes.c;
363  case CarrySet:
364  return condCodes.c;
365  case Positive:
366  return !condCodes.n;
367  case Negative:
368  return condCodes.n;
369  case OverflowClear:
370  return !condCodes.v;
371  case OverflowSet:
372  return condCodes.v;
373  }
374  panic("Tried testing condition nonexistant "
375  "condition code %d", condition);
376 }
377 
378 } // namespace SparcISA
379 } // namespace gem5
gem5::SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: misc.hh:45
gem5::SparcISA::MISCREG_TICK_CMPR
@ MISCREG_TICK_CMPR
Definition: misc.hh:54
gem5::SparcISA::z
Bitfield< 6 > z
Definition: misc.hh:142
gem5::SparcISA::FGreaterOrEqual
@ FGreaterOrEqual
Definition: static_inst.hh:81
gem5::SparcISA::OverflowSet
@ OverflowSet
Definition: static_inst.hh:63
gem5::SparcISA::FUnorderedOrGreater
@ FUnorderedOrGreater
Definition: static_inst.hh:74
gem5::SparcISA::Less
@ Less
Definition: static_inst.hh:55
misc.hh
gem5::SparcISA::FUnorderedOrLessOrEqual
@ FUnorderedOrLessOrEqual
Definition: static_inst.hh:84
gem5::SparcISA::Never
@ Never
Definition: static_inst.hh:49
gem5::SparcISA::FUnorderedOrLess
@ FUnorderedOrLess
Definition: static_inst.hh:76
gem5::SparcISA::CarryClear
@ CarryClear
Definition: static_inst.hh:58
gem5::SparcISA::FAlways
@ FAlways
Definition: static_inst.hh:70
gem5::SparcISA::v
Bitfield< 5 > v
Definition: misc.hh:143
gem5::SparcISA::MISCREG_TT
@ MISCREG_TT
Definition: misc.hh:62
gem5::SparcISA::SparcStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:256
gem5::SparcISA::CarrySet
@ CarrySet
Definition: static_inst.hh:59
gem5::SparcISA::NotEqual
@ NotEqual
Definition: static_inst.hh:50
gem5::SparcISA::SparcStaticInst::printSrcReg
void printSrcReg(std::ostream &os, int reg) const
Definition: static_inst.cc:88
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:58
gem5::SparcISA::Equal
@ Equal
Definition: static_inst.hh:51
gem5::SparcISA::n
Bitfield< 7 > n
Definition: misc.hh:140
gem5::SparcISA::MISCREG_STICK
@ MISCREG_STICK
Definition: misc.hh:55
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:64
gem5::SparcISA::FramePointerReg
const int FramePointerReg
Definition: int.hh:74
gem5::SparcISA::FLess
@ FLess
Definition: static_inst.hh:75
gem5::SparcISA::MISCREG_SOFTINT_SET
@ MISCREG_SOFTINT_SET
Definition: misc.hh:51
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::SparcISA::SparcStaticInst::advancePC
void advancePC(PCState &pcState) const override
Definition: static_inst.cc:82
BitUnion32
#define BitUnion32(name)
Definition: bitunion.hh:496
gem5::SparcISA::FUnorderedOrEqual
@ FUnorderedOrEqual
Definition: static_inst.hh:80
gem5::SparcISA::MISCREG_HVER
@ MISCREG_HVER
Definition: misc.hh:81
gem5::SparcISA::MISCREG_HPSTATE
@ MISCREG_HPSTATE
Hyper privileged registers.
Definition: misc.hh:77
gem5::SparcISA::OverflowClear
@ OverflowClear
Definition: static_inst.hh:62
gem5::SparcISA::MISCREG_FPRS
@ MISCREG_FPRS
Definition: misc.hh:47
gem5::SparcISA::SparcStaticInst::printRegArray
void printRegArray(std::ostream &os, const RegId *indexArray, int num) const
Definition: static_inst.cc:69
gem5::SparcISA::MISCREG_HINTP
@ MISCREG_HINTP
Definition: misc.hh:79
gem5::StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:237
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::SparcISA::LessOrEqual
@ LessOrEqual
Definition: static_inst.hh:53
gem5::SparcISA::MISCREG_HSTICK_CMPR
@ MISCREG_HSTICK_CMPR
Definition: misc.hh:83
gem5::SparcISA::LessOrEqualUnsigned
@ LessOrEqualUnsigned
Definition: static_inst.hh:57
gem5::SparcISA::EndBitUnion
EndBitUnion(HPSTATE) BitUnion16(PSTATE) Bitfield< 1 > ie
gem5::StaticInst::srcRegIdx
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
Definition: static_inst.hh:247
gem5::SparcISA::GreaterUnsigned
@ GreaterUnsigned
Definition: static_inst.hh:56
gem5::SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: misc.hh:66
bitunion.hh
gem5::SparcISA::MISCREG_TSTATE
@ MISCREG_TSTATE
Definition: misc.hh:61
gem5::SparcISA::SparcStaticInst::printDestReg
void printDestReg(std::ostream &os, int reg) const
Definition: static_inst.cc:95
gem5::MipsISA::l
Bitfield< 5 > l
Definition: pra_constants.hh:323
gem5::SparcISA::FGreater
@ FGreater
Definition: static_inst.hh:73
int.hh
ss
std::stringstream ss
Definition: trace.test.cc:45
gem5::SparcISA::GreaterOrEqual
@ GreaterOrEqual
Definition: static_inst.hh:54
gem5::SparcISA::FLessOrGreater
@ FLessOrGreater
Definition: static_inst.hh:77
gem5::MipsISA::g
Bitfield< 4 > g
Definition: dt_constants.hh:86
gem5::SparcISA::MISCREG_PCR
@ MISCREG_PCR
Definition: misc.hh:48
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::FOrdered
@ FOrdered
Definition: static_inst.hh:85
gem5::SparcISA::FNotEqual
@ FNotEqual
Definition: static_inst.hh:78
gem5::SparcISA::SparcStaticInst::printReg
static void printReg(std::ostream &os, RegId reg)
Definition: static_inst.cc:102
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::SparcISA::CondTestAbbrev
const char * CondTestAbbrev[]
Definition: static_inst.cc:42
gem5::ArmISA::u
Bitfield< 22 > u
Definition: misc_types.hh:352
gem5::SparcISA::MISCREG_GSR
@ MISCREG_GSR
Definition: misc.hh:50
gem5::SparcISA::MISCREG_HTBA
@ MISCREG_HTBA
Definition: misc.hh:80
gem5::SparcISA::FUnorderedOrGreaterOrEqual
@ FUnorderedOrGreaterOrEqual
Definition: static_inst.hh:82
gem5::SparcISA::MISCREG_TNPC
@ MISCREG_TNPC
Definition: misc.hh:60
gem5::RiscvISA::x
Bitfield< 3 > x
Definition: pagetable.hh:73
gem5::SparcISA::FUnordered
@ FUnordered
Definition: static_inst.hh:72
gem5::SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: misc.hh:46
gem5::SparcISA::MISCREG_TBA
@ MISCREG_TBA
Definition: misc.hh:64
gem5::SparcISA::FEqual
@ FEqual
Definition: static_inst.hh:79
gem5::SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: misc.hh:86
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::SparcISA::SparcStaticInst::passesCondition
static bool passesCondition(uint32_t codes, uint32_t condition)
Definition: static_inst.cc:330
gem5::SparcISA::Greater
@ Greater
Definition: static_inst.hh:52
gem5::StaticInst::_numDestRegs
int8_t _numDestRegs
See numDestRegs().
Definition: static_inst.hh:112
static_inst.hh
gem5::GenericISA::DelaySlotUPCState
Definition: types.hh:384
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: misc.hh:65
gem5::SparcISA::FLessOrEqual
@ FLessOrEqual
Definition: static_inst.hh:83
gem5::SparcISA::Positive
@ Positive
Definition: static_inst.hh:60
gem5::SparcISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:73
gem5::GenericISA::DelaySlotPCState::advance
void advance()
Definition: types.hh:337
gem5::SparcISA::MISCREG_SOFTINT_CLR
@ MISCREG_SOFTINT_CLR
Definition: misc.hh:52
gem5::SparcISA::MISCREG_HTSTATE
@ MISCREG_HTSTATE
Definition: misc.hh:78
gem5::SparcISA::SparcStaticInst::printMnemonic
static void printMnemonic(std::ostream &os, const char *mnemonic)
Definition: static_inst.cc:63
gem5::SparcISA::MISCREG_PIL
@ MISCREG_PIL
Definition: misc.hh:67
gem5::SparcISA::MISCREG_STRAND_STS_REG
@ MISCREG_STRAND_STS_REG
Definition: misc.hh:82
gem5::SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: misc.hh:68
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::SparcISA::FNever
@ FNever
Definition: static_inst.hh:71
gem5::SparcISA::MISCREG_GL
@ MISCREG_GL
Definition: misc.hh:74
gem5::SparcISA::Negative
@ Negative
Definition: static_inst.hh:61
gem5::SparcISA::MISCREG_TPC
@ MISCREG_TPC
Privilged Registers.
Definition: misc.hh:59
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5::SparcISA::MISCREG_PIC
@ MISCREG_PIC
Definition: misc.hh:49
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:57
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::StaticInst::_numSrcRegs
int8_t _numSrcRegs
See numSrcRegs().
Definition: static_inst.hh:109
gem5::SparcISA::Always
@ Always
Definition: static_inst.hh:48
gem5::SparcISA::MISCREG_STICK_CMPR
@ MISCREG_STICK_CMPR
Definition: misc.hh:56
gem5::SparcISA::SparcStaticInst::passesFpCondition
static bool passesFpCondition(uint32_t fcc, uint32_t condition)
Definition: static_inst.cc:285
gem5::SparcISA::c
Bitfield< 4 > c
Definition: misc.hh:144
gem5::SparcISA::MISCREG_SOFTINT
@ MISCREG_SOFTINT
Definition: misc.hh:53
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:88
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177

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