gem5 v24.0.0.0
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ide_ctrl.hh File Reference

Simple PCI IDE controller with bus mastering capability and UDMA modeled after controller in the Intel PIIX4 chip. More...

#include "base/bitunion.hh"
#include "dev/io_device.hh"
#include "dev/pci/device.hh"
#include "dev/reg_bank.hh"
#include "params/IdeController.hh"

Go to the source code of this file.

Classes

class  gem5::IdeController
 Device model for an Intel PIIX4 IDE controller. More...
 
class  gem5::IdeController::Channel
 
struct  gem5::IdeController::Channel::BMIRegs
 Registers used for bus master interface. More...
 

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 

Detailed Description

Simple PCI IDE controller with bus mastering capability and UDMA modeled after controller in the Intel PIIX4 chip.

Definition in file ide_ctrl.hh.


Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0