gem5  v22.0.0.2
ide_ctrl.hh
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28 
34 #ifndef __DEV_STORAGE_IDE_CTRL_HH__
35 #define __DEV_STORAGE_IDE_CTRL_HH__
36 
37 #include "base/bitunion.hh"
38 #include "dev/io_device.hh"
39 #include "dev/pci/device.hh"
40 #include "dev/reg_bank.hh"
41 #include "params/IdeController.hh"
42 
43 namespace gem5
44 {
45 
46 class IdeDisk;
47 
52 class IdeController : public PciDevice
53 {
54  private:
55  // Bus master IDE status register bit fields
56  BitUnion8(BMIStatusReg)
57  Bitfield<6> dmaCap0;
58  Bitfield<5> dmaCap1;
59  Bitfield<2> intStatus;
60  Bitfield<1> dmaError;
61  Bitfield<0> active;
62  EndBitUnion(BMIStatusReg)
63 
64  BitUnion8(BMICommandReg)
65  Bitfield<3> rw;
66  Bitfield<0> startStop;
67  EndBitUnion(BMICommandReg)
68 
69 
70  class ConfigSpaceRegs : public RegisterBankLE
71  {
72  public:
73  ConfigSpaceRegs(const std::string &name) :
75  {
76  // None of these registers are actually hooked up to control
77  // anything, so they have no specially defined behaviors. They
78  // just store values for now, but should presumably do something
79  // in a more accurate model.
80  addRegisters({primaryTiming, secondaryTiming, deviceTiming, raz0,
81  udmaControl, raz1, udmaTiming, raz2});
82  }
83 
84  enum
85  {
86  TimeRegWithDecodeEnabled = 0x8000
87  };
88 
89  /* Offset in config space */
90  /* 0x40-0x41 */ Register16 primaryTiming =
91  {"primary timing", TimeRegWithDecodeEnabled};
92  /* 0x42-0x43 */ Register16 secondaryTiming =
93  {"secondary timing", TimeRegWithDecodeEnabled};
94  /* 0x44 */ Register8 deviceTiming = {"device timing"};
95  /* 0x45-0x47 */ RegisterRaz raz0 = {"raz0", 3};
96  /* 0x48 */ Register8 udmaControl = {"udma control"};
97  /* 0x49 */ RegisterRaz raz1 = {"raz1", 1};
98  /* 0x4a-0x4b */ Register16 udmaTiming = {"udma timing"};
99  /* 0x4c-... */ RegisterRaz raz2 = {"raz2", PCI_CONFIG_SIZE - 0x4c};
100 
101  void serialize(CheckpointOut &cp) const;
102  void unserialize(CheckpointIn &cp);
103  };
104 
105  ConfigSpaceRegs configSpaceRegs;
106 
107  public:
108  class Channel : public Named
109  {
110  private:
112 
119  IdeDisk *device0 = nullptr, *device1 = nullptr;
120 
122  IdeDisk *_selected = nullptr;
123 
124  bool selectBit = false;
125  bool primary;
126 
127  bool _pendingInterrupt = false;
128 
129  public:
130  bool isPrimary() const { return primary; }
131 
132  bool pendingInterrupt() const { return _pendingInterrupt; }
133 
134  IdeDisk *selected() const { return _selected; }
135  IdeController *controller() const { return ctrl; }
136 
137  void
139  {
140  assert(!device0 && disk);
141  device0 = disk;
142  }
143 
144  void
146  {
147  assert(!device1 && disk);
148  device1 = disk;
149  }
150 
152  struct BMIRegs
153  {
154  void
156  {
157  memset(static_cast<void *>(this), 0, sizeof(*this));
158  }
159 
160  BMICommandReg command;
161  uint8_t reserved0;
162  BMIStatusReg status;
163  uint8_t reserved1;
164  uint32_t bmidtp;
165  } bmiRegs;
166 
167  void
168  select(bool select_device_1)
169  {
170  selectBit = select_device_1;
172  }
173 
174  void accessCommand(Addr offset, int size, uint8_t *data, bool read);
175  void accessControl(Addr offset, int size, uint8_t *data, bool read);
176  void accessBMI(Addr offset, int size, uint8_t *data, bool read);
177 
178  void setDmaComplete();
179 
180  void postInterrupt();
181  void clearInterrupt();
182 
183  Channel(std::string new_name, IdeController *new_ctrl,
184  bool new_primary);
185 
186  void serialize(const std::string &base, std::ostream &os) const;
187  void unserialize(const std::string &base, CheckpointIn &cp);
188  };
189 
190  private:
193 
194  uint32_t ioShift, ctrlOffset;
195 
196  void dispatchAccess(PacketPtr pkt, bool read);
197 
198  public:
200  IdeController(const Params &p);
201 
202  virtual void postInterrupt(bool is_primary);
203  virtual void clearInterrupt(bool is_primary);
204 
205  Tick writeConfig(PacketPtr pkt) override;
206  Tick readConfig(PacketPtr pkt) override;
207 
208  Tick read(PacketPtr pkt) override;
209  Tick write(PacketPtr pkt) override;
210 
211  void serialize(CheckpointOut &cp) const override;
212  void unserialize(CheckpointIn &cp) override;
213 };
214 
215 } // namespace gem5
216 
217 #endif // __DEV_STORAGE_IDE_CTRL_HH_
gem5::IdeController::Channel::serialize
void serialize(const std::string &base, std::ostream &os) const
Definition: ide_ctrl.cc:415
io_device.hh
gem5::IdeController::Channel::_selected
IdeDisk * _selected
Currently selected disk.
Definition: ide_ctrl.hh:122
gem5::RegisterBankLE
RegisterBank< ByteOrder::little > RegisterBankLE
Definition: reg_bank.hh:941
gem5::IdeController::Channel::pendingInterrupt
bool pendingInterrupt() const
Definition: ide_ctrl.hh:132
gem5::IdeController::Channel::BMIRegs::reserved1
uint8_t reserved1
Definition: ide_ctrl.hh:163
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::IdeController::Channel::selectBit
bool selectBit
Definition: ide_ctrl.hh:124
gem5::IdeController::dmaCap1
Bitfield< 5 > dmaCap1
Definition: ide_ctrl.hh:58
gem5::IdeController::Channel::setDevice0
void setDevice0(IdeDisk *disk)
Definition: ide_ctrl.hh:138
gem5::IdeController::Channel::BMIRegs::reserved0
uint8_t reserved0
Definition: ide_ctrl.hh:161
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::IdeController::Channel::isPrimary
bool isPrimary() const
Definition: ide_ctrl.hh:130
gem5::IdeController::ctrlOffset
uint32_t ctrlOffset
Definition: ide_ctrl.hh:194
gem5::IdeController::Channel::controller
IdeController * controller() const
Definition: ide_ctrl.hh:135
gem5::IdeController::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ide_ctrl.cc:387
gem5::IdeController::Channel::device1
IdeDisk * device1
Definition: ide_ctrl.hh:119
gem5::IdeController::Channel::accessCommand
void accessCommand(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:196
gem5::IdeController::Channel
Definition: ide_ctrl.hh:108
gem5::IdeController::Channel::postInterrupt
void postInterrupt()
Definition: ide_ctrl.cc:124
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
device.hh
PCI_DEVICE_SPECIFIC
#define PCI_DEVICE_SPECIFIC
Definition: pcireg.h:164
gem5::IdeController::Channel::unserialize
void unserialize(const std::string &base, CheckpointIn &cp)
Definition: ide_ctrl.cc:443
gem5::IdeController::Channel::selected
IdeDisk * selected() const
Definition: ide_ctrl.hh:134
gem5::Named
Interface for things with names.
Definition: named.hh:38
gem5::IdeController::Channel::accessControl
void accessControl(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:216
gem5::IdeController::ioShift
uint32_t ioShift
Definition: ide_ctrl.hh:194
gem5::IdeController::Channel::_pendingInterrupt
bool _pendingInterrupt
Definition: ide_ctrl.hh:127
gem5::IdeController::Channel::BMIRegs
Registers used for bus master interface.
Definition: ide_ctrl.hh:152
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::IdeController::Channel::accessBMI
void accessBMI(Addr offset, int size, uint8_t *data, bool read)
Definition: ide_ctrl.cc:230
gem5::IdeController::Channel::BMIRegs::command
BMICommandReg command
Definition: ide_ctrl.hh:160
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::IdeController::Channel::BMIRegs::status
BMIStatusReg status
Definition: ide_ctrl.hh:162
gem5::IdeController::IdeController
IdeController(const Params &p)
Definition: ide_ctrl.cc:73
bitunion.hh
gem5::IdeController::secondary
Channel secondary
Definition: ide_ctrl.hh:192
gem5::IdeController::dispatchAccess
void dispatchAccess(PacketPtr pkt, bool read)
Definition: ide_ctrl.cc:317
gem5::PciDevice
PCI device, base implementation is only config space.
Definition: device.hh:269
gem5::IdeController::PARAMS
PARAMS(IdeController)
gem5::IdeController::Channel::Channel
Channel(std::string new_name, IdeController *new_ctrl, bool new_primary)
Definition: ide_ctrl.cc:64
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:209
gem5::IdeController
Device model for an Intel PIIX4 IDE controller.
Definition: ide_ctrl.hh:52
gem5::IdeController::startStop
Bitfield< 0 > startStop
Definition: ide_ctrl.hh:66
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::IdeController::readConfig
Tick readConfig(PacketPtr pkt) override
Read from the PCI config space data that is stored locally.
Definition: ide_ctrl.cc:158
gem5::IdeController::active
Bitfield< 0 > active
Definition: ide_ctrl.hh:61
gem5::IdeController::BitUnion8
BitUnion8(BMIStatusReg) Bitfield< 6 > dmaCap0
gem5::IdeController::Channel::bmiRegs
struct gem5::IdeController::Channel::BMIRegs bmiRegs
gem5::IdeController::serialize
void serialize(CheckpointOut &cp) const override
Serialize this object to the given output stream.
Definition: ide_ctrl.cc:401
gem5::IdeController::Channel::BMIRegs::reset
void reset()
Definition: ide_ctrl.hh:155
gem5::IdeController::primary
Channel primary
Definition: ide_ctrl.hh:191
gem5::IdeController::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: ide_ctrl.cc:394
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::IdeController::Channel::clearInterrupt
void clearInterrupt()
Definition: ide_ctrl.cc:132
gem5::IdeController::clearInterrupt
virtual void clearInterrupt(bool is_primary)
Definition: ide_ctrl.cc:149
gem5::IdeController::postInterrupt
virtual void postInterrupt(bool is_primary)
Definition: ide_ctrl.cc:140
gem5::RegisterBank< ByteOrder::little >
gem5::IdeController::configSpaceRegs
EndBitUnion(BMICommandReg) class ConfigSpaceRegs ConfigSpaceRegs configSpaceRegs
Registers used in device specific PCI configuration.
Definition: ide_ctrl.hh:67
gem5::IdeController::unserialize
void unserialize(CheckpointIn &cp) override
Reconstruct the state of this object from a checkpoint.
Definition: ide_ctrl.cc:429
gem5::IdeController::Channel::BMIRegs::bmidtp
uint32_t bmidtp
Definition: ide_ctrl.hh:164
gem5::IdeController::intStatus
Bitfield< 2 > intStatus
Definition: ide_ctrl.hh:59
gem5::IdeController::Channel::setDmaComplete
void setDmaComplete()
Definition: ide_ctrl.cc:379
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::IdeController::Channel::ctrl
IdeController * ctrl
Definition: ide_ctrl.hh:111
gem5::IdeDisk
IDE Disk device model.
Definition: ide_disk.hh:216
gem5::ArmISA::rw
Bitfield< 31 > rw
Definition: misc_types.hh:253
gem5::IdeController::Channel::device0
IdeDisk * device0
IDE disks connected to this controller For more details about device0 and device1 see: https://en....
Definition: ide_ctrl.hh:119
gem5::IdeController::writeConfig
Tick writeConfig(PacketPtr pkt) override
Write to the PCI config space data that is stored locally.
Definition: ide_ctrl.cc:177
PCI_CONFIG_SIZE
#define PCI_CONFIG_SIZE
Definition: pcireg.h:165
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::IdeController::EndBitUnion
EndBitUnion(BMIStatusReg) BitUnion8(BMICommandReg) Bitfield< 3 > rw
gem5::IdeController::Channel::setDevice1
void setDevice1(IdeDisk *disk)
Definition: ide_ctrl.hh:145
gem5::IdeController::Channel::select
void select(bool select_device_1)
Definition: ide_ctrl.hh:168
gem5::IdeController::dmaError
Bitfield< 1 > dmaError
Definition: ide_ctrl.hh:60
reg_bank.hh
gem5::IdeController::Channel::primary
bool primary
Definition: ide_ctrl.hh:125

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