gem5::PlicOutput Struct Reference

NOTE: This implementation of PLIC is based on he riscv-plic-spec repository: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0. More...

#include <plic.hh>

Public Attributes
std::vector< uint32_t >	maxID
std::vector< uint32_t >	maxPriority

Detailed Description

NOTE: This implementation of PLIC is based on he riscv-plic-spec repository: https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0.

PLIC Latency Model MMIO changed (aside from threshold) => update internal states => calculate new output => schedule update (3 cycles delay) => update output & schedule next update => update xEIP lines

threshold changed => update xEIP lines

This ensures cycle-accurate values for MMIO accesses and xEIP lines

NOTE: check pending bit when returning maxID to avoid claiming by multiple contexts. Note that pending bits are not propagated through the 3-cycle delay.

TODO:

• Enforce access control (e.g. avoid S mode writing to M mode registers)

Definition at line 91 of file plic.hh.

Member Data Documentation

maxID

std::vector<uint32_t> gem5::PlicOutput::maxID

Definition at line 93 of file plic.hh.

Referenced by gem5::Plic::readClaim(), gem5::Plic::serialize(), gem5::Plic::unserialize(), and gem5::Plic::updateInt().

maxPriority

std::vector<uint32_t> gem5::PlicOutput::maxPriority

Definition at line 94 of file plic.hh.

Referenced by gem5::Plic::serialize(), gem5::Plic::unserialize(), and gem5::Plic::updateInt().

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The documentation for this struct was generated from the following file:

• dev/riscv/plic.hh