gem5  v21.1.0.2
plic.cc
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37 
38 
39 #include "dev/riscv/plic.hh"
40 
41 #include <algorithm>
42 
43 #include "cpu/base.hh"
44 #include "debug/Plic.hh"
45 #include "mem/packet.hh"
46 #include "mem/packet_access.hh"
47 #include "params/Plic.hh"
48 #include "sim/system.hh"
49 
50 namespace gem5
51 {
52 
53 using namespace RiscvISA;
54 
55 Plic::Plic(const Params &params) :
56  BasicPioDevice(params, params.pio_size),
57  system(params.system),
58  nSrc(params.n_src),
59  registers(params.name, pioAddr, this),
60  update([this]{updateOutput();}, name() + ".update")
61 {
62 }
63 
64 void
65 Plic::post(int src_id)
66 {
67  // Sanity check
68  assert(src_id < nSrc && src_id >= 0);
69 
70  // Update pending bit
71  int src_index = src_id >> 5;
72  int src_offset = src_id & 0x1F;
73 
74  uint32_t& pending = registers.pending[src_index].get();
75  std::bitset<32> pending_bits(pending);
76  pending_bits[src_offset] = 1;
77  pending = (uint32_t) pending_bits.to_ulong();
78 
79  // Update states
80  pendingPriority[src_id] = registers.priority[src_id].get();
81  for (int i = 0; i < nContext; i++) {
82  bool enabled = bits(registers.enable[i][src_index].get(), src_offset);
83  effPriority[i][src_id] = enabled ? pendingPriority[src_id] : 0;
84  }
85  DPRINTF(Plic,
86  "Int post request - source: %#x, current priority: %#x\n",
87  src_id, pendingPriority[src_id]);
88 
89  // Propagate output changes
91 }
92 
93 void
94 Plic::clear(int src_id)
95 {
96  // Sanity check
97  assert(src_id < nSrc);
98  assert(src_id >= 0);
99 
100  // Update pending bit
101  int src_index = src_id >> 5;
102  int src_offset = src_id & 0x1F;
103  uint32_t& pending = registers.pending[src_index].get();
104  std::bitset<32> pending_bits(pending);
105  pending_bits[src_offset] = 0;
106  pending = (uint32_t) pending_bits.to_ulong();
107 
108  // Update states
109  pendingPriority[src_id] = 0;
110  for (int i = 0; i < nContext; i++) {
111  effPriority[i][src_id] = 0;
112  }
113  DPRINTF(Plic,
114  "Int clear request - source: %#x, current priority: %#x\n",
115  src_id, pendingPriority[src_id]);
116 
117  // Propagate output changes
118  propagateOutput();
119 }
120 
121 Tick
123 {
124  // Check for atomic operation
125  bool is_atomic = pkt->isAtomicOp() && pkt->cmd == MemCmd::SwapReq;
126  DPRINTF(Plic,
127  "Read request - addr: %#x, size: %#x, atomic:%d\n",
128  pkt->getAddr(), pkt->getSize(), is_atomic);
129 
130  // Perform register read
131  registers.read(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
132 
133  if (is_atomic) {
134  // Perform atomic operation
135  (*(pkt->getAtomicOp()))(pkt->getPtr<uint8_t>());
136  return write(pkt);
137  } else {
138  pkt->makeResponse();
139  return pioDelay;
140  }
141 }
142 
143 Tick
145 {
146  DPRINTF(Plic,
147  "Write request - addr: %#x, size: %#x\n",
148  pkt->getAddr(), pkt->getSize());
149 
150  // Perform register write
151  registers.write(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
152 
153  // Propagate output changes
154  propagateOutput();
155 
156  // Apply threshold changes
157  updateInt();
158 
159  pkt->makeResponse();
160  return pioDelay;
161 }
162 
163 void
165 {
166  // Number of contexts
167  nContext = system->threads.size() * 2;
168  // Number of 32-bit pending registesrs where
169  // each bit correspondings to one interrupt source
170  nSrc32 = divCeil(nSrc, 32);
171 
172  // Setup register bank
173  registers.init();
174 
175  // Setup internal states
176  pendingPriority.resize(nSrc, 0x0);
177  for (int i = 0; i < nContext; i++) {
178  std::vector<uint32_t> context_priority(nSrc, 0x0);
179  effPriority.push_back(context_priority);
180  }
181  lastID.resize(nContext, 0x0);
182 
183  // Setup outputs
184  output = PlicOutput{
187 
188  DPRINTF(Plic,
189  "Device init - %d contexts, %d sources, %d pending registers\n",
190  nContext, nSrc, nSrc32);
191 
193 }
194 
195 void
197 {
198  using namespace std::placeholders;
199 
200  // Calculate reserved space size
201  const size_t reserve0_size = pendingStart - plic->nSrc * 4;
202  reserved.emplace_back("reserved0", reserve0_size);
203  const size_t reserve1_size = enableStart - pendingStart
204  - plic->nSrc32 * 4;
205  reserved.emplace_back("reserved1", reserve1_size);
206  const size_t reserve2_size = thresholdStart - enableStart
208  reserved.emplace_back("reserved2", reserve2_size);
209  const size_t reserve3_size = plic->pioSize - thresholdStart
211  reserved.emplace_back("reserved3", reserve3_size);
212 
213  // Sanity check
214  assert(plic->pioSize >= thresholdStart
216  assert((int) plic->pioSize <= maxBankSize);
217 
218  // Calculate hole sizes
219  const size_t enable_hole_size = enablePadding - plic->nSrc32 * 4;
220  const size_t claim_hole_size = thresholdPadding - 0x8;
221 
222  // Initialize registers
223  for (int i = 0; i < plic->nSrc; i++) {
224  priority.emplace_back(
225  std::string("priority") + std::to_string(i), 0);
226  }
227  for (int i = 0; i < plic->nSrc32; i++) {
228  pending.emplace_back(
229  std::string("pending") + std::to_string(i), 0);
230  }
231  for (int i = 0; i < plic->nContext; i++) {
232 
233  enable.push_back(std::vector<Register32>());
234  for (int j = 0; j < plic->nSrc32; j++) {
235  enable[i].emplace_back(
236  std::string("enable") + std::to_string(i)
237  + "_" + std::to_string(j), 0);
238  }
239  enable_holes.emplace_back(
240  std::string("enable_hole") + std::to_string(i), enable_hole_size);
241 
242  threshold.emplace_back(
243  std::string("threshold") + std::to_string(i), 0);
244  claim.emplace_back(
245  std::string("claim") + std::to_string(i), 0);
246  claim_holes.emplace_back(
247  std::string("claim_hole") + std::to_string(i), claim_hole_size);
248  }
249 
250  // Add registers to bank
251  // Priority
252  for (int i = 0; i < plic->nSrc; i++) {
253  auto write_cb = std::bind(&Plic::writePriority, plic, _1, _2, i);
254  priority[i].writer(write_cb);
256  }
257  addRegister(reserved[0]);
258 
259  // Pending
260  for (int i = 0; i < plic->nSrc32; i++) {
261  pending[i].readonly();
263  }
264  addRegister(reserved[1]);
265 
266  // Enable
267  for (int i = 0; i < plic->nContext; i++) {
268  for (int j = 0; j < plic->nSrc32; j++) {
269  auto write_cb = std::bind(&Plic::writeEnable, plic, _1, _2, j, i);
270  enable[i][j].writer(write_cb);
271  addRegister(enable[i][j]);
272  }
274  }
275  addRegister(reserved[2]);
276 
277  // Threshold and claim
278  for (int i = 0; i < plic->nContext; i++) {
279  auto threshold_cb = std::bind(&Plic::writeThreshold, plic, _1, _2, i);
280  threshold[i].writer(threshold_cb);
281  auto read_cb = std::bind(&Plic::readClaim, plic, _1, i);
282  auto write_cb = std::bind(&Plic::writeClaim, plic, _1, _2, i);
283  claim[i].reader(read_cb)
284  .writer(write_cb);
286  addRegister(claim[i]);
288  }
289  addRegister(reserved[3]);
290 }
291 
292 void
293 Plic::writePriority(Register32& reg, const uint32_t& data, const int src_id)
294 {
295  reg.update(data);
296 
297  // Calculate indices
298  int src_index = src_id >> 5;
299  int src_offset = src_id & 0x1F;
300 
301  // Update states
302  bool pending = bits(registers.pending[src_index].get(), src_offset);
303  pendingPriority[src_id] = pending ? reg.get() : 0;
304  for (int i = 0; i < nContext; i++) {
305  bool enabled = bits(
306  registers.enable[i][src_index].get(), src_offset);
307  effPriority[i][src_id] = enabled ? pendingPriority[src_id] : 0;
308  }
309 
310  DPRINTF(Plic,
311  "Priority updated - src: %d, val: %d\n",
312  src_id, reg.get());
313 }
314 
315 void
317  const int src32_id, const int context_id)
318 {
319  reg.update(data);
320 
321  for (int i = 0; i < 32; i ++) {
322  int src_id = (src32_id << 5) + i;
323  if (src_id < nSrc) {
324  effPriority[context_id][src_id] =
325  bits(reg.get(), i) ? pendingPriority[src_id] : 0;
326  }
327  }
328  DPRINTF(Plic,
329  "Enable updated - context: %d, src32: %d, val: %#x\n",
330  context_id, src32_id, reg.get());
331 }
332 
333 void
335  const int context_id)
336 {
337  DPRINTF(Plic,
338  "Threshold updated - context: %d, val: %d\n",
339  context_id, reg.get());
340 }
341 
342 uint32_t
343 Plic::readClaim(Register32& reg, const int context_id)
344 {
345  if (lastID[context_id] == 0) {
346  // Calculate indices
347  uint32_t max_int_id = output.maxID[context_id];
348  int src_index = max_int_id >> 5;
349  int src_offset = max_int_id & 0x1F;
350 
351  // Check pending bits
352  if (bits(registers.pending[src_index].get(), src_offset)) {
353  lastID[context_id] = max_int_id;
354  DPRINTF(Plic,
355  "Claim success - context: %d, interrupt ID: %d\n",
356  context_id, max_int_id);
357  clear(max_int_id);
358  reg.update(max_int_id);
359  return reg.get();
360  } else {
361  DPRINTF(Plic,
362  "Claim already cleared - context: %d, interrupt ID: %d\n",
363  context_id, max_int_id);
364  return 0;
365  }
366  } else {
367  warn("PLIC claim repeated (not completed) - context: %d, last: %d",
368  context_id, lastID[context_id]);
369  return lastID[context_id];
370  }
371 }
372 
373 void
374 Plic::writeClaim(Register32& reg, const uint32_t& data, const int context_id)
375 {
376  reg.update(data);
377 
382  assert(lastID[context_id] == reg.get());
383  lastID[context_id] = 0;
384  DPRINTF(Plic,
385  "Complete - context: %d, interrupt ID: %d\n",
386  context_id, reg.get());
387  updateInt();
388 }
389 
390 void
392 {
393  // Calculate new output
394  PlicOutput new_output{
397  uint32_t max_id;
398  uint32_t max_priority;
399  for (int i = 0; i < nContext; i++) {
400  max_id = max_element(effPriority[i].begin(),
401  effPriority[i].end()) - effPriority[i].begin();
402  max_priority = effPriority[i][max_id];
403  new_output.maxID[i] = max_id;
404  new_output.maxPriority[i] = max_priority;
405  }
406 
407  // Add new output to outputQueue
408  Tick next_update = curTick() + cyclesToTicks(Cycles(3));
409  if (outputQueue.find(next_update) != outputQueue.end()) {
410  outputQueue[next_update] = new_output;
411  } else {
412  outputQueue.insert({next_update, new_output});
413  }
414 
415  // Schedule next update event
416  if (!update.scheduled()) {
417  DPRINTF(Plic, "Update scheduled - tick: %d\n", next_update);
418  schedule(update, next_update);
419  }
420 }
421 
422 void
424 {
425  DPRINTF(Plic, "Update triggered\n");
426  // Set current output to new output
427  output = outputQueue.begin()->second;
428  outputQueue.erase(outputQueue.begin()->first);
429 
430  // Schedule next update event (if any)
431  if (!outputQueue.empty()) {
432  DPRINTF(Plic, "Update scheduled - tick: %d\n",
433  outputQueue.begin()->first);
434  schedule(update, outputQueue.begin()->first);
435  }
436 
437  updateInt();
438 }
439 
440 void
442 {
443  // Update xEIP lines
444  for (int i = 0; i < nContext; i++) {
445  int thread_id = i >> 1;
446  int int_id = (i & 1) ?
448 
449  auto tc = system->threads[thread_id];
450  uint32_t max_id = output.maxID[i];
451  uint32_t priority = output.maxPriority[i];
452  uint32_t threshold = registers.threshold[i].get();
453  if (priority > threshold && max_id > 0 && lastID[i] == 0) {
454  DPRINTF(Plic, "Int posted - thread: %d, int id: %d, ",
455  thread_id, int_id);
456  DPRINTFR(Plic, "pri: %d, thres: %d\n", priority, threshold);
457  tc->getCpuPtr()->postInterrupt(tc->threadId(), int_id, 0);
458  } else {
459  if (priority > 0) {
460  DPRINTF(Plic, "Int filtered - thread: %d, int id: %d, ",
461  thread_id, int_id);
462  DPRINTFR(Plic, "pri: %d, thres: %d\n", priority, threshold);
463  }
464  tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_id, 0);
465  }
466  }
467 }
468 
469 void
471 {
472  int n_outputs = 0;
473 
474  for (auto const &reg: registers.pending) {
475  paramOut(cp, reg.name(), reg);
476  }
477  for (auto const &reg: registers.priority) {
478  paramOut(cp, reg.name(), reg);
479  }
480  for (auto const &reg: registers.enable) {
481  for (auto const &reg_inner: reg) {
482  paramOut(cp, reg_inner.name(), reg_inner);
483  }
484  }
485  for (auto const &reg: registers.threshold) {
486  paramOut(cp, reg.name(), reg);
487  }
488  for (auto const &reg: registers.claim) {
489  paramOut(cp, reg.name(), reg);
490  }
491  for (auto const & it : outputQueue) {
492  paramOut(cp, std::string("output_tick") +
493  std::to_string(n_outputs), it.first);
494  arrayParamOut(cp, std::string("output_id") +
495  std::to_string(n_outputs), it.second.maxID);
496  arrayParamOut(cp, std::string("output_pri") +
497  std::to_string(n_outputs), it.second.maxPriority);
498  n_outputs++;
499  }
500  SERIALIZE_SCALAR(n_outputs);
504  for (int i=0; i < effPriority.size(); i++) {
505  arrayParamOut(cp, std::string("effPriority") +
507  }
509 }
510 
511 void
513 {
514  int n_outputs;
515  UNSERIALIZE_SCALAR(n_outputs);
516 
517  for (auto &reg: registers.pending) {
518  paramIn(cp, reg.name(), reg);
519  }
520  for (auto &reg: registers.priority) {
521  paramIn(cp, reg.name(), reg);
522  }
523  for (auto &reg: registers.enable) {
524  for (auto &reg_inner: reg) {
525  paramIn(cp, reg_inner.name(), reg_inner);
526  }
527  }
528  for (auto &reg: registers.threshold) {
529  paramIn(cp, reg.name(), reg);
530  }
531  for (auto &reg: registers.claim) {
532  paramIn(cp, reg.name(), reg);
533  }
534  for (int i = 0; i < n_outputs; i++) {
535  Tick output_tick;
536  std::vector<uint32_t> output_id;
537  std::vector<uint32_t> output_pri;
538  paramIn(cp, std::string("output_tick") +
539  std::to_string(i), output_tick);
540  arrayParamIn(cp, std::string("output_id") +
541  std::to_string(i), output_id);
542  arrayParamIn(cp, std::string("output_pri") +
543  std::to_string(i), output_pri);
544  outputQueue[output_tick] = PlicOutput{output_id, output_pri};
545  }
546  if (!outputQueue.empty()) {
547  schedule(update, outputQueue.begin()->first);
548  }
552  for (int i=0; i < effPriority.size(); i++) {
553  arrayParamIn(cp, std::string("effPriority") +
555  }
557  updateInt();
558 }
559 
560 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Plic::nSrc32
int nSrc32
Number of 32-bit pending registers needed = ceil(nSrc / 32)
Definition: plic.hh:109
gem5::RiscvISA::INT_EXT_MACHINE
@ INT_EXT_MACHINE
Definition: faults.hh:95
gem5::Packet::isAtomicOp
bool isAtomicOp() const
Definition: packet.hh:820
gem5::Plic::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: plic.cc:470
warn
#define warn(...)
Definition: logging.hh:245
gem5::System::Threads::size
int size() const
Definition: system.hh:216
gem5::Plic::PlicRegisters::enable_holes
std::vector< RegisterRaz > enable_holes
Definition: plic.hh:203
system.hh
gem5::Plic::nContext
int nContext
Number of interrupt contexts = nThread * 2 e.g.
Definition: plic.hh:117
DPRINTFR
#define DPRINTFR(x,...)
Definition: trace.hh:200
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Plic::PlicRegisters::enable
std::vector< std::vector< Register32 > > enable
Definition: plic.hh:200
gem5::MemCmd::SwapReq
@ SwapReq
Definition: packet.hh:115
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::Plic::outputQueue
std::map< Tick, PlicOutput > outputQueue
Definition: plic.hh:260
gem5::Plic::post
void post(int src_id)
Interrupt interface.
Definition: plic.cc:65
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::Plic::PlicRegisters::thresholdStart
const Addr thresholdStart
Definition: plic.hh:192
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Plic::writePriority
void writePriority(Register32 &reg, const uint32_t &data, const int src_id)
Register read / write callbacks.
Definition: plic.cc:293
gem5::Plic::PlicRegisters::enablePadding
const Addr enablePadding
Definition: plic.hh:193
gem5::Plic::registers
gem5::Plic::PlicRegisters registers
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::Plic::nSrc
int nSrc
Definition: plic.hh:104
gem5::Plic::pendingPriority
std::vector< uint32_t > pendingPriority
Definition: plic.hh:241
gem5::RegisterBank::write
virtual void write(Addr addr, const void *buf, Addr bytes)
Definition: reg_bank.hh:884
gem5::Plic
Definition: plic.hh:97
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::Plic::PlicRegisters::pending
std::vector< Register32 > pending
Definition: plic.hh:199
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
std::vector< uint32_t >
gem5::Plic::Plic
Plic(const Params &params)
Definition: plic.cc:55
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::Plic::updateOutput
void updateOutput()
Trigger:
Definition: plic.cc:423
gem5::Plic::PlicRegisters::enableStart
const Addr enableStart
Definition: plic.hh:191
gem5::Plic::init
void init() override
SimObject functions.
Definition: plic.cc:164
packet.hh
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::Packet::getAtomicOp
AtomicOpFunctor * getAtomicOp() const
Accessor function to atomic op.
Definition: packet.hh:819
gem5::RiscvISA::INT_EXT_SUPER
@ INT_EXT_SUPER
Definition: faults.hh:94
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::Plic::PlicRegisters::reserved
std::vector< RegisterRaz > reserved
Definition: plic.hh:205
gem5::Plic::system
System * system
Definition: plic.hh:101
gem5::Plic::PlicRegisters::threshold
std::vector< Register32 > threshold
Definition: plic.hh:201
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
gem5::Plic::PlicRegisters::thresholdPadding
const Addr thresholdPadding
Definition: plic.hh:194
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Plic::writeThreshold
void writeThreshold(Register32 &reg, const uint32_t &data, const int context_id)
Definition: plic.cc:334
gem5::PlicOutput::maxID
std::vector< uint32_t > maxID
Definition: plic.hh:93
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::Plic::updateInt
void updateInt()
Trigger:
Definition: plic.cc:441
gem5::Plic::effPriority
std::vector< std::vector< uint32_t > > effPriority
Definition: plic.hh:243
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Plic::writeClaim
void writeClaim(Register32 &reg, const uint32_t &data, const int context_id)
Definition: plic.cc:374
gem5::Plic::clear
void clear(int src_id)
Definition: plic.cc:94
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:361
gem5::PlicOutput
NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive....
Definition: plic.hh:91
gem5::Plic::propagateOutput
void propagateOutput()
Trigger:
Definition: plic.cc:391
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::Plic::PlicRegisters::claim
std::vector< Register32 > claim
Definition: plic.hh:202
packet_access.hh
gem5::arrayParamOut
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void()) arrayParamOut(CheckpointOut &os, const std::string &name, const T &param)
Definition: serialize.hh:409
gem5::PlicOutput::maxPriority
std::vector< uint32_t > maxPriority
Definition: plic.hh:94
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:280
gem5::divCeil
static constexpr T divCeil(const T &a, const U &b)
Definition: intmath.hh:110
gem5::RegisterBank< ByteOrder::little >::addRegister
void addRegister(RegisterBase &reg)
Definition: reg_bank.hh:820
gem5::Plic::output
PlicOutput output
Definition: plic.hh:246
gem5::Plic::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: plic.cc:144
gem5::Plic::read
Tick read(PacketPtr pkt) override
PioDevice funcitons.
Definition: plic.cc:122
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Plic::PlicRegisters::init
void init()
Definition: plic.cc:196
gem5::RegisterBank::read
virtual void read(Addr addr, void *buf, Addr bytes)
Definition: reg_bank.hh:827
gem5::Plic::PlicRegisters::priority
std::vector< Register32 > priority
Definition: plic.hh:198
gem5::Plic::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: plic.cc:512
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
base.hh
gem5::System::threads
Threads threads
Definition: system.hh:316
gem5::Plic::update
EventFunctionWrapper update
Definition: plic.hh:261
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1031
gem5::Plic::writeEnable
void writeEnable(Register32 &reg, const uint32_t &data, const int src32_id, const int context_id)
Definition: plic.cc:316
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::Plic::PlicRegisters::plic
Plic * plic
Definition: plic.hh:211
gem5::Plic::PlicRegisters::maxBankSize
const Addr maxBankSize
Definition: plic.hh:195
plic.hh
gem5::BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Plic::PlicRegisters::claim_holes
std::vector< RegisterRaz > claim_holes
Definition: plic.hh:204
gem5::Plic::lastID
std::vector< uint32_t > lastID
Definition: plic.hh:245
gem5::arrayParamIn
void arrayParamIn(CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
Definition: circlebuf.hh:257
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
gem5::Plic::Register32
PlicRegisters::Register32 Register32
Definition: plic.hh:217
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Plic::PlicRegisters::pendingStart
const Addr pendingStart
Definition: plic.hh:190
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::Plic::readClaim
uint32_t readClaim(Register32 &reg, const int context_id)
Definition: plic.cc:343
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1184

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