gem5  v22.0.0.1
plic.cc
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37 
38 
39 #include "dev/riscv/plic.hh"
40 
41 #include <algorithm>
42 
43 #include "cpu/base.hh"
44 #include "debug/Plic.hh"
45 #include "mem/packet.hh"
46 #include "mem/packet_access.hh"
47 #include "params/Plic.hh"
48 #include "sim/system.hh"
49 
50 namespace gem5
51 {
52 
53 using namespace RiscvISA;
54 
55 Plic::Plic(const Params &params) :
56  BasicPioDevice(params, params.pio_size),
57  system(params.system),
58  nSrc(params.n_src),
59  nContext(params.n_contexts),
60  registers(params.name, pioAddr, this),
61  update([this]{updateOutput();}, name() + ".update")
62 {
63 }
64 
65 void
66 Plic::post(int src_id)
67 {
68  // Sanity check
69  assert(src_id < nSrc && src_id >= 0);
70 
71  // Update pending bit
72  int src_index = src_id >> 5;
73  int src_offset = src_id & 0x1F;
74 
75  uint32_t& pending = registers.pending[src_index].get();
76  std::bitset<32> pending_bits(pending);
77  pending_bits[src_offset] = 1;
78  pending = (uint32_t) pending_bits.to_ulong();
79 
80  // Update states
81  pendingPriority[src_id] = registers.priority[src_id].get();
82  for (int i = 0; i < nContext; i++) {
83  bool enabled = bits(registers.enable[i][src_index].get(), src_offset);
84  effPriority[i][src_id] = enabled ? pendingPriority[src_id] : 0;
85  }
86  DPRINTF(Plic,
87  "Int post request - source: %#x, current priority: %#x\n",
88  src_id, pendingPriority[src_id]);
89 
90  // Propagate output changes
92 }
93 
94 void
95 Plic::clear(int src_id)
96 {
97  // Sanity check
98  assert(src_id < nSrc);
99  assert(src_id >= 0);
100 
101  // Update pending bit
102  int src_index = src_id >> 5;
103  int src_offset = src_id & 0x1F;
104  uint32_t& pending = registers.pending[src_index].get();
105  std::bitset<32> pending_bits(pending);
106  pending_bits[src_offset] = 0;
107  pending = (uint32_t) pending_bits.to_ulong();
108 
109  // Update states
110  pendingPriority[src_id] = 0;
111  for (int i = 0; i < nContext; i++) {
112  effPriority[i][src_id] = 0;
113  }
114  DPRINTF(Plic,
115  "Int clear request - source: %#x, current priority: %#x\n",
116  src_id, pendingPriority[src_id]);
117 
118  // Propagate output changes
119  propagateOutput();
120 }
121 
122 Tick
124 {
125  // Check for atomic operation
126  bool is_atomic = pkt->isAtomicOp() && pkt->cmd == MemCmd::SwapReq;
127  DPRINTF(Plic,
128  "Read request - addr: %#x, size: %#x, atomic:%d\n",
129  pkt->getAddr(), pkt->getSize(), is_atomic);
130 
131  // Perform register read
132  registers.read(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
133 
134  if (is_atomic) {
135  // Perform atomic operation
136  (*(pkt->getAtomicOp()))(pkt->getPtr<uint8_t>());
137  return write(pkt);
138  } else {
139  pkt->makeResponse();
140  return pioDelay;
141  }
142 }
143 
144 Tick
146 {
147  DPRINTF(Plic,
148  "Write request - addr: %#x, size: %#x\n",
149  pkt->getAddr(), pkt->getSize());
150 
151  // Perform register write
152  registers.write(pkt->getAddr(), pkt->getPtr<void>(), pkt->getSize());
153 
154  // Propagate output changes
155  propagateOutput();
156 
157  // Apply threshold changes
158  updateInt();
159 
160  pkt->makeResponse();
161  return pioDelay;
162 }
163 
164 void
166 {
167  // Number of 32-bit pending registesrs where
168  // each bit correspondings to one interrupt source
169  nSrc32 = divCeil(nSrc, 32);
170 
171  // Setup register bank
172  registers.init();
173 
174  // Setup internal states
175  pendingPriority.resize(nSrc, 0x0);
176  for (int i = 0; i < nContext; i++) {
177  std::vector<uint32_t> context_priority(nSrc, 0x0);
178  effPriority.push_back(context_priority);
179  }
180  lastID.resize(nContext, 0x0);
181 
182  // Setup outputs
183  output = PlicOutput{
186 
187  DPRINTF(Plic,
188  "Device init - %d contexts, %d sources, %d pending registers\n",
189  nContext, nSrc, nSrc32);
190 
192 }
193 
194 void
196 {
197  using namespace std::placeholders;
198 
199  // Calculate reserved space size
200  const size_t reserve0_size = pendingStart - plic->nSrc * 4;
201  reserved.emplace_back("reserved0", reserve0_size);
202  const size_t reserve1_size = enableStart - pendingStart
203  - plic->nSrc32 * 4;
204  reserved.emplace_back("reserved1", reserve1_size);
205  const size_t reserve2_size = thresholdStart - enableStart
207  reserved.emplace_back("reserved2", reserve2_size);
208  const size_t reserve3_size = plic->pioSize - thresholdStart
210  reserved.emplace_back("reserved3", reserve3_size);
211 
212  // Sanity check
213  assert(plic->pioSize >= thresholdStart
215  assert((int) plic->pioSize <= maxBankSize);
216 
217  // Calculate hole sizes
218  const size_t enable_hole_size = enablePadding - plic->nSrc32 * 4;
219  const size_t claim_hole_size = thresholdPadding - 0x8;
220 
221  // Initialize registers
222  for (int i = 0; i < plic->nSrc; i++) {
223  priority.emplace_back(
224  std::string("priority") + std::to_string(i), 0);
225  }
226  for (int i = 0; i < plic->nSrc32; i++) {
227  pending.emplace_back(
228  std::string("pending") + std::to_string(i), 0);
229  }
230  for (int i = 0; i < plic->nContext; i++) {
231 
232  enable.push_back(std::vector<Register32>());
233  for (int j = 0; j < plic->nSrc32; j++) {
234  enable[i].emplace_back(
235  std::string("enable") + std::to_string(i)
236  + "_" + std::to_string(j), 0);
237  }
238  enable_holes.emplace_back(
239  std::string("enable_hole") + std::to_string(i), enable_hole_size);
240 
241  threshold.emplace_back(
242  std::string("threshold") + std::to_string(i), 0);
243  claim.emplace_back(
244  std::string("claim") + std::to_string(i), 0);
245  claim_holes.emplace_back(
246  std::string("claim_hole") + std::to_string(i), claim_hole_size);
247  }
248 
249  // Add registers to bank
250  // Priority
251  for (int i = 0; i < plic->nSrc; i++) {
252  auto write_cb = std::bind(&Plic::writePriority, plic, _1, _2, i);
253  priority[i].writer(write_cb);
255  }
256  addRegister(reserved[0]);
257 
258  // Pending
259  for (int i = 0; i < plic->nSrc32; i++) {
260  pending[i].readonly();
262  }
263  addRegister(reserved[1]);
264 
265  // Enable
266  for (int i = 0; i < plic->nContext; i++) {
267  for (int j = 0; j < plic->nSrc32; j++) {
268  auto write_cb = std::bind(&Plic::writeEnable, plic, _1, _2, j, i);
269  enable[i][j].writer(write_cb);
270  addRegister(enable[i][j]);
271  }
273  }
274  addRegister(reserved[2]);
275 
276  // Threshold and claim
277  for (int i = 0; i < plic->nContext; i++) {
278  auto threshold_cb = std::bind(&Plic::writeThreshold, plic, _1, _2, i);
279  threshold[i].writer(threshold_cb);
280  auto read_cb = std::bind(&Plic::readClaim, plic, _1, i);
281  auto write_cb = std::bind(&Plic::writeClaim, plic, _1, _2, i);
282  claim[i].reader(read_cb)
283  .writer(write_cb);
285  addRegister(claim[i]);
287  }
288  addRegister(reserved[3]);
289 }
290 
291 void
292 Plic::writePriority(Register32& reg, const uint32_t& data, const int src_id)
293 {
294  reg.update(data);
295 
296  // Calculate indices
297  int src_index = src_id >> 5;
298  int src_offset = src_id & 0x1F;
299 
300  // Update states
301  bool pending = bits(registers.pending[src_index].get(), src_offset);
302  pendingPriority[src_id] = pending ? reg.get() : 0;
303  for (int i = 0; i < nContext; i++) {
304  bool enabled = bits(
305  registers.enable[i][src_index].get(), src_offset);
306  effPriority[i][src_id] = enabled ? pendingPriority[src_id] : 0;
307  }
308 
309  DPRINTF(Plic,
310  "Priority updated - src: %d, val: %d\n",
311  src_id, reg.get());
312 }
313 
314 void
316  const int src32_id, const int context_id)
317 {
318  reg.update(data);
319 
320  for (int i = 0; i < 32; i ++) {
321  int src_id = (src32_id << 5) + i;
322  if (src_id < nSrc) {
323  effPriority[context_id][src_id] =
324  bits(reg.get(), i) ? pendingPriority[src_id] : 0;
325  }
326  }
327  DPRINTF(Plic,
328  "Enable updated - context: %d, src32: %d, val: %#x\n",
329  context_id, src32_id, reg.get());
330 }
331 
332 void
334  const int context_id)
335 {
336  DPRINTF(Plic,
337  "Threshold updated - context: %d, val: %d\n",
338  context_id, reg.get());
339 }
340 
341 uint32_t
342 Plic::readClaim(Register32& reg, const int context_id)
343 {
344  if (lastID[context_id] == 0) {
345  // Calculate indices
346  uint32_t max_int_id = output.maxID[context_id];
347  int src_index = max_int_id >> 5;
348  int src_offset = max_int_id & 0x1F;
349 
350  // Check pending bits
351  if (bits(registers.pending[src_index].get(), src_offset)) {
352  lastID[context_id] = max_int_id;
353  DPRINTF(Plic,
354  "Claim success - context: %d, interrupt ID: %d\n",
355  context_id, max_int_id);
356  clear(max_int_id);
357  reg.update(max_int_id);
358  return reg.get();
359  } else {
360  DPRINTF(Plic,
361  "Claim already cleared - context: %d, interrupt ID: %d\n",
362  context_id, max_int_id);
363  return 0;
364  }
365  } else {
366  warn("PLIC claim repeated (not completed) - context: %d, last: %d",
367  context_id, lastID[context_id]);
368  return lastID[context_id];
369  }
370 }
371 
372 void
373 Plic::writeClaim(Register32& reg, const uint32_t& data, const int context_id)
374 {
375  reg.update(data);
376 
381  assert(lastID[context_id] == reg.get());
382  lastID[context_id] = 0;
383  DPRINTF(Plic,
384  "Complete - context: %d, interrupt ID: %d\n",
385  context_id, reg.get());
386  updateInt();
387 }
388 
389 void
391 {
392  // Calculate new output
393  PlicOutput new_output{
396  uint32_t max_id;
397  uint32_t max_priority;
398  for (int i = 0; i < nContext; i++) {
399  max_id = max_element(effPriority[i].begin(),
400  effPriority[i].end()) - effPriority[i].begin();
401  max_priority = effPriority[i][max_id];
402  new_output.maxID[i] = max_id;
403  new_output.maxPriority[i] = max_priority;
404  }
405 
406  // Add new output to outputQueue
407  Tick next_update = curTick() + cyclesToTicks(Cycles(3));
408  if (outputQueue.find(next_update) != outputQueue.end()) {
409  outputQueue[next_update] = new_output;
410  } else {
411  outputQueue.insert({next_update, new_output});
412  }
413 
414  // Schedule next update event
415  if (!update.scheduled()) {
416  DPRINTF(Plic, "Update scheduled - tick: %d\n", next_update);
417  schedule(update, next_update);
418  }
419 }
420 
421 void
423 {
424  DPRINTF(Plic, "Update triggered\n");
425  // Set current output to new output
426  output = outputQueue.begin()->second;
427  outputQueue.erase(outputQueue.begin()->first);
428 
429  // Schedule next update event (if any)
430  if (!outputQueue.empty()) {
431  DPRINTF(Plic, "Update scheduled - tick: %d\n",
432  outputQueue.begin()->first);
433  schedule(update, outputQueue.begin()->first);
434  }
435 
436  updateInt();
437 }
438 
439 void
441 {
442  // Update xEIP lines
443  for (int i = 0; i < nContext; i++) {
444  int thread_id = i >> 1;
445  int int_id = (i & 1) ?
447 
448  auto tc = system->threads[thread_id];
449  uint32_t max_id = output.maxID[i];
450  uint32_t priority = output.maxPriority[i];
451  uint32_t threshold = registers.threshold[i].get();
452  if (priority > threshold && max_id > 0 && lastID[i] == 0) {
453  DPRINTF(Plic, "Int posted - thread: %d, int id: %d, ",
454  thread_id, int_id);
455  DPRINTFR(Plic, "pri: %d, thres: %d\n", priority, threshold);
456  tc->getCpuPtr()->postInterrupt(tc->threadId(), int_id, 0);
457  } else {
458  if (priority > 0) {
459  DPRINTF(Plic, "Int filtered - thread: %d, int id: %d, ",
460  thread_id, int_id);
461  DPRINTFR(Plic, "pri: %d, thres: %d\n", priority, threshold);
462  }
463  tc->getCpuPtr()->clearInterrupt(tc->threadId(), int_id, 0);
464  }
465  }
466 }
467 
468 void
470 {
471  int n_outputs = 0;
472 
473  for (auto const &reg: registers.pending) {
474  paramOut(cp, reg.name(), reg);
475  }
476  for (auto const &reg: registers.priority) {
477  paramOut(cp, reg.name(), reg);
478  }
479  for (auto const &reg: registers.enable) {
480  for (auto const &reg_inner: reg) {
481  paramOut(cp, reg_inner.name(), reg_inner);
482  }
483  }
484  for (auto const &reg: registers.threshold) {
485  paramOut(cp, reg.name(), reg);
486  }
487  for (auto const &reg: registers.claim) {
488  paramOut(cp, reg.name(), reg);
489  }
490  for (auto const & it : outputQueue) {
491  paramOut(cp, std::string("output_tick") +
492  std::to_string(n_outputs), it.first);
493  arrayParamOut(cp, std::string("output_id") +
494  std::to_string(n_outputs), it.second.maxID);
495  arrayParamOut(cp, std::string("output_pri") +
496  std::to_string(n_outputs), it.second.maxPriority);
497  n_outputs++;
498  }
499  SERIALIZE_SCALAR(n_outputs);
503  for (int i=0; i < effPriority.size(); i++) {
504  arrayParamOut(cp, std::string("effPriority") +
506  }
508 }
509 
510 void
512 {
513  int n_outputs;
514  UNSERIALIZE_SCALAR(n_outputs);
515 
516  for (auto &reg: registers.pending) {
517  paramIn(cp, reg.name(), reg);
518  }
519  for (auto &reg: registers.priority) {
520  paramIn(cp, reg.name(), reg);
521  }
522  for (auto &reg: registers.enable) {
523  for (auto &reg_inner: reg) {
524  paramIn(cp, reg_inner.name(), reg_inner);
525  }
526  }
527  for (auto &reg: registers.threshold) {
528  paramIn(cp, reg.name(), reg);
529  }
530  for (auto &reg: registers.claim) {
531  paramIn(cp, reg.name(), reg);
532  }
533  for (int i = 0; i < n_outputs; i++) {
534  Tick output_tick;
535  std::vector<uint32_t> output_id;
536  std::vector<uint32_t> output_pri;
537  paramIn(cp, std::string("output_tick") +
538  std::to_string(i), output_tick);
539  arrayParamIn(cp, std::string("output_id") +
540  std::to_string(i), output_id);
541  arrayParamIn(cp, std::string("output_pri") +
542  std::to_string(i), output_pri);
543  outputQueue[output_tick] = PlicOutput{output_id, output_pri};
544  }
545  if (!outputQueue.empty()) {
546  schedule(update, outputQueue.begin()->first);
547  }
551  for (int i=0; i < effPriority.size(); i++) {
552  arrayParamIn(cp, std::string("effPriority") +
554  }
556  updateInt();
557 }
558 
559 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Plic::nSrc32
int nSrc32
Number of 32-bit pending registers needed = ceil(nSrc / 32)
Definition: plic.hh:109
gem5::RiscvISA::INT_EXT_MACHINE
@ INT_EXT_MACHINE
Definition: faults.hh:95
gem5::Packet::isAtomicOp
bool isAtomicOp() const
Definition: packet.hh:829
gem5::Plic::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: plic.cc:469
warn
#define warn(...)
Definition: logging.hh:246
gem5::Plic::PlicRegisters::enable_holes
std::vector< RegisterRaz > enable_holes
Definition: plic.hh:203
system.hh
gem5::Plic::nContext
int nContext
Number of interrupt contexts = nThread * 2 e.g.
Definition: plic.hh:117
DPRINTFR
#define DPRINTFR(x,...)
Definition: trace.hh:200
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Plic::PlicRegisters::enable
std::vector< std::vector< Register32 > > enable
Definition: plic.hh:200
gem5::MemCmd::SwapReq
@ SwapReq
Definition: packet.hh:119
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::Plic::outputQueue
std::map< Tick, PlicOutput > outputQueue
Definition: plic.hh:260
gem5::Plic::post
void post(int src_id)
Interrupt interface.
Definition: plic.cc:66
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:634
gem5::Plic::PlicRegisters::thresholdStart
const Addr thresholdStart
Definition: plic.hh:192
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Plic::writePriority
void writePriority(Register32 &reg, const uint32_t &data, const int src_id)
Register read / write callbacks.
Definition: plic.cc:292
gem5::Plic::PlicRegisters::enablePadding
const Addr enablePadding
Definition: plic.hh:193
gem5::Plic::registers
gem5::Plic::PlicRegisters registers
sc_dt::to_string
const std::string to_string(sc_enc enc)
Definition: sc_fxdefs.cc:91
gem5::Plic::nSrc
int nSrc
Definition: plic.hh:104
gem5::Plic::pendingPriority
std::vector< uint32_t > pendingPriority
Definition: plic.hh:241
gem5::RegisterBank::write
virtual void write(Addr addr, const void *buf, Addr bytes)
Definition: reg_bank.hh:884
gem5::Plic
Definition: plic.hh:97
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::Plic::PlicRegisters::pending
std::vector< Register32 > pending
Definition: plic.hh:199
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
std::vector< uint32_t >
gem5::Plic::Plic
Plic(const Params &params)
Definition: plic.cc:55
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Plic::updateOutput
void updateOutput()
Trigger:
Definition: plic.cc:422
gem5::Plic::PlicRegisters::enableStart
const Addr enableStart
Definition: plic.hh:191
gem5::Plic::init
void init() override
SimObject functions.
Definition: plic.cc:165
packet.hh
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::PioDevice::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: io_device.cc:59
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::Packet::getAtomicOp
AtomicOpFunctor * getAtomicOp() const
Accessor function to atomic op.
Definition: packet.hh:828
gem5::RiscvISA::INT_EXT_SUPER
@ INT_EXT_SUPER
Definition: faults.hh:94
gem5::ArmISA::j
Bitfield< 24 > j
Definition: misc_types.hh:57
gem5::Plic::PlicRegisters::reserved
std::vector< RegisterRaz > reserved
Definition: plic.hh:205
gem5::Plic::system
System * system
Definition: plic.hh:101
gem5::Plic::PlicRegisters::threshold
std::vector< Register32 > threshold
Definition: plic.hh:201
gem5::Clocked::cyclesToTicks
Tick cyclesToTicks(Cycles c) const
Definition: clocked_object.hh:227
gem5::Plic::PlicRegisters::thresholdPadding
const Addr thresholdPadding
Definition: plic.hh:194
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Plic::writeThreshold
void writeThreshold(Register32 &reg, const uint32_t &data, const int context_id)
Definition: plic.cc:333
gem5::PlicOutput::maxID
std::vector< uint32_t > maxID
Definition: plic.hh:93
gem5::BasicPioDevice::pioDelay
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:157
gem5::Plic::updateInt
void updateInt()
Trigger:
Definition: plic.cc:440
gem5::Plic::effPriority
std::vector< std::vector< uint32_t > > effPriority
Definition: plic.hh:243
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::Plic::writeClaim
void writeClaim(Register32 &reg, const uint32_t &data, const int context_id)
Definition: plic.cc:373
gem5::Plic::clear
void clear(int src_id)
Definition: plic.cc:95
gem5::Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:369
gem5::PlicOutput
NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive....
Definition: plic.hh:91
gem5::Plic::propagateOutput
void propagateOutput()
Trigger:
Definition: plic.cc:390
name
const std::string & name()
Definition: trace.cc:49
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::Plic::PlicRegisters::claim
std::vector< Register32 > claim
Definition: plic.hh:202
packet_access.hh
gem5::arrayParamOut
decltype(std::begin(std::declval< const T & >()), std::end(std::declval< const T & >()), void()) arrayParamOut(CheckpointOut &os, const std::string &name, const T &param)
Definition: serialize.hh:409
gem5::PlicOutput::maxPriority
std::vector< uint32_t > maxPriority
Definition: plic.hh:94
gem5::statistics::enabled
bool enabled()
Definition: statistics.cc:286
gem5::divCeil
static constexpr T divCeil(const T &a, const U &b)
Definition: intmath.hh:110
gem5::RegisterBank< ByteOrder::little >::addRegister
void addRegister(RegisterBase &reg)
Definition: reg_bank.hh:820
gem5::Plic::output
PlicOutput output
Definition: plic.hh:246
gem5::Plic::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: plic.cc:145
gem5::Plic::read
Tick read(PacketPtr pkt) override
PioDevice funcitons.
Definition: plic.cc:123
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::Plic::PlicRegisters::init
void init()
Definition: plic.cc:195
gem5::RegisterBank::read
virtual void read(Addr addr, void *buf, Addr bytes)
Definition: reg_bank.hh:827
gem5::Plic::PlicRegisters::priority
std::vector< Register32 > priority
Definition: plic.hh:198
gem5::Plic::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: plic.cc:511
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
base.hh
gem5::System::threads
Threads threads
Definition: system.hh:314
gem5::Plic::update
EventFunctionWrapper update
Definition: plic.hh:261
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:626
gem5::Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1044
gem5::Plic::writeEnable
void writeEnable(Register32 &reg, const uint32_t &data, const int src32_id, const int context_id)
Definition: plic.cc:315
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::Plic::PlicRegisters::plic
Plic * plic
Definition: plic.hh:211
gem5::Plic::PlicRegisters::maxBankSize
const Addr maxBankSize
Definition: plic.hh:195
plic.hh
gem5::BasicPioDevice::pioSize
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:154
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::Plic::PlicRegisters::claim_holes
std::vector< RegisterRaz > claim_holes
Definition: plic.hh:204
gem5::Plic::lastID
std::vector< uint32_t > lastID
Definition: plic.hh:245
gem5::arrayParamIn
void arrayParamIn(CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
Definition: circlebuf.hh:257
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:790
gem5::Plic::Register32
PlicRegisters::Register32 Register32
Definition: plic.hh:217
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Plic::PlicRegisters::pendingStart
const Addr pendingStart
Definition: plic.hh:190
gem5::BasicPioDevice
Definition: io_device.hh:147
gem5::Plic::readClaim
uint32_t readClaim(Register32 &reg, const int context_id)
Definition: plic.cc:342
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:800
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1197

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