gem5  v21.1.0.2
plic.hh
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37 
38 #ifndef __DEV_RISCV_PLIC_HH__
39 #define __DEV_RISCV_PLIC_HH__
40 
41 #include <bitset>
42 #include <map>
43 
44 #include "arch/riscv/interrupts.hh"
45 #include "dev/io_device.hh"
46 #include "dev/reg_bank.hh"
47 #include "mem/packet.hh"
48 #include "mem/packet_access.hh"
49 #include "params/Plic.hh"
50 #include "sim/system.hh"
51 
52 namespace gem5
53 {
54 
55 using namespace RiscvISA;
91 struct PlicOutput
92 {
95 };
96 
97 class Plic : public BasicPioDevice
98 {
99  // Params
100  protected:
102 
103  // Number of interrupt sources
104  int nSrc;
109  int nSrc32;
117  int nContext;
118 
119  public:
120  typedef PlicParams Params;
121  Plic(const Params &params);
122 
123  // External API
124  public:
128  void post(int src_id);
129  void clear(int src_id);
130 
134  void init() override;
135  void serialize(CheckpointOut &cp) const override;
136  void unserialize(CheckpointIn &cp) override;
137 
138  protected:
142  Tick read(PacketPtr pkt) override;
143  Tick write(PacketPtr pkt) override;
144 
145  // Register bank
146  private:
147 
188  {
189  public:
190  const Addr pendingStart = 0x1000;
191  const Addr enableStart = 0x2000;
192  const Addr thresholdStart = 0x0200000;
193  const Addr enablePadding = 0x80;
194  const Addr thresholdPadding = 0x1000;
195  const Addr maxBankSize = 0x4000000;
196 
197 
206 
207  PlicRegisters(const std::string &name, Addr base, Plic* plic) :
209  plic(plic) {}
210 
212 
213  void init();
214 
215  } registers;
216 
218 
222  void writePriority(Register32& reg, const uint32_t& data,
223  const int src_id);
224 
225  void writeEnable(Register32& reg, const uint32_t& data,
226  const int src32_id, const int context_id);
227 
228  void writeThreshold(Register32& reg, const uint32_t& data,
229  const int context_id);
230 
231  uint32_t readClaim(Register32& reg, const int context_id);
232 
233  void writeClaim(Register32& reg, const uint32_t& data,
234  const int context_id);
235 
236  // Latency Model
237  private:
238 
239  // Internal states
240  // per-source pending * priority
242  // per-context, per-source pendingPriority * enable
244  // per-context last-claimed id
247 
259  void propagateOutput();
260  std::map<Tick, PlicOutput> outputQueue;
262 
271  void updateOutput();
272 
282  void updateInt();
283 };
284 
285 } // namespace gem5
286 
287 #endif // __DEV_RISCV_PLIC_HH__
gem5::unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:206
gem5::Plic::nSrc32
int nSrc32
Number of 32-bit pending registers needed = ceil(nSrc / 32)
Definition: plic.hh:109
io_device.hh
gem5::Plic::PlicRegisters::enable_holes
std::vector< RegisterRaz > enable_holes
Definition: plic.hh:203
system.hh
gem5::Plic::nContext
int nContext
Number of interrupt contexts = nThread * 2 e.g.
Definition: plic.hh:117
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::Plic::PlicRegisters::enable
std::vector< std::vector< Register32 > > enable
Definition: plic.hh:200
gem5::Plic::outputQueue
std::map< Tick, PlicOutput > outputQueue
Definition: plic.hh:260
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::Plic::nSrc
int nSrc
Definition: plic.hh:104
gem5::Plic::pendingPriority
std::vector< uint32_t > pendingPriority
Definition: plic.hh:241
interrupts.hh
gem5::Plic
Definition: plic.hh:97
gem5::Plic::PlicRegisters::pending
std::vector< Register32 > pending
Definition: plic.hh:199
std::vector< uint32_t >
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
packet.hh
gem5::PioDevice::Params
PioDeviceParams Params
Definition: io_device.hh:134
gem5::Plic::PlicRegisters::reserved
std::vector< RegisterRaz > reserved
Definition: plic.hh:205
gem5::System
Definition: system.hh:77
gem5::Plic::system
System * system
Definition: plic.hh:101
gem5::Plic::PlicRegisters::threshold
std::vector< Register32 > threshold
Definition: plic.hh:201
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PlicOutput::maxID
std::vector< uint32_t > maxID
Definition: plic.hh:93
gem5::Plic::Params
PlicParams Params
Definition: plic.hh:120
gem5::Plic::effPriority
std::vector< std::vector< uint32_t > > effPriority
Definition: plic.hh:243
gem5::serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:157
gem5::PlicOutput
NOTE: This implementation of CLINT is based on the SiFive U54MC datasheet: https://sifive....
Definition: plic.hh:91
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
name
const std::string & name()
Definition: trace.cc:49
gem5::Plic::PlicRegisters::claim
std::vector< Register32 > claim
Definition: plic.hh:202
packet_access.hh
gem5::PlicOutput::maxPriority
std::vector< uint32_t > maxPriority
Definition: plic.hh:94
gem5::Plic::output
PlicOutput output
Definition: plic.hh:246
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::Plic::PlicRegisters::PlicRegisters
PlicRegisters(const std::string &name, Addr base, Plic *plic)
Definition: plic.hh:207
gem5::Plic::PlicRegisters::priority
std::vector< Register32 > priority
Definition: plic.hh:198
gem5::Plic::PlicRegisters
MMIO Registers.
Definition: plic.hh:187
gem5::Plic::update
EventFunctionWrapper update
Definition: plic.hh:261
gem5::Plic::PlicRegisters::plic
Plic * plic
Definition: plic.hh:211
gem5::RegisterBank< ByteOrder::little >
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::statistics::init
const FlagsType init
This Stat is Initialized.
Definition: info.hh:56
gem5::Plic::PlicRegisters::claim_holes
std::vector< RegisterRaz > claim_holes
Definition: plic.hh:204
gem5::Plic::lastID
std::vector< uint32_t > lastID
Definition: plic.hh:245
gem5::RegisterBank< ByteOrder::little >::Register32
Register< uint32_t > Register32
Definition: reg_bank.hh:794
gem5::Plic::Register32
PlicRegisters::Register32 Register32
Definition: plic.hh:217
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BasicPioDevice
Definition: io_device.hh:147
reg_bank.hh

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