gem5::VegaISA::InFmt_SOP1 Struct Reference

#include <gpu_decoder.hh>

Public Attributes
unsigned int	SSRC0: 8
unsigned int	OP: 8
unsigned int	SDST: 7
unsigned int	ENCODING: 9

Detailed Description

Definition at line 1744 of file gpu_decoder.hh.

Member Data Documentation

ENCODING

unsigned int gem5::VegaISA::InFmt_SOP1::ENCODING

Definition at line 1748 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Decoder::decode().

OP

unsigned int gem5::VegaISA::InFmt_SOP1::OP

Definition at line 1746 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP1::initOperandInfo(), and gem5::VegaISA::Decoder::subDecode_OP_SOP1().

SDST

unsigned int gem5::VegaISA::InFmt_SOP1::SDST

Definition at line 1747 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP1__S_MOV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_CMOV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_CMOV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NOT_B32::execute(), gem5::VegaISA::Inst_SOP1__S_NOT_B64::execute(), gem5::VegaISA::Inst_SOP1__S_WQM_B32::execute(), gem5::VegaISA::Inst_SOP1__S_WQM_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BREV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BREV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64::execute(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8::execute(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B64::execute(), gem5::VegaISA::Inst_SOP1__S_GETPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32::execute(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ABS_I32::execute(), gem5::VegaISA::Inst_SOP1::generateDisassembly(), and gem5::VegaISA::Inst_SOP1::initOperandInfo().

SSRC0

unsigned int gem5::VegaISA::InFmt_SOP1::SSRC0

Definition at line 1745 of file gpu_decoder.hh.

Referenced by gem5::VegaISA::Inst_SOP1__S_MOV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_CMOV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_CMOV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NOT_B32::execute(), gem5::VegaISA::Inst_SOP1__S_NOT_B64::execute(), gem5::VegaISA::Inst_SOP1__S_WQM_B32::execute(), gem5::VegaISA::Inst_SOP1__S_WQM_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BREV_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BREV_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32::execute(), gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64::execute(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8::execute(), gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET0_B64::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B32::execute(), gem5::VegaISA::Inst_SOP1__S_BITSET1_B64::execute(), gem5::VegaISA::Inst_SOP1__S_SETPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64::execute(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32::execute(), gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32::execute(), gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64::execute(), gem5::VegaISA::Inst_SOP1__S_ABS_I32::execute(), gem5::VegaISA::Inst_SOP1::generateDisassembly(), gem5::VegaISA::Inst_SOP1::hasSecondDword(), and gem5::VegaISA::Inst_SOP1::initOperandInfo().

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The documentation for this struct was generated from the following file:

• arch/amdgpu/vega/gpu_decoder.hh