gem5 v24.0.0.0
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sop1.cc
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1/*
2 * Copyright (c) 2024 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
34
35namespace gem5
36{
37
38namespace VegaISA
39{
40 // --- Inst_SOP1__S_MOV_B32 class methods ---
41
43 : Inst_SOP1(iFmt, "s_mov_b32")
44 {
45 setFlag(ALU);
46 } // Inst_SOP1__S_MOV_B32
47
49 {
50 } // ~Inst_SOP1__S_MOV_B32
51
52 // --- description from .arch file ---
53 // D.u = S0.u.
54 void
56 {
57 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
58 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
59
60 src.read();
61
62 sdst = src.rawData();
63
64 sdst.write();
65 } // execute
66 // --- Inst_SOP1__S_MOV_B64 class methods ---
67
69 : Inst_SOP1(iFmt, "s_mov_b64")
70 {
71 setFlag(ALU);
72 } // Inst_SOP1__S_MOV_B64
73
75 {
76 } // ~Inst_SOP1__S_MOV_B64
77
78 // --- description from .arch file ---
79 // D.u64 = S0.u64.
80 void
82 {
83 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
84 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
85
86 src.read();
87
88 sdst = src.rawData();
89
90 sdst.write();
91 } // execute
92 // --- Inst_SOP1__S_CMOV_B32 class methods ---
93
95 : Inst_SOP1(iFmt, "s_cmov_b32")
96 {
97 setFlag(ALU);
98 } // Inst_SOP1__S_CMOV_B32
99
101 {
102 } // ~Inst_SOP1__S_CMOV_B32
103
104 // --- description from .arch file ---
105 // (SCC) then D.u = S0.u;
106 // else NOP.
107 // Conditional move.
108 void
110 {
111 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
112 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
113 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
114
115 src.read();
116 scc.read();
117
118 if (scc.rawData()) {
119 sdst = src.rawData();
120 sdst.write();
121 }
122 } // execute
123 // --- Inst_SOP1__S_CMOV_B64 class methods ---
124
126 : Inst_SOP1(iFmt, "s_cmov_b64")
127 {
128 setFlag(ALU);
129 } // Inst_SOP1__S_CMOV_B64
130
132 {
133 } // ~Inst_SOP1__S_CMOV_B64
134
135 // --- description from .arch file ---
136 // if (SCC) then D.u64 = S0.u64;
137 // else NOP.
138 // Conditional move.
139 void
141 {
142 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
143 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
144 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
145
146 src.read();
147 scc.read();
148
149 if (scc.rawData()) {
150 sdst = src.rawData();
151 sdst.write();
152 }
153 } // execute
154 // --- Inst_SOP1__S_NOT_B32 class methods ---
155
157 : Inst_SOP1(iFmt, "s_not_b32")
158 {
159 setFlag(ALU);
160 } // Inst_SOP1__S_NOT_B32
161
163 {
164 } // ~Inst_SOP1__S_NOT_B32
165
166 // --- description from .arch file ---
167 // D.u = ~S0.u;
168 // SCC = 1 if result is non-zero.
169 // Bitwise negation.
170 void
172 {
173 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
174 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
175 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
176
177 src.read();
178
179 sdst = ~src.rawData();
180
181 scc = sdst.rawData() ? 1 : 0;
182
183 sdst.write();
184 scc.write();
185 } // execute
186 // --- Inst_SOP1__S_NOT_B64 class methods ---
187
189 : Inst_SOP1(iFmt, "s_not_b64")
190 {
191 setFlag(ALU);
192 } // Inst_SOP1__S_NOT_B64
193
195 {
196 } // ~Inst_SOP1__S_NOT_B64
197
198 // --- description from .arch file ---
199 // D.u64 = ~S0.u64;
200 // SCC = 1 if result is non-zero.
201 // Bitwise negation.
202 void
204 {
205 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
206 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
207 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
208
209 src.read();
210
211 sdst = ~src.rawData();
212 scc = sdst.rawData() ? 1 : 0;
213
214 sdst.write();
215 scc.write();
216 } // execute
217 // --- Inst_SOP1__S_WQM_B32 class methods ---
218
220 : Inst_SOP1(iFmt, "s_wqm_b32")
221 {
222 setFlag(ALU);
223 } // Inst_SOP1__S_WQM_B32
224
226 {
227 } // ~Inst_SOP1__S_WQM_B32
228
229 // --- description from .arch file ---
230 // D[i] = (S0[(i & ~3):(i | 3)] != 0);
231 // Computes whole quad mode for an active/valid mask.
232 // SCC = 1 if result is non-zero.
233 void
235 {
236 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
237 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
238 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
239
240 src.read();
241
242 sdst = wholeQuadMode(src.rawData());
243 scc = sdst.rawData() ? 1 : 0;
244
245 sdst.write();
246 scc.write();
247 } // execute
248 // --- Inst_SOP1__S_WQM_B64 class methods ---
249
251 : Inst_SOP1(iFmt, "s_wqm_b64")
252 {
253 setFlag(ALU);
254 } // Inst_SOP1__S_WQM_B64
255
257 {
258 } // ~Inst_SOP1__S_WQM_B64
259
260 // --- description from .arch file ---
261 // D[i] = (S0[(i & ~3):(i | 3)] != 0);
262 // Computes whole quad mode for an active/valid mask.
263 // SCC = 1 if result is non-zero.
264 void
266 {
267 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
268 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
269 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
270
271 src.read();
272
273 sdst = wholeQuadMode(src.rawData());
274 scc = sdst.rawData() ? 1 : 0;
275
276 sdst.write();
277 scc.write();
278 } // execute
279 // --- Inst_SOP1__S_BREV_B32 class methods ---
280
282 : Inst_SOP1(iFmt, "s_brev_b32")
283 {
284 setFlag(ALU);
285 } // Inst_SOP1__S_BREV_B32
286
288 {
289 } // ~Inst_SOP1__S_BREV_B32
290
291 // --- description from .arch file ---
292 // D.u[31:0] = S0.u[0:31] (reverse bits).
293 void
295 {
296 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
297 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
298
299 src.read();
300
301 sdst = reverseBits(src.rawData());
302
303 sdst.write();
304 } // execute
305 // --- Inst_SOP1__S_BREV_B64 class methods ---
306
308 : Inst_SOP1(iFmt, "s_brev_b64")
309 {
310 setFlag(ALU);
311 } // Inst_SOP1__S_BREV_B64
312
314 {
315 } // ~Inst_SOP1__S_BREV_B64
316
317 // --- description from .arch file ---
318 // D.u64[63:0] = S0.u64[0:63] (reverse bits).
319 void
321 {
322 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
323 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
324
325 src.read();
326
327 sdst = reverseBits(src.rawData());
328
329 sdst.write();
330 } // execute
331 // --- Inst_SOP1__S_BCNT0_I32_B32 class methods ---
332
334 : Inst_SOP1(iFmt, "s_bcnt0_i32_b32")
335 {
336 setFlag(ALU);
337 } // Inst_SOP1__S_BCNT0_I32_B32
338
340 {
341 } // ~Inst_SOP1__S_BCNT0_I32_B32
342
343 // --- description from .arch file ---
344 // D.i = CountZeroBits(S0.u);
345 // SCC = 1 if result is non-zero.
346 void
348 {
349 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
350 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
351 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
352
353 src.read();
354
355 sdst = countZeroBits(src.rawData());
356 scc = sdst.rawData() ? 1 : 0;
357
358 sdst.write();
359 scc.write();
360 } // execute
361 // --- Inst_SOP1__S_BCNT0_I32_B64 class methods ---
362
364 : Inst_SOP1(iFmt, "s_bcnt0_i32_b64")
365 {
366 setFlag(ALU);
367 } // Inst_SOP1__S_BCNT0_I32_B64
368
370 {
371 } // ~Inst_SOP1__S_BCNT0_I32_B64
372
373 // --- description from .arch file ---
374 // D.i = CountZeroBits(S0.u64);
375 // SCC = 1 if result is non-zero.
376 void
378 {
379 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
380 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
381 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
382
383 src.read();
384
385 sdst = countZeroBits(src.rawData());
386 scc = sdst.rawData() ? 1 : 0;
387
388 sdst.write();
389 scc.write();
390 } // execute
391 // --- Inst_SOP1__S_BCNT1_I32_B32 class methods ---
392
394 : Inst_SOP1(iFmt, "s_bcnt1_i32_b32")
395 {
396 setFlag(ALU);
397 } // Inst_SOP1__S_BCNT1_I32_B32
398
400 {
401 } // ~Inst_SOP1__S_BCNT1_I32_B32
402
403 // --- description from .arch file ---
404 // D.i = CountOneBits(S0.u);
405 // SCC = 1 if result is non-zero.
406 void
408 {
409 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
410 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
411 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
412
413 src.read();
414
415 sdst = popCount(src.rawData());
416 scc = sdst.rawData() ? 1 : 0;
417
418 sdst.write();
419 scc.write();
420 } // execute
421 // --- Inst_SOP1__S_BCNT1_I32_B64 class methods ---
422
424 : Inst_SOP1(iFmt, "s_bcnt1_i32_b64")
425 {
426 setFlag(ALU);
427 } // Inst_SOP1__S_BCNT1_I32_B64
428
430 {
431 } // ~Inst_SOP1__S_BCNT1_I32_B64
432
433 // --- description from .arch file ---
434 // D.i = CountOneBits(S0.u64);
435 // SCC = 1 if result is non-zero.
436 void
438 {
439 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
440 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
441 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
442
443 src.read();
444
445 sdst = popCount(src.rawData());
446 scc = sdst.rawData() ? 1 : 0;
447
448 sdst.write();
449 scc.write();
450 } // execute
451 // --- Inst_SOP1__S_FF0_I32_B32 class methods ---
452
454 : Inst_SOP1(iFmt, "s_ff0_i32_b32")
455 {
456 setFlag(ALU);
457 } // Inst_SOP1__S_FF0_I32_B32
458
460 {
461 } // ~Inst_SOP1__S_FF0_I32_B32
462
463 // --- description from .arch file ---
464 // D.i = FindFirstZero(S0.u);
465 // If no zeros are found, return -1.
466 // Returns the bit position of the first zero from the LSB.
467 void
469 {
470 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
471 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
472
473 src.read();
474
475 sdst = findFirstZero(src.rawData());
476
477 sdst.write();
478 } // execute
479 // --- Inst_SOP1__S_FF0_I32_B64 class methods ---
480
482 : Inst_SOP1(iFmt, "s_ff0_i32_b64")
483 {
484 setFlag(ALU);
485 } // Inst_SOP1__S_FF0_I32_B64
486
488 {
489 } // ~Inst_SOP1__S_FF0_I32_B64
490
491 // --- description from .arch file ---
492 // D.i = FindFirstZero(S0.u64);
493 // If no zeros are found, return -1.
494 // Returns the bit position of the first zero from the LSB.
495 void
497 {
498 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
499 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
500
501 src.read();
502
503 sdst = findFirstZero(src.rawData());
504
505 sdst.write();
506 } // execute
507 // --- Inst_SOP1__S_FF1_I32_B32 class methods ---
508
510 : Inst_SOP1(iFmt, "s_ff1_i32_b32")
511 {
512 setFlag(ALU);
513 } // Inst_SOP1__S_FF1_I32_B32
514
516 {
517 } // ~Inst_SOP1__S_FF1_I32_B32
518
519 // --- description from .arch file ---
520 // D.i = FindFirstOne(S0.u);
521 // If no ones are found, return -1.
522 // Returns the bit position of the first one from the LSB.
523 void
525 {
526 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
527 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
528
529 src.read();
530
531 sdst = findFirstOne(src.rawData());
532
533 sdst.write();
534 } // execute
535 // --- Inst_SOP1__S_FF1_I32_B64 class methods ---
536
538 : Inst_SOP1(iFmt, "s_ff1_i32_b64")
539 {
540 setFlag(ALU);
541 } // Inst_SOP1__S_FF1_I32_B64
542
544 {
545 } // ~Inst_SOP1__S_FF1_I32_B64
546
547 // --- description from .arch file ---
548 // D.i = FindFirstOne(S0.u64);
549 // If no ones are found, return -1.
550 // Returns the bit position of the first one from the LSB.
551 void
553 {
554 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
555 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
556
557 src.read();
558
559 sdst = findFirstOne(src.rawData());
560
561 sdst.write();
562 } // execute
563 // --- Inst_SOP1__S_FLBIT_I32_B32 class methods ---
564
566 : Inst_SOP1(iFmt, "s_flbit_i32_b32")
567 {
568 setFlag(ALU);
569 } // Inst_SOP1__S_FLBIT_I32_B32
570
572 {
573 } // ~Inst_SOP1__S_FLBIT_I32_B32
574
575 // --- description from .arch file ---
576 // D.i = FindFirstOne(S0.u);
577 // If no ones are found, return -1.
578 // Counts how many zeros before the first one starting from the MSB.
579 void
581 {
582 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
583 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
584
585 src.read();
586
587 sdst = countZeroBitsMsb(src.rawData());
588
589 sdst.write();
590 } // execute
591 // --- Inst_SOP1__S_FLBIT_I32_B64 class methods ---
592
594 : Inst_SOP1(iFmt, "s_flbit_i32_b64")
595 {
596 setFlag(ALU);
597 } // Inst_SOP1__S_FLBIT_I32_B64
598
600 {
601 } // ~Inst_SOP1__S_FLBIT_I32_B64
602
603 // --- description from .arch file ---
604 // D.i = FindFirstOne(S0.u64);
605 // If no ones are found, return -1.
606 // Counts how many zeros before the first one starting from the MSB.
607 void
609 {
610 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
611 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
612
613 src.read();
614
615 sdst = countZeroBitsMsb(src.rawData());
616
617 sdst.write();
618 } // execute
619 // --- Inst_SOP1__S_FLBIT_I32 class methods ---
620
622 : Inst_SOP1(iFmt, "s_flbit_i32")
623 {
624 setFlag(ALU);
625 } // Inst_SOP1__S_FLBIT_I32
626
628 {
629 } // ~Inst_SOP1__S_FLBIT_I32
630
631 // --- description from .arch file ---
632 // D.i = FirstOppositeSignBit(S0.i);
633 // If S0.i == 0 or S0.i == -1 (all bits are the same), return -1.
634 // Counts how many bits in a row (from MSB to LSB) are the same as the
635 // sign bit.
636 void
638 {
639 ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
640 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
641
642 src.read();
643
644 sdst = firstOppositeSignBit(src.rawData());
645
646 sdst.write();
647 } // execute
648 // --- Inst_SOP1__S_FLBIT_I32_I64 class methods ---
649
651 : Inst_SOP1(iFmt, "s_flbit_i32_i64")
652 {
653 setFlag(ALU);
654 } // Inst_SOP1__S_FLBIT_I32_I64
655
657 {
658 } // ~Inst_SOP1__S_FLBIT_I32_I64
659
660 // --- description from .arch file ---
661 // D.i = FirstOppositeSignBit(S0.i64);
662 // If S0.i == 0 or S0.i == -1 (all bits are the same), return -1.
663 // Counts how many bits in a row (from MSB to LSB) are the same as the
664 // sign bit.
665 void
667 {
668 ConstScalarOperandI64 src(gpuDynInst, instData.SSRC0);
669 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
670
671 src.read();
672
673 sdst = firstOppositeSignBit(src.rawData());
674
675 sdst.write();
676 } // execute
677 // --- Inst_SOP1__S_SEXT_I32_I8 class methods ---
678
680 : Inst_SOP1(iFmt, "s_sext_i32_i8")
681 {
682 setFlag(ALU);
683 } // Inst_SOP1__S_SEXT_I32_I8
684
686 {
687 } // ~Inst_SOP1__S_SEXT_I32_I8
688
689 // --- description from .arch file ---
690 // D.i = signext(S0.i[7:0]) (sign extension).
691 void
693 {
694 ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
695 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
696
697 src.read();
698
699 sdst = sext<std::numeric_limits<ScalarRegI8>::digits>(
700 bits(src.rawData(), 7, 0));
701
702 sdst.write();
703 } // execute
704 // --- Inst_SOP1__S_SEXT_I32_I16 class methods ---
705
707 : Inst_SOP1(iFmt, "s_sext_i32_i16")
708 {
709 setFlag(ALU);
710 } // Inst_SOP1__S_SEXT_I32_I16
711
713 {
714 } // ~Inst_SOP1__S_SEXT_I32_I16
715
716 // --- description from .arch file ---
717 // D.i = signext(S0.i[15:0]) (sign extension).
718 void
720 {
721 ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
722 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
723
724 src.read();
725
726 sdst = sext<std::numeric_limits<ScalarRegI16>::digits>(
727 bits(src.rawData(), 15, 0));
728
729 sdst.write();
730 } // execute
731 // --- Inst_SOP1__S_BITSET0_B32 class methods ---
732
734 : Inst_SOP1(iFmt, "s_bitset0_b32")
735 {
736 setFlag(ALU);
737 } // Inst_SOP1__S_BITSET0_B32
738
740 {
741 } // ~Inst_SOP1__S_BITSET0_B32
742
743 // --- description from .arch file ---
744 // D.u[S0.u[4:0]] = 0.
745 void
747 {
748 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
749 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
750
751 src.read();
752
753 sdst.setBit(bits(src.rawData(), 4, 0), 0);
754
755 sdst.write();
756 } // execute
757 // --- Inst_SOP1__S_BITSET0_B64 class methods ---
758
760 : Inst_SOP1(iFmt, "s_bitset0_b64")
761 {
762 setFlag(ALU);
763 } // Inst_SOP1__S_BITSET0_B64
764
766 {
767 } // ~Inst_SOP1__S_BITSET0_B64
768
769 // --- description from .arch file ---
770 // D.u64[S0.u[5:0]] = 0.
771 void
773 {
774 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
775 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
776
777 src.read();
778
779 sdst.setBit(bits(src.rawData(), 5, 0), 0);
780
781 sdst.write();
782 } // execute
783 // --- Inst_SOP1__S_BITSET1_B32 class methods ---
784
786 : Inst_SOP1(iFmt, "s_bitset1_b32")
787 {
788 setFlag(ALU);
789 } // Inst_SOP1__S_BITSET1_B32
790
792 {
793 } // ~Inst_SOP1__S_BITSET1_B32
794
795 // --- description from .arch file ---
796 // D.u[S0.u[4:0]] = 1.
797 void
799 {
800 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
801 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
802
803 src.read();
804
805 sdst.setBit(bits(src.rawData(), 4, 0), 1);
806
807 sdst.write();
808 } // execute
809 // --- Inst_SOP1__S_BITSET1_B64 class methods ---
810
812 : Inst_SOP1(iFmt, "s_bitset1_b64")
813 {
814 setFlag(ALU);
815 } // Inst_SOP1__S_BITSET1_B64
816
818 {
819 } // ~Inst_SOP1__S_BITSET1_B64
820
821 // --- description from .arch file ---
822 // D.u64[S0.u[5:0]] = 1.
823 void
825 {
826 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
827 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
828
829 src.read();
830
831 sdst.setBit(bits(src.rawData(), 5, 0), 1);
832
833 sdst.write();
834 } // execute
835 // --- Inst_SOP1__S_GETPC_B64 class methods ---
836
838 : Inst_SOP1(iFmt, "s_getpc_b64")
839 {
840 setFlag(ALU);
841 } // Inst_SOP1__S_GETPC_B64
842
844 {
845 } // ~Inst_SOP1__S_GETPC_B64
846
847 // --- description from .arch file ---
848 // D.u64 = PC + 4.
849 // Destination receives the byte address of the next instruction.
850 void
852 {
853 Addr pc = gpuDynInst->pc();
854 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
855
856 sdst = pc + 4;
857
858 sdst.write();
859 } // execute
860 // --- Inst_SOP1__S_SETPC_B64 class methods ---
861
863 : Inst_SOP1(iFmt, "s_setpc_b64")
864 {
865 setFlag(ALU);
866 } // Inst_SOP1__S_SETPC_B64
867
869 {
870 } // ~Inst_SOP1__S_SETPC_B64
871
872 // --- description from .arch file ---
873 // PC = S0.u64.
874 // S0.u64 is a byte address of the instruction to jump to.
875 void
877 {
878 Wavefront *wf = gpuDynInst->wavefront();
879 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
880
881 src.read();
882
883 wf->pc(src.rawData());
884 } // execute
885 // --- Inst_SOP1__S_SWAPPC_B64 class methods ---
886
888 : Inst_SOP1(iFmt, "s_swappc_b64")
889 {
890 setFlag(ALU);
891 } // Inst_SOP1__S_SWAPPC_B64
892
894 {
895 } // ~Inst_SOP1__S_SWAPPC_B64
896
897 // --- description from .arch file ---
898 // D.u64 = PC + 4; PC = S0.u64.
899 // S0.u64 is a byte address of the instruction to jump to.
900 void
902 {
903 Wavefront *wf = gpuDynInst->wavefront();
904 Addr pc = gpuDynInst->pc();
905 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
906 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
907
908 src.read();
909
910 sdst = pc + 4;
911
912 wf->pc(src.rawData());
913 sdst.write();
914 } // execute
915 // --- Inst_SOP1__S_RFE_B64 class methods ---
916
918 : Inst_SOP1(iFmt, "s_rfe_b64")
919 {
920 } // Inst_SOP1__S_RFE_B64
921
923 {
924 } // ~Inst_SOP1__S_RFE_B64
925
926 // --- description from .arch file ---
927 // PRIV = 0;
928 // PC = S0.u64.
929 // Return from exception handler and continue.
930 // This instruction may only be used within a trap handler.
931 void
933 {
935 } // execute
936 // --- Inst_SOP1__S_AND_SAVEEXEC_B64 class methods ---
937
939 InFmt_SOP1 *iFmt)
940 : Inst_SOP1(iFmt, "s_and_saveexec_b64")
941 {
942 setFlag(ALU);
943 setFlag(ReadsEXEC);
944 setFlag(WritesEXEC);
945 } // Inst_SOP1__S_AND_SAVEEXEC_B64
946
948 {
949 } // ~Inst_SOP1__S_AND_SAVEEXEC_B64
950
951 // --- description from .arch file ---
952 // D.u64 = EXEC;
953 // EXEC = S0.u64 & EXEC;
954 // SCC = 1 if the new value of EXEC is non-zero.
955 void
957 {
958 Wavefront *wf = gpuDynInst->wavefront();
959 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
960 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
961 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
962
963 src.read();
964
965 sdst = wf->execMask().to_ullong();
966 wf->execMask() = src.rawData() & wf->execMask().to_ullong();
967 scc = wf->execMask().any() ? 1 : 0;
968
969 sdst.write();
970 scc.write();
971 } // execute
972 // --- Inst_SOP1__S_OR_SAVEEXEC_B64 class methods ---
973
975 InFmt_SOP1 *iFmt)
976 : Inst_SOP1(iFmt, "s_or_saveexec_b64")
977 {
978 setFlag(ALU);
979 setFlag(ReadsEXEC);
980 setFlag(WritesEXEC);
981 } // Inst_SOP1__S_OR_SAVEEXEC_B64
982
984 {
985 } // ~Inst_SOP1__S_OR_SAVEEXEC_B64
986
987 // --- description from .arch file ---
988 // D.u64 = EXEC;
989 // EXEC = S0.u64 | EXEC;
990 // SCC = 1 if the new value of EXEC is non-zero.
991 void
993 {
994 Wavefront *wf = gpuDynInst->wavefront();
995 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
996 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
997 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
998
999 src.read();
1000
1001 sdst = wf->execMask().to_ullong();
1002 wf->execMask() = src.rawData() | wf->execMask().to_ullong();
1003 scc = wf->execMask().any() ? 1 : 0;
1004
1005 sdst.write();
1006 scc.write();
1007 } // execute
1008 // --- Inst_SOP1__S_XOR_SAVEEXEC_B64 class methods ---
1009
1011 InFmt_SOP1 *iFmt)
1012 : Inst_SOP1(iFmt, "s_xor_saveexec_b64")
1013 {
1014 setFlag(ALU);
1015 setFlag(ReadsEXEC);
1016 setFlag(WritesEXEC);
1017 } // Inst_SOP1__S_XOR_SAVEEXEC_B64
1018
1020 {
1021 } // ~Inst_SOP1__S_XOR_SAVEEXEC_B64
1022
1023 // --- description from .arch file ---
1024 // D.u64 = EXEC;
1025 // EXEC = S0.u64 ^ EXEC;
1026 // SCC = 1 if the new value of EXEC is non-zero.
1027 void
1029 {
1030 Wavefront *wf = gpuDynInst->wavefront();
1031 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1032 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1033 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1034
1035 src.read();
1036
1037 sdst = wf->execMask().to_ullong();
1038 wf->execMask() = src.rawData() ^ wf->execMask().to_ullong();
1039 scc = wf->execMask().any() ? 1 : 0;
1040
1041 sdst.write();
1042 scc.write();
1043 } // execute
1044 // --- Inst_SOP1__S_ANDN2_SAVEEXEC_B64 class methods ---
1045
1047 InFmt_SOP1 *iFmt)
1048 : Inst_SOP1(iFmt, "s_andn2_saveexec_b64")
1049 {
1050 setFlag(ALU);
1051 setFlag(ReadsEXEC);
1052 setFlag(WritesEXEC);
1053 } // Inst_SOP1__S_ANDN2_SAVEEXEC_B64
1054
1056 {
1057 } // ~Inst_SOP1__S_ANDN2_SAVEEXEC_B64
1058
1059 // --- description from .arch file ---
1060 // D.u64 = EXEC;
1061 // EXEC = S0.u64 & ~EXEC;
1062 // SCC = 1 if the new value of EXEC is non-zero.
1063 void
1065 {
1066 Wavefront *wf = gpuDynInst->wavefront();
1067 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1068 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1069 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1070
1071 src.read();
1072
1073 sdst = wf->execMask().to_ullong();
1074 wf->execMask() = src.rawData() &~ wf->execMask().to_ullong();
1075 scc = wf->execMask().any() ? 1 : 0;
1076
1077 sdst.write();
1078 scc.write();
1079 } // execute
1080 // --- Inst_SOP1__S_ORN2_SAVEEXEC_B64 class methods ---
1081
1083 InFmt_SOP1 *iFmt)
1084 : Inst_SOP1(iFmt, "s_orn2_saveexec_b64")
1085 {
1086 setFlag(ALU);
1087 setFlag(ReadsEXEC);
1088 setFlag(WritesEXEC);
1089 } // Inst_SOP1__S_ORN2_SAVEEXEC_B64
1090
1092 {
1093 } // ~Inst_SOP1__S_ORN2_SAVEEXEC_B64
1094
1095 // --- description from .arch file ---
1096 // D.u64 = EXEC;
1097 // EXEC = S0.u64 | ~EXEC;
1098 // SCC = 1 if the new value of EXEC is non-zero.
1099 void
1101 {
1102 Wavefront *wf = gpuDynInst->wavefront();
1103 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1104 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1105 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1106
1107 src.read();
1108
1109 sdst = wf->execMask().to_ullong();
1110 wf->execMask() = src.rawData() |~ wf->execMask().to_ullong();
1111 scc = wf->execMask().any() ? 1 : 0;
1112
1113 sdst.write();
1114 scc.write();
1115 } // execute
1116 // --- Inst_SOP1__S_NAND_SAVEEXEC_B64 class methods ---
1117
1119 InFmt_SOP1 *iFmt)
1120 : Inst_SOP1(iFmt, "s_nand_saveexec_b64")
1121 {
1122 setFlag(ALU);
1123 setFlag(ReadsEXEC);
1124 setFlag(WritesEXEC);
1125 } // Inst_SOP1__S_NAND_SAVEEXEC_B64
1126
1128 {
1129 } // ~Inst_SOP1__S_NAND_SAVEEXEC_B64
1130
1131 // --- description from .arch file ---
1132 // D.u64 = EXEC;
1133 // EXEC = ~(S0.u64 & EXEC);
1134 // SCC = 1 if the new value of EXEC is non-zero.
1135 void
1137 {
1138 Wavefront *wf = gpuDynInst->wavefront();
1139 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1140 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1141 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1142
1143 src.read();
1144
1145 sdst = wf->execMask().to_ullong();
1146 wf->execMask() = ~(src.rawData() & wf->execMask().to_ullong());
1147 scc = wf->execMask().any() ? 1 : 0;
1148
1149 sdst.write();
1150 scc.write();
1151 } // execute
1152 // --- Inst_SOP1__S_NOR_SAVEEXEC_B64 class methods ---
1153
1155 InFmt_SOP1 *iFmt)
1156 : Inst_SOP1(iFmt, "s_nor_saveexec_b64")
1157 {
1158 setFlag(ALU);
1159 setFlag(ReadsEXEC);
1160 setFlag(WritesEXEC);
1161 } // Inst_SOP1__S_NOR_SAVEEXEC_B64
1162
1164 {
1165 } // ~Inst_SOP1__S_NOR_SAVEEXEC_B64
1166
1167 // --- description from .arch file ---
1168 // D.u64 = EXEC;
1169 // EXEC = ~(S0.u64 | EXEC);
1170 // SCC = 1 if the new value of EXEC is non-zero.
1171 void
1173 {
1174 Wavefront *wf = gpuDynInst->wavefront();
1175 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1176 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1177 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1178
1179 src.read();
1180
1181 sdst = wf->execMask().to_ullong();
1182 wf->execMask() = ~(src.rawData() | wf->execMask().to_ullong());
1183 scc = wf->execMask().any() ? 1 : 0;
1184
1185 sdst.write();
1186 scc.write();
1187 } // execute
1188 // --- Inst_SOP1__S_XNOR_SAVEEXEC_B64 class methods ---
1189
1191 InFmt_SOP1 *iFmt)
1192 : Inst_SOP1(iFmt, "s_xnor_saveexec_b64")
1193 {
1194 setFlag(ALU);
1195 setFlag(ReadsEXEC);
1196 setFlag(WritesEXEC);
1197 } // Inst_SOP1__S_XNOR_SAVEEXEC_B64
1198
1200 {
1201 } // ~Inst_SOP1__S_XNOR_SAVEEXEC_B64
1202
1203 // --- description from .arch file ---
1204 // D.u64 = EXEC;
1205 // EXEC = ~(S0.u64 ^ EXEC);
1206 // SCC = 1 if the new value of EXEC is non-zero.
1207 void
1209 {
1210 Wavefront *wf = gpuDynInst->wavefront();
1211 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1212 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1213 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1214
1215 src.read();
1216
1217 sdst = wf->execMask().to_ullong();
1218 wf->execMask() = ~(src.rawData() ^ wf->execMask().to_ullong());
1219 scc = wf->execMask().any() ? 1 : 0;
1220
1221 sdst.write();
1222 scc.write();
1223 } // execute
1224 // --- Inst_SOP1__S_QUADMASK_B32 class methods ---
1225
1227 : Inst_SOP1(iFmt, "s_quadmask_b32")
1228 {
1229 setFlag(ALU);
1230 } // Inst_SOP1__S_QUADMASK_B32
1231
1233 {
1234 } // ~Inst_SOP1__S_QUADMASK_B32
1235
1236 // --- description from .arch file ---
1237 // D.u = QuadMask(S0.u):
1238 // D[0] = OR(S0[3:0]), D[1] = OR(S0[7:4]) ... D[31:8] = 0;
1239 // SCC = 1 if result is non-zero.
1240 void
1242 {
1243 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
1244 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
1245 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1246
1247 src.read();
1248
1249 sdst = quadMask(src.rawData());
1250 scc = sdst.rawData() ? 1 : 0;
1251
1252 sdst.write();
1253 scc.write();
1254 } // execute
1255 // --- Inst_SOP1__S_QUADMASK_B64 class methods ---
1256
1258 : Inst_SOP1(iFmt, "s_quadmask_b64")
1259 {
1260 setFlag(ALU);
1261 } // Inst_SOP1__S_QUADMASK_B64
1262
1264 {
1265 } // ~Inst_SOP1__S_QUADMASK_B64
1266
1267 // --- description from .arch file ---
1268 // D.u64 = QuadMask(S0.u64):
1269 // D[0] = OR(S0[3:0]), D[1] = OR(S0[7:4]) ... D[63:16] = 0;
1270 // SCC = 1 if result is non-zero.
1271 void
1273 {
1274 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1275 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1276 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1277
1278 src.read();
1279
1280 sdst = quadMask(src.rawData());
1281 scc = sdst.rawData() ? 1 : 0;
1282
1283 sdst.write();
1284 scc.write();
1285 } // execute
1286 // --- Inst_SOP1__S_MOVRELS_B32 class methods ---
1287
1289 : Inst_SOP1(iFmt, "s_movrels_b32")
1290 {
1291 setFlag(ALU);
1292 } // Inst_SOP1__S_MOVRELS_B32
1293
1295 {
1296 } // ~Inst_SOP1__S_MOVRELS_B32
1297
1298 // --- description from .arch file ---
1299 // D.u = SGPR[S0.u + M0.u].u (move from relative source).
1300 void
1302 {
1303 ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
1304 m0.read();
1305 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0 + m0.rawData());
1306 ScalarOperandU32 sdst(gpuDynInst, instData.SDST);
1307
1308 src.read();
1309
1310 sdst = src.rawData();
1311
1312 sdst.write();
1313 } // execute
1314 // --- Inst_SOP1__S_MOVRELS_B64 class methods ---
1315
1317 : Inst_SOP1(iFmt, "s_movrels_b64")
1318 {
1319 setFlag(ALU);
1320 } // Inst_SOP1__S_MOVRELS_B64
1321
1323 {
1324 } // ~Inst_SOP1__S_MOVRELS_B64
1325
1326 // --- description from .arch file ---
1327 // D.u64 = SGPR[S0.u + M0.u].u64 (move from relative source).
1328 // The index in M0.u must be even for this operation.
1329 void
1331 {
1332 ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
1333 m0.read();
1334 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0 + m0.rawData());
1335 ScalarOperandU64 sdst(gpuDynInst, instData.SDST);
1336
1337 src.read();
1338
1339 sdst = src.rawData();
1340
1341 sdst.write();
1342 } // execute
1343 // --- Inst_SOP1__S_MOVRELD_B32 class methods ---
1344
1346 : Inst_SOP1(iFmt, "s_movreld_b32")
1347 {
1348 setFlag(ALU);
1349 } // Inst_SOP1__S_MOVRELD_B32
1350
1352 {
1353 } // ~Inst_SOP1__S_MOVRELD_B32
1354
1355 // --- description from .arch file ---
1356 // SGPR[D.u + M0.u].u = S0.u (move to relative destination).
1357 void
1359 {
1360 ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
1361 m0.read();
1362 ConstScalarOperandU32 src(gpuDynInst, instData.SSRC0);
1363 ScalarOperandU32 sdst(gpuDynInst, instData.SDST + m0.rawData());
1364
1365 src.read();
1366
1367 sdst = src.rawData();
1368
1369 sdst.write();
1370 } // execute
1371 // --- Inst_SOP1__S_MOVRELD_B64 class methods ---
1372
1374 : Inst_SOP1(iFmt, "s_movreld_b64")
1375 {
1376 setFlag(ALU);
1377 } // Inst_SOP1__S_MOVRELD_B64
1378
1380 {
1381 } // ~Inst_SOP1__S_MOVRELD_B64
1382
1383 // --- description from .arch file ---
1384 // SGPR[D.u + M0.u].u64 = S0.u64 (move to relative destination).
1385 // The index in M0.u must be even for this operation.
1386 void
1388 {
1389 ConstScalarOperandU32 m0(gpuDynInst, REG_M0);
1390 m0.read();
1391 ConstScalarOperandU64 src(gpuDynInst, instData.SSRC0);
1392 ScalarOperandU64 sdst(gpuDynInst, instData.SDST + m0.rawData());
1393
1394 src.read();
1395
1396 sdst = src.rawData();
1397
1398 sdst.write();
1399 } // execute
1400 // --- Inst_SOP1__S_CBRANCH_JOIN class methods ---
1401
1403 : Inst_SOP1(iFmt, "s_cbranch_join")
1404 {
1405 setFlag(Branch);
1406 setFlag(WritesEXEC);
1407 } // Inst_SOP1__S_CBRANCH_JOIN
1408
1410 {
1411 } // ~Inst_SOP1__S_CBRANCH_JOIN
1412
1413 // --- description from .arch file ---
1414 // saved_csp = S0.u;
1415 // if (CSP == saved_csp) then
1416 // PC += 4; // Second time to JOIN: continue with program.
1417 // else
1418 // CSP -= 1; // First time to JOIN; jump to other FORK path.
1419 // {PC, EXEC} = SGPR[CSP * 4]; // Read 128 bits from 4 consecutive
1420 // SGPRs.
1421 // end
1422 // Conditional branch join point (end of conditional branch block). S0 is
1423 // saved CSP value.
1424 // See S_CBRANCH_G_FORK and S_CBRANCH_I_FORK for related instructions.
1425 void
1427 {
1429 } // execute
1430 // --- Inst_SOP1__S_ABS_I32 class methods ---
1431
1433 : Inst_SOP1(iFmt, "s_abs_i32")
1434 {
1435 setFlag(ALU);
1436 } // Inst_SOP1__S_ABS_I32
1437
1439 {
1440 } // ~Inst_SOP1__S_ABS_I32
1441
1442 // --- description from .arch file ---
1443 // if (S.i < 0) then D.i = -S.i;
1444 // else D.i = S.i;
1445 // SCC = 1 if result is non-zero.
1446 // Integer absolute value.
1447 void
1449 {
1450 ConstScalarOperandI32 src(gpuDynInst, instData.SSRC0);
1451 ScalarOperandI32 sdst(gpuDynInst, instData.SDST);
1452 ScalarOperandU32 scc(gpuDynInst, REG_SCC);
1453
1454 src.read();
1455
1456 sdst = std::abs(src.rawData());
1457
1458 scc = sdst.rawData() ? 1 : 0;
1459
1460 sdst.write();
1461 scc.write();
1462 } // execute
1463 // --- Inst_SOP1__S_MOV_FED_B32 class methods ---
1464
1466 : Inst_SOP1(iFmt, "s_mov_fed_b32")
1467 {
1468 setFlag(ALU);
1469 } // Inst_SOP1__S_MOV_FED_B32
1470
1472 {
1473 } // ~Inst_SOP1__S_MOV_FED_B32
1474
1475 // --- description from .arch file ---
1476 // D.u = S0.u. Introduce an EDC double-detect error on write to the
1477 // destination SGPR.
1478 void
1480 {
1482 } // execute
1483 // --- Inst_SOP1__S_SET_GPR_IDX_IDX class methods ---
1484
1486 InFmt_SOP1 *iFmt)
1487 : Inst_SOP1(iFmt, "s_set_gpr_idx_idx")
1488 {
1489 } // Inst_SOP1__S_SET_GPR_IDX_IDX
1490
1492 {
1493 } // ~Inst_SOP1__S_SET_GPR_IDX_IDX
1494
1495 // --- description from .arch file ---
1496 // M0[7:0] = S0.u[7:0].
1497 // Modify the index used in vector GPR indexing.
1498 void
1500 {
1502 } // execute
1503} // namespace VegaISA
1504} // namespace gem5
void setFlag(Flags flag)
Base class for branch operations.
Definition branch.hh:49
void execute(GPUDynInstPtr) override
Definition sop1.cc:1448
void execute(GPUDynInstPtr) override
Definition sop1.cc:1064
void execute(GPUDynInstPtr) override
Definition sop1.cc:956
void execute(GPUDynInstPtr) override
Definition sop1.cc:347
void execute(GPUDynInstPtr) override
Definition sop1.cc:377
void execute(GPUDynInstPtr) override
Definition sop1.cc:407
void execute(GPUDynInstPtr) override
Definition sop1.cc:437
void execute(GPUDynInstPtr) override
Definition sop1.cc:746
void execute(GPUDynInstPtr) override
Definition sop1.cc:772
void execute(GPUDynInstPtr) override
Definition sop1.cc:798
void execute(GPUDynInstPtr) override
Definition sop1.cc:824
void execute(GPUDynInstPtr) override
Definition sop1.cc:294
void execute(GPUDynInstPtr) override
Definition sop1.cc:320
void execute(GPUDynInstPtr) override
Definition sop1.cc:1426
void execute(GPUDynInstPtr) override
Definition sop1.cc:109
Inst_SOP1__S_CMOV_B32(InFmt_SOP1 *)
Definition sop1.cc:94
void execute(GPUDynInstPtr) override
Definition sop1.cc:140
void execute(GPUDynInstPtr) override
Definition sop1.cc:468
void execute(GPUDynInstPtr) override
Definition sop1.cc:496
void execute(GPUDynInstPtr) override
Definition sop1.cc:524
void execute(GPUDynInstPtr) override
Definition sop1.cc:552
void execute(GPUDynInstPtr) override
Definition sop1.cc:580
void execute(GPUDynInstPtr) override
Definition sop1.cc:608
void execute(GPUDynInstPtr) override
Definition sop1.cc:666
void execute(GPUDynInstPtr) override
Definition sop1.cc:637
void execute(GPUDynInstPtr) override
Definition sop1.cc:851
void execute(GPUDynInstPtr) override
Definition sop1.cc:1358
void execute(GPUDynInstPtr) override
Definition sop1.cc:1387
void execute(GPUDynInstPtr) override
Definition sop1.cc:1301
void execute(GPUDynInstPtr) override
Definition sop1.cc:1330
Inst_SOP1__S_MOV_B32(InFmt_SOP1 *)
Definition sop1.cc:42
void execute(GPUDynInstPtr) override
Definition sop1.cc:55
Inst_SOP1__S_MOV_B64(InFmt_SOP1 *)
Definition sop1.cc:68
void execute(GPUDynInstPtr) override
Definition sop1.cc:81
void execute(GPUDynInstPtr) override
Definition sop1.cc:1479
void execute(GPUDynInstPtr) override
Definition sop1.cc:1136
void execute(GPUDynInstPtr) override
Definition sop1.cc:1172
void execute(GPUDynInstPtr) override
Definition sop1.cc:171
void execute(GPUDynInstPtr) override
Definition sop1.cc:203
void execute(GPUDynInstPtr) override
Definition sop1.cc:1100
void execute(GPUDynInstPtr) override
Definition sop1.cc:992
void execute(GPUDynInstPtr) override
Definition sop1.cc:1241
void execute(GPUDynInstPtr) override
Definition sop1.cc:1272
void execute(GPUDynInstPtr) override
Definition sop1.cc:932
void execute(GPUDynInstPtr) override
Definition sop1.cc:876
void execute(GPUDynInstPtr) override
Definition sop1.cc:1499
void execute(GPUDynInstPtr) override
Definition sop1.cc:719
void execute(GPUDynInstPtr) override
Definition sop1.cc:692
void execute(GPUDynInstPtr) override
Definition sop1.cc:901
void execute(GPUDynInstPtr) override
Definition sop1.cc:234
void execute(GPUDynInstPtr) override
Definition sop1.cc:265
void execute(GPUDynInstPtr) override
Definition sop1.cc:1208
void execute(GPUDynInstPtr) override
Definition sop1.cc:1028
void read() override
read from and write to the underlying register(s) that this operand is referring to.
Definition operand.hh:409
std::enable_if< Condition, DataType >::type rawData() const
we store scalar data in a std::array, however if we need the full operand data we use this method to ...
Definition operand.hh:392
std::enable_if< Condition, void >::type setBit(int bit, int bit_val)
bit access to scalar data.
Definition operand.hh:491
Addr pc() const
VectorMask & execMask()
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
constexpr int popCount(uint64_t val)
Returns the number of set ones in the provided value.
Definition bitfield.hh:415
std::enable_if_t< std::is_integral_v< T >, T > reverseBits(T val, size_t size=sizeof(T))
Takes a value and returns the bit reversed version.
Definition bitfield.hh:255
Bitfield< 4 > pc
ScalarRegI32 countZeroBitsMsb(T val)
Definition inst_util.hh:164
T quadMask(T val)
Definition inst_util.hh:104
ScalarRegI32 firstOppositeSignBit(ScalarRegI32 val)
Definition inst_util.hh:174
ScalarRegI32 findFirstZero(T val)
Definition inst_util.hh:131
ScalarRegI32 findFirstOne(T val)
Definition inst_util.hh:142
T wholeQuadMode(T val)
Definition inst_util.hh:90
ScalarRegI32 countZeroBits(T val)
Definition inst_util.hh:121
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::shared_ptr< GPUDynInst > GPUDynInstPtr
Definition misc.hh:49
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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