gem5  v21.1.0.2
sve_mem.cc
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37 
39 
40 namespace gem5
41 {
42 
43 namespace ArmISA
44 {
45 
46 std::string
48  Addr pc, const loader::SymbolTable *symtab) const
49 {
50  std::stringstream ss;
51  printMnemonic(ss, "", false);
52  printVecReg(ss, dest, true);
53  ccprintf(ss, ", [");
55  if (imm != 0) {
56  ccprintf(ss, ", #%d, mul vl", imm);
57  }
58  ccprintf(ss, "]");
59  return ss.str();
60 }
61 
62 std::string
64  Addr pc, const loader::SymbolTable *symtab) const
65 {
66  std::stringstream ss;
67  printMnemonic(ss, "", false);
69  ccprintf(ss, ", [");
71  if (imm != 0) {
72  ccprintf(ss, ", #%d, mul vl", imm);
73  }
74  ccprintf(ss, "]");
75  return ss.str();
76 }
77 
78 std::string
80  Addr pc, const loader::SymbolTable *symtab) const
81 {
82  // TODO: add suffix to transfer register and scaling factor (LSL #<x>)
83  std::stringstream ss;
84  printMnemonic(ss, "", false);
85  ccprintf(ss, "{");
86  printVecReg(ss, dest, true);
87  ccprintf(ss, "}, ");
89  ccprintf(ss, "/z, ");
90  ccprintf(ss, ", [");
92  ccprintf(ss, ", ");
94  ccprintf(ss, "]");
95  return ss.str();
96 }
97 
98 std::string
100  Addr pc, const loader::SymbolTable *symtab) const
101 {
102  // TODO: add suffix to transfer register
103  std::stringstream ss;
104  printMnemonic(ss, "", false);
105  ccprintf(ss, "{");
106  printVecReg(ss, dest, true);
107  ccprintf(ss, "}, ");
109  ccprintf(ss, "/z, ");
110  ccprintf(ss, ", [");
111  printIntReg(ss, base);
112  if (imm != 0) {
113  ccprintf(ss, ", #%d, mul vl", imm);
114  }
115  ccprintf(ss, "]");
116  return ss.str();
117 }
118 
119 } // namespace ArmISA
120 } // namespace gem5
gem5::ArmISA::ArmStaticInst::printVecReg
void printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
Definition: static_inst.cc:351
gem5::ArmISA::SveContigMemSI::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:99
gem5::ArmISA::SveMemPredFillSpill::dest
IntRegIndex dest
Definition: sve_mem.hh:79
gem5::ArmISA::SveMemPredFillSpill::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:63
gem5::ArmISA::SveMemPredFillSpill::imm
uint64_t imm
Definition: sve_mem.hh:81
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::SveContigMemSS::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:79
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::SveMemPredFillSpill::base
IntRegIndex base
Definition: sve_mem.hh:80
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::SveMemVecFillSpill::imm
uint64_t imm
Definition: sve_mem.hh:55
gem5::ArmISA::SveMemVecFillSpill::base
IntRegIndex base
Definition: sve_mem.hh:54
gem5::ArmISA::SveMemVecFillSpill::dest
IntRegIndex dest
Definition: sve_mem.hh:53
gem5::ArmISA::SveContigMemSS::offset
IntRegIndex offset
Definition: sve_mem.hh:108
gem5::ArmISA::SveContigMemSI::imm
uint64_t imm
Definition: sve_mem.hh:135
gem5::ArmISA::ArmStaticInst::printVecPredReg
void printVecPredReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:358
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SveContigMemSI::gp
IntRegIndex gp
Definition: sve_mem.hh:133
gem5::ArmISA::SveMemVecFillSpill::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:47
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::SveContigMemSI::dest
IntRegIndex dest
Definition: sve_mem.hh:132
gem5::ArmISA::SveContigMemSS::dest
IntRegIndex dest
Definition: sve_mem.hh:105
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
sve_mem.hh
gem5::ArmISA::SveContigMemSI::base
IntRegIndex base
Definition: sve_mem.hh:134
gem5::ArmISA::SveContigMemSS::gp
IntRegIndex gp
Definition: sve_mem.hh:106
gem5::ArmISA::SveContigMemSS::base
IntRegIndex base
Definition: sve_mem.hh:107

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