gem5  v21.1.0.2
sve_mem.hh
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37 
38 #ifndef __ARCH_ARM_SVE_MEM_HH__
39 #define __ARCH_ARM_SVE_MEM_HH__
40 
42 #include "arch/arm/tlb.hh"
43 
44 namespace gem5
45 {
46 
47 namespace ArmISA
48 {
49 
51 {
52  protected:
53  IntRegIndex dest;
54  IntRegIndex base;
55  uint64_t imm;
56 
58  bool baseIsSP;
59 
60  unsigned memAccessFlags;
61 
62  SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst,
63  OpClass __opClass, IntRegIndex _dest,
64  IntRegIndex _base, uint64_t _imm)
65  : ArmStaticInst(mnem, _machInst, __opClass),
66  dest(_dest), base(_base), imm(_imm),
67  memAccessFlags(ArmISA::TLB::AllowUnaligned)
68  {
69  baseIsSP = isSP(_base);
70  }
71 
72  std::string generateDisassembly(
73  Addr pc, const loader::SymbolTable *symtab) const override;
74 };
75 
77 {
78  protected:
79  IntRegIndex dest;
80  IntRegIndex base;
81  uint64_t imm;
82 
84  bool baseIsSP;
85 
86  unsigned memAccessFlags;
87 
88  SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst,
89  OpClass __opClass, IntRegIndex _dest,
90  IntRegIndex _base, uint64_t _imm)
91  : ArmStaticInst(mnem, _machInst, __opClass),
92  dest(_dest), base(_base), imm(_imm),
93  memAccessFlags(ArmISA::TLB::AllowUnaligned)
94  {
95  baseIsSP = isSP(_base);
96  }
97 
98  std::string generateDisassembly(
99  Addr pc, const loader::SymbolTable *symtab) const override;
100 };
101 
103 {
104  protected:
105  IntRegIndex dest;
106  IntRegIndex gp;
107  IntRegIndex base;
108  IntRegIndex offset;
109 
111  bool baseIsSP;
112 
113  unsigned memAccessFlags;
114 
115  SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
116  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
117  IntRegIndex _offset)
118  : ArmStaticInst(mnem, _machInst, __opClass),
119  dest(_dest), gp(_gp), base(_base), offset(_offset),
120  memAccessFlags(ArmISA::TLB::AllowUnaligned)
121  {
122  baseIsSP = isSP(_base);
123  }
124 
125  std::string generateDisassembly(
126  Addr pc, const loader::SymbolTable *symtab) const override;
127 };
128 
130 {
131  protected:
132  IntRegIndex dest;
133  IntRegIndex gp;
134  IntRegIndex base;
135  uint64_t imm;
136 
138  bool baseIsSP;
139 
140  unsigned memAccessFlags;
141 
142  SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
143  IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
144  uint64_t _imm)
145  : ArmStaticInst(mnem, _machInst, __opClass),
146  dest(_dest), gp(_gp), base(_base), imm(_imm),
147  memAccessFlags(ArmISA::TLB::AllowUnaligned)
148  {
149  baseIsSP = isSP(_base);
150  }
151 
152  std::string generateDisassembly(
153  Addr pc, const loader::SymbolTable *symtab) const override;
154 };
155 
156 } // namespace ArmISA
157 } // namespace gem5
158 
159 #endif // __ARCH_ARM_SVE_MEM_HH__
gem5::ArmISA::SveContigMemSI::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:99
gem5::ArmISA::isSP
static bool isSP(IntRegIndex reg)
Definition: int.hh:529
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::SveMemPredFillSpill::dest
IntRegIndex dest
Definition: sve_mem.hh:79
gem5::ArmISA::SveMemPredFillSpill::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:63
gem5::ArmISA::SveMemPredFillSpill::imm
uint64_t imm
Definition: sve_mem.hh:81
gem5::ArmISA::SveContigMemSI
Definition: sve_mem.hh:129
gem5::ArmISA::SveMemVecFillSpill::SveMemVecFillSpill
SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, uint64_t _imm)
Definition: sve_mem.hh:62
gem5::ArmISA::TLB
Definition: tlb.hh:109
gem5::ArmISA::SveContigMemSS::baseIsSP
bool baseIsSP
True if the base register is SP (used for SP alignment checking).
Definition: sve_mem.hh:111
gem5::ArmISA::SveContigMemSS::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:79
gem5::loader::SymbolTable
Definition: symtab.hh:65
tlb.hh
gem5::ArmISA::SveMemPredFillSpill::base
IntRegIndex base
Definition: sve_mem.hh:80
gem5::ArmISA::SveMemVecFillSpill::imm
uint64_t imm
Definition: sve_mem.hh:55
gem5::ArmISA::SveMemVecFillSpill::base
IntRegIndex base
Definition: sve_mem.hh:54
gem5::ArmISA::SveMemPredFillSpill::SveMemPredFillSpill
SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, uint64_t _imm)
Definition: sve_mem.hh:88
gem5::ArmISA::SveContigMemSI::SveContigMemSI
SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, uint64_t _imm)
Definition: sve_mem.hh:142
gem5::ArmISA::SveMemVecFillSpill
Definition: sve_mem.hh:50
gem5::ArmISA::SveMemVecFillSpill::dest
IntRegIndex dest
Definition: sve_mem.hh:53
gem5::ArmISA::SveContigMemSS::offset
IntRegIndex offset
Definition: sve_mem.hh:108
gem5::ArmISA::SveContigMemSI::imm
uint64_t imm
Definition: sve_mem.hh:135
gem5::ArmISA::SveMemVecFillSpill::baseIsSP
bool baseIsSP
True if the base register is SP (used for SP alignment checking).
Definition: sve_mem.hh:58
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::SveContigMemSI::baseIsSP
bool baseIsSP
True if the base register is SP (used for SP alignment checking).
Definition: sve_mem.hh:138
gem5::ArmISA::SveContigMemSI::gp
IntRegIndex gp
Definition: sve_mem.hh:133
gem5::ArmISA::SveMemVecFillSpill::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: sve_mem.cc:47
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::SveMemPredFillSpill
Definition: sve_mem.hh:76
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::SveContigMemSS::memAccessFlags
unsigned memAccessFlags
Definition: sve_mem.hh:113
gem5::ArmISA::SveContigMemSI::dest
IntRegIndex dest
Definition: sve_mem.hh:132
gem5::ArmISA::SveContigMemSI::memAccessFlags
unsigned memAccessFlags
Definition: sve_mem.hh:140
gem5::ArmISA::SveMemPredFillSpill::memAccessFlags
unsigned memAccessFlags
Definition: sve_mem.hh:86
gem5::ArmISA::SveContigMemSS::dest
IntRegIndex dest
Definition: sve_mem.hh:105
gem5::ArmISA::SveMemVecFillSpill::memAccessFlags
unsigned memAccessFlags
Definition: sve_mem.hh:60
gem5::ArmISA::SveMemPredFillSpill::baseIsSP
bool baseIsSP
True if the base register is SP (used for SP alignment checking).
Definition: sve_mem.hh:84
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::SveContigMemSS::SveContigMemSS
SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, IntRegIndex _offset)
Definition: sve_mem.hh:115
gem5::ArmISA::SveContigMemSS
Definition: sve_mem.hh:102
gem5::ArmISA::SveContigMemSI::base
IntRegIndex base
Definition: sve_mem.hh:134
gem5::ArmISA::SveContigMemSS::gp
IntRegIndex gp
Definition: sve_mem.hh:106
gem5::ArmISA::SveContigMemSS::base
IntRegIndex base
Definition: sve_mem.hh:107

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