sve_mem.hh

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/*
 * Copyright (c) 2017 ARM Limited
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 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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#ifndef __ARCH_ARM_SVE_MEM_HH__
#define __ARCH_ARM_SVE_MEM_HH__
 
#include "arch/arm/insts/static_inst.hh"
#include "arch/arm/tlb.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
class SveMemVecFillSpill : public ArmStaticInst
{
  protected:
    IntRegIndex dest;
    IntRegIndex base;
    uint64_t imm;
 
    bool baseIsSP;
 
    unsigned memAccessFlags;
 
    SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst,
                       OpClass __opClass, IntRegIndex _dest,
                       IntRegIndex _base, uint64_t _imm)
        : ArmStaticInst(mnem, _machInst, __opClass),
          dest(_dest), base(_base), imm(_imm),
          memAccessFlags(ArmISA::TLB::AllowUnaligned)
    {
        baseIsSP = isSP(_base);
    }
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveMemPredFillSpill : public ArmStaticInst
{
  protected:
    IntRegIndex dest;
    IntRegIndex base;
    uint64_t imm;
 
    bool baseIsSP;
 
    unsigned memAccessFlags;
 
    SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst,
                        OpClass __opClass, IntRegIndex _dest,
                        IntRegIndex _base, uint64_t _imm)
        : ArmStaticInst(mnem, _machInst, __opClass),
          dest(_dest), base(_base), imm(_imm),
          memAccessFlags(ArmISA::TLB::AllowUnaligned)
    {
        baseIsSP = isSP(_base);
    }
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveContigMemSS : public ArmStaticInst
{
  protected:
    IntRegIndex dest;
    IntRegIndex gp;
    IntRegIndex base;
    IntRegIndex offset;
 
    bool baseIsSP;
 
    unsigned memAccessFlags;
 
    SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                   IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
                   IntRegIndex _offset)
        : ArmStaticInst(mnem, _machInst, __opClass),
          dest(_dest), gp(_gp), base(_base), offset(_offset),
          memAccessFlags(ArmISA::TLB::AllowUnaligned)
    {
        baseIsSP = isSP(_base);
    }
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveContigMemSI : public ArmStaticInst
{
  protected:
    IntRegIndex dest;
    IntRegIndex gp;
    IntRegIndex base;
    uint64_t imm;
 
    bool baseIsSP;
 
    unsigned memAccessFlags;
 
    SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                   IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
                   uint64_t _imm)
        : ArmStaticInst(mnem, _machInst, __opClass),
          dest(_dest), gp(_gp), base(_base), imm(_imm),
          memAccessFlags(ArmISA::TLB::AllowUnaligned)
    {
        baseIsSP = isSP(_base);
    }
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif  // __ARCH_ARM_SVE_MEM_HH__