gem5  v21.1.0.2
static_inst.cc
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41 
43 
44 #include "arch/arm/faults.hh"
45 #include "arch/arm/isa.hh"
46 #include "arch/arm/self_debug.hh"
47 #include "arch/arm/utility.hh"
48 #include "base/condcodes.hh"
49 #include "base/cprintf.hh"
50 #include "base/loader/symtab.hh"
51 #include "cpu/reg_class.hh"
52 
53 namespace gem5
54 {
55 
56 namespace ArmISA
57 {
58 // Shift Rm by an immediate value
59 int32_t
60 ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
61  uint32_t type, uint32_t cfval) const
62 {
63  assert(shamt < 32);
64  ArmShiftType shiftType;
65  shiftType = (ArmShiftType)type;
66 
67  switch (shiftType)
68  {
69  case LSL:
70  return base << shamt;
71  case LSR:
72  if (shamt == 0)
73  return 0;
74  else
75  return base >> shamt;
76  case ASR:
77  if (shamt == 0)
78  return (base >> 31) | -((base & (1 << 31)) >> 31);
79  else
80  return (base >> shamt) | -((base & (1 << 31)) >> shamt);
81  case ROR:
82  if (shamt == 0)
83  return (cfval << 31) | (base >> 1); // RRX
84  else
85  return (base << (32 - shamt)) | (base >> shamt);
86  default:
87  ccprintf(std::cerr, "Unhandled shift type\n");
88  exit(1);
89  break;
90  }
91  return 0;
92 }
93 
94 int64_t
95 ArmStaticInst::shiftReg64(uint64_t base, uint64_t shiftAmt,
96  ArmShiftType type, uint8_t width) const
97 {
98  shiftAmt = shiftAmt % width;
99  ArmShiftType shiftType;
100  shiftType = (ArmShiftType)type;
101 
102  switch (shiftType)
103  {
104  case LSL:
105  return base << shiftAmt;
106  case LSR:
107  if (shiftAmt == 0)
108  return base;
109  else
110  return (base & mask(width)) >> shiftAmt;
111  case ASR:
112  if (shiftAmt == 0) {
113  return base;
114  } else {
115  int sign_bit = bits(base, intWidth - 1);
116  base >>= shiftAmt;
117  base = sign_bit ? (base | ~mask(intWidth - shiftAmt)) : base;
118  return base & mask(intWidth);
119  }
120  case ROR:
121  if (shiftAmt == 0)
122  return base;
123  else
124  return (base << (width - shiftAmt)) | (base >> shiftAmt);
125  default:
126  ccprintf(std::cerr, "Unhandled shift type\n");
127  exit(1);
128  break;
129  }
130  return 0;
131 }
132 
133 int64_t
135  uint64_t shiftAmt, uint8_t width) const
136 {
137  bool sign_extend = false;
138  int len = 0;
139  switch (type) {
140  case UXTB:
141  len = 8;
142  break;
143  case UXTH:
144  len = 16;
145  break;
146  case UXTW:
147  len = 32;
148  break;
149  case UXTX:
150  len = 64;
151  break;
152  case SXTB:
153  len = 8;
154  sign_extend = true;
155  break;
156  case SXTH:
157  len = 16;
158  sign_extend = true;
159  break;
160  case SXTW:
161  len = 32;
162  sign_extend = true;
163  break;
164  case SXTX:
165  len = 64;
166  sign_extend = true;
167  break;
168  }
169  len = len <= width - shiftAmt ? len : width - shiftAmt;
170  uint64_t tmp = (uint64_t) bits(base, len - 1, 0) << shiftAmt;
171  if (sign_extend) {
172  int sign_bit = bits(tmp, len + shiftAmt - 1);
173  tmp = sign_bit ? (tmp | ~mask(len + shiftAmt)) : tmp;
174  }
175  return tmp & mask(width);
176 }
177 
178 // Shift Rm by Rs
179 int32_t
180 ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
181  uint32_t type, uint32_t cfval) const
182 {
183  enum ArmShiftType shiftType;
184  shiftType = (enum ArmShiftType) type;
185 
186  switch (shiftType)
187  {
188  case LSL:
189  if (shamt >= 32)
190  return 0;
191  else
192  return base << shamt;
193  case LSR:
194  if (shamt >= 32)
195  return 0;
196  else
197  return base >> shamt;
198  case ASR:
199  if (shamt >= 32)
200  return (base >> 31) | -((base & (1 << 31)) >> 31);
201  else
202  return (base >> shamt) | -((base & (1 << 31)) >> shamt);
203  case ROR:
204  shamt = shamt & 0x1f;
205  if (shamt == 0)
206  return base;
207  else
208  return (base << (32 - shamt)) | (base >> shamt);
209  default:
210  ccprintf(std::cerr, "Unhandled shift type\n");
211  exit(1);
212  break;
213  }
214  return 0;
215 }
216 
217 
218 // Generate C for a shift by immediate
219 bool
220 ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
221  uint32_t type, uint32_t cfval) const
222 {
223  enum ArmShiftType shiftType;
224  shiftType = (enum ArmShiftType) type;
225 
226  switch (shiftType)
227  {
228  case LSL:
229  if (shamt == 0)
230  return cfval;
231  else
232  return (base >> (32 - shamt)) & 1;
233  case LSR:
234  if (shamt == 0)
235  return (base >> 31);
236  else
237  return (base >> (shamt - 1)) & 1;
238  case ASR:
239  if (shamt == 0)
240  return (base >> 31);
241  else
242  return (base >> (shamt - 1)) & 1;
243  case ROR:
244  shamt = shamt & 0x1f;
245  if (shamt == 0)
246  return (base & 1); // RRX
247  else
248  return (base >> (shamt - 1)) & 1;
249  default:
250  ccprintf(std::cerr, "Unhandled shift type\n");
251  exit(1);
252  break;
253  }
254  return 0;
255 }
256 
257 
258 // Generate C for a shift by Rs
259 bool
260 ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
261  uint32_t type, uint32_t cfval) const
262 {
263  enum ArmShiftType shiftType;
264  shiftType = (enum ArmShiftType) type;
265 
266  if (shamt == 0)
267  return cfval;
268 
269  switch (shiftType)
270  {
271  case LSL:
272  if (shamt > 32)
273  return 0;
274  else
275  return (base >> (32 - shamt)) & 1;
276  case LSR:
277  if (shamt > 32)
278  return 0;
279  else
280  return (base >> (shamt - 1)) & 1;
281  case ASR:
282  if (shamt > 32)
283  shamt = 32;
284  return (base >> (shamt - 1)) & 1;
285  case ROR:
286  shamt = shamt & 0x1f;
287  if (shamt == 0)
288  shamt = 32;
289  return (base >> (shamt - 1)) & 1;
290  default:
291  ccprintf(std::cerr, "Unhandled shift type\n");
292  exit(1);
293  break;
294  }
295  return 0;
296 }
297 
298 void
299 ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx,
300  uint8_t opWidth) const
301 {
302  if (opWidth == 0)
303  opWidth = intWidth;
304  if (aarch64) {
305  if (reg_idx == INTREG_UREG0)
306  ccprintf(os, "ureg0");
307  else if (reg_idx == INTREG_SPX)
308  ccprintf(os, "%s%s", (opWidth == 32) ? "w" : "", "sp");
309  else if (reg_idx == INTREG_X31)
310  ccprintf(os, "%szr", (opWidth == 32) ? "w" : "x");
311  else
312  ccprintf(os, "%s%d", (opWidth == 32) ? "w" : "x", reg_idx);
313  } else {
314  switch (reg_idx) {
315  case PCReg:
316  ccprintf(os, "pc");
317  break;
318  case StackPointerReg:
319  ccprintf(os, "sp");
320  break;
321  case FramePointerReg:
322  ccprintf(os, "fp");
323  break;
324  case ReturnAddressReg:
325  ccprintf(os, "lr");
326  break;
327  default:
328  ccprintf(os, "r%d", reg_idx);
329  break;
330  }
331  }
332 }
333 
334 void ArmStaticInst::printPFflags(std::ostream &os, int flag) const
335 {
336  const char *flagtoprfop[]= { "PLD", "PLI", "PST", "Reserved"};
337  const char *flagtotarget[] = { "L1", "L2", "L3", "Reserved"};
338  const char *flagtopolicy[] = { "KEEP", "STRM"};
339 
340  ccprintf(os, "%s%s%s", flagtoprfop[(flag>>3)&3],
341  flagtotarget[(flag>>1)&3], flagtopolicy[flag&1]);
342 }
343 
344 void
345 ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
346 {
347  ccprintf(os, "f%d", reg_idx);
348 }
349 
350 void
351 ArmStaticInst::printVecReg(std::ostream &os, RegIndex reg_idx,
352  bool isSveVecReg) const
353 {
354  ccprintf(os, "%s%d", isSveVecReg ? "z" : "v", reg_idx);
355 }
356 
357 void
358 ArmStaticInst::printVecPredReg(std::ostream &os, RegIndex reg_idx) const
359 {
360  ccprintf(os, "p%d", reg_idx);
361 }
362 
363 void
364 ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
365 {
366  ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
367 }
368 
369 void
370 ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
371 {
372  assert(reg_idx < NUM_MISCREGS);
373  ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);
374 }
375 
376 void
378  const std::string &suffix,
379  bool withPred,
380  bool withCond64,
381  ConditionCode cond64) const
382 {
383  os << " " << mnemonic;
384  if (withPred && !aarch64) {
385  printCondition(os, machInst.condCode);
386  os << suffix;
387  } else if (withCond64) {
388  os << ".";
389  printCondition(os, cond64);
390  os << suffix;
391  }
392  if (machInst.bigThumb)
393  os << ".w";
394  os << " ";
395 }
396 
397 void
398 ArmStaticInst::printTarget(std::ostream &os, Addr target,
399  const loader::SymbolTable *symtab) const
400 {
401  if (symtab) {
402  auto it = symtab->findNearest(target);
403  if (it != symtab->end()) {
404  ccprintf(os, "<%s", it->name);
405  Addr delta = target - it->address;
406  if (delta)
407  ccprintf(os, "+%d>", delta);
408  else
409  ccprintf(os, ">");
410  return;
411  }
412  }
413  ccprintf(os, "%#x", target);
414 }
415 
416 void
418  unsigned code,
419  bool noImplicit) const
420 {
421  switch (code) {
422  case COND_EQ:
423  os << "eq";
424  break;
425  case COND_NE:
426  os << "ne";
427  break;
428  case COND_CS:
429  os << "cs";
430  break;
431  case COND_CC:
432  os << "cc";
433  break;
434  case COND_MI:
435  os << "mi";
436  break;
437  case COND_PL:
438  os << "pl";
439  break;
440  case COND_VS:
441  os << "vs";
442  break;
443  case COND_VC:
444  os << "vc";
445  break;
446  case COND_HI:
447  os << "hi";
448  break;
449  case COND_LS:
450  os << "ls";
451  break;
452  case COND_GE:
453  os << "ge";
454  break;
455  case COND_LT:
456  os << "lt";
457  break;
458  case COND_GT:
459  os << "gt";
460  break;
461  case COND_LE:
462  os << "le";
463  break;
464  case COND_AL:
465  // This one is implicit.
466  if (noImplicit)
467  os << "al";
468  break;
469  case COND_UC:
470  // Unconditional.
471  if (noImplicit)
472  os << "uc";
473  break;
474  default:
475  panic("Unrecognized condition code %d.\n", code);
476  }
477 }
478 
479 void
481  const loader::SymbolTable *symtab,
482  const std::string &prefix,
483  const Addr addr,
484  const std::string &suffix) const
485 {
486  if (symtab) {
487  auto it = symtab->findNearest(addr);
488  if (it != symtab->end()) {
489  ccprintf(os, "%s%s", prefix, it->name);
490  if (it->address != addr)
491  ccprintf(os, "+%d", addr - it->address);
492  ccprintf(os, suffix);
493  }
494  }
495 }
496 
497 void
499  IntRegIndex rm,
500  bool immShift,
501  uint32_t shiftAmt,
502  IntRegIndex rs,
503  ArmShiftType type) const
504 {
505  bool firstOp = false;
506 
507  if (rm != INTREG_ZERO) {
508  printIntReg(os, rm);
509  }
510 
511  bool done = false;
512 
513  if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
514  shiftAmt = 32;
515 
516  switch (type) {
517  case LSL:
518  if (immShift && shiftAmt == 0) {
519  done = true;
520  break;
521  }
522  if (!firstOp)
523  os << ", ";
524  os << "LSL";
525  break;
526  case LSR:
527  if (!firstOp)
528  os << ", ";
529  os << "LSR";
530  break;
531  case ASR:
532  if (!firstOp)
533  os << ", ";
534  os << "ASR";
535  break;
536  case ROR:
537  if (immShift && shiftAmt == 0) {
538  if (!firstOp)
539  os << ", ";
540  os << "RRX";
541  done = true;
542  break;
543  }
544  if (!firstOp)
545  os << ", ";
546  os << "ROR";
547  break;
548  default:
549  panic("Tried to disassemble unrecognized shift type.\n");
550  }
551  if (!done) {
552  if (!firstOp)
553  os << " ";
554  if (immShift)
555  os << "#" << shiftAmt;
556  else
557  printIntReg(os, rs);
558  }
559 }
560 
561 void
562 ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
563  IntRegIndex rm, ArmExtendType type,
564  int64_t shiftAmt) const
565 {
566  if (!firstOperand)
567  ccprintf(os, ", ");
568  printIntReg(os, rm);
569  if (type == UXTX && shiftAmt == 0)
570  return;
571  switch (type) {
572  case UXTB: ccprintf(os, ", UXTB");
573  break;
574  case UXTH: ccprintf(os, ", UXTH");
575  break;
576  case UXTW: ccprintf(os, ", UXTW");
577  break;
578  case UXTX: ccprintf(os, ", LSL");
579  break;
580  case SXTB: ccprintf(os, ", SXTB");
581  break;
582  case SXTH: ccprintf(os, ", SXTH");
583  break;
584  case SXTW: ccprintf(os, ", SXTW");
585  break;
586  case SXTX: ccprintf(os, ", SXTW");
587  break;
588  }
589  if (type == UXTX || shiftAmt)
590  ccprintf(os, " #%d", shiftAmt);
591 }
592 
593 void
594 ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
595  bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
596  IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
597  ArmShiftType type, uint64_t imm) const
598 {
599  printMnemonic(os, s ? "s" : "");
600  bool firstOp = true;
601 
602  // Destination
603  if (rd != INTREG_ZERO) {
604  firstOp = false;
605  printIntReg(os, rd);
606  }
607 
608  // Source 1.
609  if (rn != INTREG_ZERO) {
610  if (!firstOp)
611  os << ", ";
612  firstOp = false;
613  printIntReg(os, rn);
614  }
615 
616  if (!firstOp)
617  os << ", ";
618  if (withImm) {
619  ccprintf(os, "#%ld", imm);
620  } else {
621  printShiftOperand(os, rm, immShift, shiftAmt, rs, type);
622  }
623 }
624 
625 std::string
627  const loader::SymbolTable *symtab) const
628 {
629  std::stringstream ss;
630  printMnemonic(ss);
631  return ss.str();
632 }
633 
634 Fault
636 {
637  const auto tc = xc->tcBase();
638  const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
639  const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
640  if ((EL2Enabled(tc) && !ELIs32(tc, EL2) &&
641  (hcr.tge || mdcr.tde)) || !ELIs32(tc, EL1)) {
642  // Route to AArch64 Software Breakpoint
643  return std::make_shared<SoftwareBreakpoint>(machInst, imm);
644  } else {
645  // Execute AArch32 Software Breakpoint
646  return std::make_shared<PrefetchAbort>(readPC(xc),
648  false,
651  }
652 }
653 
654 Fault
656 {
657  switch (el) {
658  case EL1:
659  return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
661  case EL2:
662  return std::make_shared<HypervisorTrap>(machInst, 0x1E00000,
664  case EL3:
665  return std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000,
667 
668  default:
669  panic("Illegal EL in advSIMDFPAccessTrap64\n");
670  }
671 }
672 
673 
674 Fault
676 {
677  if (currEL(tc) <= EL2 && EL2Enabled(tc)) {
678  bool trap_el2 = false;
679  CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL2);
680  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
681  if (HaveVirtHostExt(tc) && hcr.e2h == 0x1) {
682  switch (cptr_en_check.fpen) {
683  case 0:
684  case 2:
685  trap_el2 = !(currEL(tc) == EL1 && hcr.tge == 1);
686  break;
687  case 1:
688  trap_el2 = (currEL(tc) == EL0 && hcr.tge == 1);
689  break;
690  default:
691  trap_el2 = false;
692  break;
693  }
694  } else if (cptr_en_check.tfp) {
695  trap_el2 = true;
696  }
697 
698  if (trap_el2) {
699  return advSIMDFPAccessTrap64(EL2);
700  }
701  }
702 
703  if (ArmSystem::haveSecurity(tc)) {
704  CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
705  if (cptr_en_check.tfp) {
706  return advSIMDFPAccessTrap64(EL3);
707  }
708  }
709 
710  return NoFault;
711 }
712 
713 Fault
715  CPSR cpsr, CPACR cpacr) const
716 {
717  const ExceptionLevel el = currEL(tc);
718  if ((el == EL0 && cpacr.fpen != 0x3) ||
719  (el == EL1 && !(cpacr.fpen & 0x1)))
720  return advSIMDFPAccessTrap64(EL1);
721 
722  return checkFPAdvSIMDTrap64(tc, cpsr);
723 }
724 
725 Fault
727  CPSR cpsr, CPACR cpacr,
728  NSACR nsacr, FPEXC fpexc,
729  bool fpexc_check, bool advsimd) const
730 {
731  const bool have_virtualization = ArmSystem::haveVirtualization(tc);
732  const bool have_security = ArmSystem::haveSecurity(tc);
733  const bool is_secure = isSecure(tc);
734  const ExceptionLevel cur_el = currEL(tc);
735 
736  if (cur_el == EL0 && ELIs64(tc, EL1))
737  return checkFPAdvSIMDEnabled64(tc, cpsr, cpacr);
738 
739  uint8_t cpacr_cp10 = cpacr.cp10;
740  bool cpacr_asedis = cpacr.asedis;
741 
742  if (have_security && !ELIs64(tc, EL3) && !is_secure) {
743  if (nsacr.nsasedis)
744  cpacr_asedis = true;
745  if (nsacr.cp10 == 0)
746  cpacr_cp10 = 0;
747  }
748 
749  if (cur_el != EL2) {
750  if (advsimd && cpacr_asedis)
751  return disabledFault();
752 
753  if ((cur_el == EL0 && cpacr_cp10 != 0x3) ||
754  (cur_el != EL0 && !(cpacr_cp10 & 0x1)))
755  return disabledFault();
756  }
757 
758  if (fpexc_check && !fpexc.en)
759  return disabledFault();
760 
761  // -- aarch32/exceptions/traps/AArch32.CheckFPAdvSIMDTrap --
762 
763  if (have_virtualization && !is_secure && ELIs64(tc, EL2))
764  return checkFPAdvSIMDTrap64(tc, cpsr);
765 
766  if (have_virtualization && !is_secure) {
767  HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
768  bool hcptr_cp10 = hcptr.tcp10;
769  bool hcptr_tase = hcptr.tase;
770 
771  if (have_security && !ELIs64(tc, EL3) && !is_secure) {
772  if (nsacr.nsasedis)
773  hcptr_tase = true;
774  if (nsacr.cp10)
775  hcptr_cp10 = true;
776  }
777 
778  if ((advsimd && hcptr_tase) || hcptr_cp10) {
779  const uint32_t iss = advsimd ? (1 << 5) : 0xA;
780  if (cur_el == EL2) {
781  return std::make_shared<UndefinedInstruction>(
782  machInst, iss,
784  } else {
785  return std::make_shared<HypervisorTrap>(
786  machInst, iss,
788  }
789 
790  }
791  }
792 
793  if (have_security && ELIs64(tc, EL3)) {
794  HCPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
795  if (cptr_en_check.tfp)
796  return advSIMDFPAccessTrap64(EL3);
797  }
798 
799  return NoFault;
800 }
801 
802 inline bool
804  ExceptionLevel tgtEl,
805  bool isWfe) const
806 {
807  bool trap = false;
808  SCTLR sctlr = ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1));
809  HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
810  SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
811 
812  switch (tgtEl) {
813  case EL1:
814  trap = isWfe? !sctlr.ntwe : !sctlr.ntwi;
815  break;
816  case EL2:
817  trap = isWfe? hcr.twe : hcr.twi;
818  break;
819  case EL3:
820  trap = isWfe? scr.twe : scr.twi;
821  break;
822  default:
823  break;
824  }
825 
826  return trap;
827 }
828 
829 Fault
831  ExceptionLevel targetEL,
832  bool isWfe) const
833 {
834  // Check if target exception level is implemented.
835  assert(ArmSystem::haveEL(tc, targetEL));
836 
837  // Check for routing to AArch64: this happens if the
838  // target exception level (where the trap will be handled)
839  // is using aarch64
840  if (ELIs64(tc, targetEL)) {
841  return checkForWFxTrap64(tc, targetEL, isWfe);
842  }
843 
844  // Check if processor needs to trap at selected exception level
845  bool trap = isWFxTrapping(tc, targetEL, isWfe);
846 
847  if (trap) {
848  uint32_t iss = isWfe? 0x1E00001 : /* WFE Instruction syndrome */
849  0x1E00000; /* WFI Instruction syndrome */
850  switch (targetEL) {
851  case EL1:
852  return std::make_shared<UndefinedInstruction>(
853  machInst, iss,
855  case EL2:
856  return std::make_shared<HypervisorTrap>(machInst, iss,
858  case EL3:
859  return std::make_shared<SecureMonitorTrap>(machInst, iss,
861  default:
862  panic("Unrecognized Exception Level: %d\n", targetEL);
863  }
864  }
865 
866  return NoFault;
867 }
868 
869 Fault
871  ExceptionLevel targetEL,
872  bool isWfe) const
873 {
874  // Check if target exception level is implemented.
875  assert(ArmSystem::haveEL(tc, targetEL));
876 
877  // Check if processor needs to trap at selected exception level
878  bool trap = isWFxTrapping(tc, targetEL, isWfe);
879 
880  if (trap) {
881  uint32_t iss = isWfe? 0x1E00001 : /* WFE Instruction syndrome */
882  0x1E00000; /* WFI Instruction syndrome */
883  switch (targetEL) {
884  case EL1:
885  return std::make_shared<SupervisorTrap>(machInst, iss,
887  case EL2:
888  return std::make_shared<HypervisorTrap>(machInst, iss,
890  case EL3:
891  return std::make_shared<SecureMonitorTrap>(machInst, iss,
893  default:
894  panic("Unrecognized Exception Level: %d\n", targetEL);
895  }
896  }
897 
898  return NoFault;
899 }
900 
901 Fault
903  CPSR cpsr, SCR scr,
904  bool isWfe) const
905 {
906  Fault fault = NoFault;
907  ExceptionLevel curr_el = currEL(tc);
908 
909  if (curr_el == EL0) {
910  fault = checkForWFxTrap32(tc, EL1, isWfe);
911  }
912 
913  if ((fault == NoFault) && EL2Enabled(tc) &&
914  ((curr_el == EL0) || (curr_el == EL1))) {
915 
916  fault = checkForWFxTrap32(tc, EL2, isWfe);
917  }
918 
919  if ((fault == NoFault) &&
920  ArmSystem::haveEL(tc, EL3) && curr_el != EL3) {
921  fault = checkForWFxTrap32(tc, EL3, isWfe);
922  }
923 
924  return fault;
925 }
926 
927 Fault
929 {
930  bool setend_disabled(false);
931  ExceptionLevel pstate_el = currEL(tc);
932 
933  if (pstate_el == EL2) {
934  setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(MISCREG_HSCTLR)).sed;
935  } else {
936  // Please note: in the armarm pseudocode there is a distinction
937  // whether EL1 is aarch32 or aarch64:
938  // if ELUsingAArch32(EL1) then SCTLR.SED else SCTLR[].SED;
939  // Considering that SETEND is aarch32 only, ELUsingAArch32(EL1)
940  // will always be true (hence using SCTLR.SED) except for
941  // instruction executed at EL0, and with an AArch64 EL1.
942  // In this case SCTLR_EL1 will be used. In gem5 the register is
943  // mapped to SCTLR_ns. We can safely use SCTLR and choose the
944  // appropriate bank version.
945 
946  // Get the index of the banked version of SCTLR:
947  // SCTLR_s or SCTLR_ns.
948  auto banked_sctlr = snsBankedIndex(
949  MISCREG_SCTLR, tc, !isSecure(tc));
950 
951  // SCTLR.SED bit is enabling/disabling the ue of SETEND instruction.
952  setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(banked_sctlr)).sed;
953  }
954 
955  return setend_disabled ? undefinedFault32(tc, pstate_el) :
956  NoFault;
957 }
958 
959 Fault
961  ExceptionLevel pstateEL) const
962 {
963  // Even if we are running in aarch32, the fault might be dealt with in
964  // aarch64 ISA.
965  if (generalExceptionsToAArch64(tc, pstateEL)) {
966  return undefinedFault64(tc, pstateEL);
967  } else {
968  // Please note: according to the ARM ARM pseudocode we should handle
969  // the case when EL2 is aarch64 and HCR.TGE is 1 as well.
970  // However this case is already handled by the routeToHyp method in
971  // ArmFault class.
972  return std::make_shared<UndefinedInstruction>(
973  machInst, 0,
975  }
976 }
977 
978 Fault
980  ExceptionLevel pstateEL) const
981 {
982  switch (pstateEL) {
983  case EL0:
984  case EL1:
985  return std::make_shared<SupervisorTrap>(machInst, 0, EC_UNKNOWN);
986  case EL2:
987  return std::make_shared<HypervisorTrap>(machInst, 0, EC_UNKNOWN);
988  case EL3:
989  return std::make_shared<SecureMonitorTrap>(machInst, 0, EC_UNKNOWN);
990  default:
991  panic("Unrecognized Exception Level: %d\n", pstateEL);
992  break;
993  }
994 
995  return NoFault;
996 }
997 
998 Fault
1000 {
1001  switch (el) {
1002  case EL1:
1003  return std::make_shared<SupervisorTrap>(machInst, 0, EC_TRAPPED_SVE);
1004  case EL2:
1005  return std::make_shared<HypervisorTrap>(machInst, 0, EC_TRAPPED_SVE);
1006  case EL3:
1007  return std::make_shared<SecureMonitorTrap>(machInst, 0,
1008  EC_TRAPPED_SVE);
1009 
1010  default:
1011  panic("Illegal EL in sveAccessTrap\n");
1012  }
1013 }
1014 
1015 Fault
1016 ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
1017 {
1018  const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
1019  // Check if access disabled in CPACR_EL1
1020  if (el <= EL1 && !ELIsInHost(tc, el)) {
1021  if ((el == EL0 && cpacr.zen == 0x1) ||
1022  (!(cpacr.zen & 0x1)))
1023  return sveAccessTrap(EL1);
1024 
1025  if ((el == EL0 && cpacr.fpen == 0x1) ||
1026  (!(cpacr.fpen & 0x1)))
1027  return advSIMDFPAccessTrap64(EL1);
1028  }
1029 
1030  // Check if access disabled in CPTR_EL2
1031  if (el <= EL2 && EL2Enabled(tc)) {
1032  CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL2);
1033  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1034  if (HaveVirtHostExt(tc) && hcr.e2h) {
1035  if (((cptr_en_check.zen & 0x1) == 0x0) ||
1036  (cptr_en_check.zen == 0x1 && el == EL0 &&
1037  hcr.tge == 0x1)) {
1038  return sveAccessTrap(EL2);
1039  }
1040  if (((cptr_en_check.fpen & 0x1) == 0x0) ||
1041  (cptr_en_check.fpen == 0x1 && el == EL0 &&
1042  hcr.tge == 0x1)) {
1043  return advSIMDFPAccessTrap64(EL2);
1044  }
1045  } else {
1046  if (cptr_en_check.tz == 1)
1047  return sveAccessTrap(EL2);
1048  if (cptr_en_check.tfp == 1)
1049  return advSIMDFPAccessTrap64(EL2);
1050  }
1051  }
1052 
1053  // Check if access disabled in CPTR_EL3
1054  if (ArmSystem::haveSecurity(tc)) {
1055  CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
1056  if (!cptr_en_check.ez)
1057  return sveAccessTrap(EL3);
1058  if (cptr_en_check.tfp)
1059  return advSIMDFPAccessTrap64(EL3);
1060  }
1061 
1062  return NoFault;
1063 }
1064 
1065 static uint8_t
1067 {
1068  // See: shared/functions/system/RestoredITBits in the ARM ARM
1069 
1070  const ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t)spsr.mode);
1071  const uint8_t it = itState(spsr);
1072 
1073  if (!spsr.t || spsr.il)
1074  return 0;
1075 
1076  // The IT bits are forced to zero when they are set to a reserved
1077  // value.
1078  if (bits(it, 7, 4) != 0 && bits(it, 3, 0) == 0)
1079  return 0;
1080 
1081  const bool itd = el == EL2 ?
1082  ((SCTLR)tc->readMiscReg(MISCREG_HSCTLR)).itd :
1083  ((SCTLR)tc->readMiscReg(MISCREG_SCTLR)).itd;
1084 
1085  // The IT bits are forced to zero when returning to A32 state, or
1086  // when returning to an EL with the ITD bit set to 1, and the IT
1087  // bits are describing a multi-instruction block.
1088  if (itd && bits(it, 2, 0) != 0)
1089  return 0;
1090 
1091  return it;
1092 }
1093 
1094 static bool
1095 illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
1096 {
1097  const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
1098  if (unknownMode(mode))
1099  return true;
1100 
1101  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
1102  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
1103 
1104  //ELFromSPSR
1105  bool valid;
1106  ExceptionLevel target_el = opModeToEL(mode);
1107  if (!spsr.width) {
1108  if (!ArmSystem::highestELIs64(tc)) {
1109  valid = false;
1110  } else if (!ArmSystem::haveEL(tc, target_el)) {
1111  valid = false;
1112  } else if (spsr & 0x2) {
1113  valid = false;
1114  } else if (target_el == EL0 && spsr.sp) {
1115  valid = false;
1116  } else if (target_el == EL2 && ArmSystem::haveEL(tc, EL3) &&
1117  !scr.ns && !IsSecureEL2Enabled(tc)) {
1118  valid = false;
1119  } else {
1120  valid = true;
1121  }
1122  } else {
1123  valid = !unknownMode32(mode);
1124  }
1125  if (!valid)
1126  return true;
1127 
1128  if (target_el > currEL(tc))
1129  return true;
1130 
1131  bool spsr_mode_is_aarch32 = (spsr.width == 1);
1132  bool known, target_el_is_aarch32;
1133  std::tie(known, target_el_is_aarch32) = ELUsingAArch32K(tc, target_el);
1134  assert(known || (target_el == EL0 && ELIs64(tc, EL1)));
1135 
1136  if (known && (spsr_mode_is_aarch32 != target_el_is_aarch32))
1137  return true;
1138 
1139  if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && hcr.tge &&
1140  (IsSecureEL2Enabled(tc) || !isSecureBelowEL3(tc))) {
1141  return true;
1142  }
1143 
1144  return false;
1145 }
1146 
1147 CPSR
1148 ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
1149 {
1150  CPSR new_cpsr = 0;
1151  ExceptionLevel dest;
1152 
1153  if (illegalExceptionReturn(tc, cpsr, spsr)) {
1154  // If the SPSR specifies an illegal exception return,
1155  // then PSTATE.{M, nRW, EL, SP} are unchanged and PSTATE.IL
1156  // is set to 1.
1157  new_cpsr.il = 1;
1158  if (cpsr.width) {
1159  new_cpsr.mode = cpsr.mode;
1160  } else {
1161  new_cpsr.width = cpsr.width;
1162  new_cpsr.el = cpsr.el;
1163  new_cpsr.sp = cpsr.sp;
1164  }
1165  dest = currEL(tc);
1166  } else {
1167  new_cpsr.il = spsr.il;
1168  if (spsr.width && unknownMode32((OperatingMode)(uint8_t)spsr.mode)) {
1169  new_cpsr.il = 1;
1170  } else if (spsr.width) {
1171  new_cpsr.mode = spsr.mode;
1172  } else {
1173  new_cpsr.el = spsr.el;
1174  new_cpsr.sp = spsr.sp;
1175  }
1176  dest = (ExceptionLevel)(uint8_t) spsr.el;
1177  }
1178 
1179  new_cpsr.nz = spsr.nz;
1180  new_cpsr.c = spsr.c;
1181  new_cpsr.v = spsr.v;
1182  new_cpsr.pan = spsr.pan;
1183  if (new_cpsr.width) {
1184  // aarch32
1185  const ITSTATE it = getRestoredITBits(tc, spsr);
1186  new_cpsr.q = spsr.q;
1187  new_cpsr.ge = spsr.ge;
1188  new_cpsr.e = spsr.e;
1189  new_cpsr.aif = spsr.aif;
1190  new_cpsr.t = spsr.t;
1191  new_cpsr.it2 = it.top6;
1192  new_cpsr.it1 = it.bottom2;
1193  } else {
1194  // aarch64
1195  new_cpsr.daif = spsr.daif;
1196  }
1197 
1199  SoftwareStep *ss = sd->getSstep();
1200  new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest);
1201 
1202  return new_cpsr;
1203 }
1204 
1205 bool
1207  ExceptionLevel pstateEL) const
1208 {
1209  // Returns TRUE if exceptions normally routed to EL1 are being handled
1210  // at an Exception level using AArch64, because either EL1 is using
1211  // AArch64 or TGE is in force and EL2 is using AArch64.
1212  HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
1213  return (pstateEL == EL0 && !ELIs32(tc, EL1)) ||
1214  (ArmSystem::haveEL(tc, EL2) && !isSecure(tc) &&
1215  !ELIs32(tc, EL2) && hcr.tge);
1216 }
1217 
1218 unsigned
1220 {
1221  auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
1222  return isa->getCurSveVecLenInBits();
1223 }
1224 
1225 } // namespace ArmISA
1226 } // namespace gem5
gem5::ArmISA::FramePointerReg
const int FramePointerReg
Definition: int.hh:544
gem5::ArmISA::MISCREG_CPTR_EL2
@ MISCREG_CPTR_EL2
Definition: misc.hh:588
gem5::ArmISA::ArmStaticInst::printShiftOperand
void printShiftOperand(std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) const
Definition: static_inst.cc:498
gem5::ArmISA::COND_HI
@ COND_HI
Definition: cc.hh:77
gem5::ArmISA::ArmStaticInst::printVecReg
void printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) const
Definition: static_inst.cc:351
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::NoFault
constexpr decltype(nullptr) NoFault
Definition: types.hh:260
gem5::ArmISA::len
Bitfield< 18, 16 > len
Definition: misc_types.hh:444
gem5::ArmISA::ELIs64
bool ELIs64(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:282
gem5::ArmISA::ArmStaticInst::advSIMDFPAccessTrap64
Fault advSIMDFPAccessTrap64(ExceptionLevel el) const
Trap an access to Advanced SIMD or FP registers due to access control bits.
Definition: static_inst.cc:655
gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR
CPSR getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
Get the new PSTATE from a SPSR register in preparation for an exception return.
Definition: static_inst.cc:1148
gem5::ArmISA::sed
Bitfield< 8 > sed
Definition: misc_types.hh:379
gem5::ArmISA::ISA::getCurSveVecLenInBits
unsigned getCurSveVecLenInBits() const
Definition: isa.cc:2358
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:205
gem5::ArmISA::SelfDebug
Definition: self_debug.hh:277
gem5::ArmISA::advsimd
Bitfield< 23, 20 > advsimd
Definition: misc_types.hh:175
gem5::ArmISA::ArmFault::BRKPOINT
@ BRKPOINT
Definition: faults.hh:160
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:72
gem5::ArmISA::ArmStaticInst::undefinedFault32
Fault undefinedFault32(ThreadContext *tc, ExceptionLevel el) const
UNDEFINED behaviour in AArch32.
Definition: static_inst.cc:960
gem5::ArmISA::COND_NE
@ COND_NE
Definition: cc.hh:70
gem5::ArmISA::MISCREG_MDCR_EL2
@ MISCREG_MDCR_EL2
Definition: misc.hh:587
gem5::ArmISA::UXTH
@ UXTH
Definition: types.hh:218
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:593
gem5::ArmISA::ArmStaticInst::shift_carry_imm
bool shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:220
gem5::ArmISA::isSecureBelowEL3
bool isSecureBelowEL3(ThreadContext *tc)
Definition: utility.cc:84
gem5::ArmISA::SXTX
@ SXTX
Definition: types.hh:224
gem5::ArmISA::ArmStaticInst::printMnemonic
void printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) const
Definition: static_inst.cc:377
gem5::ArmISA::MISCREG_HSCTLR
@ MISCREG_HSCTLR
Definition: misc.hh:246
gem5::ArmISA::currEL
static ExceptionLevel currEL(const ThreadContext *tc)
Definition: utility.hh:119
gem5::ArmISA::illegalExceptionReturn
static bool illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
Definition: static_inst.cc:1095
gem5::ArmISA::ccRegName
const char *const ccRegName[NUM_CCREGS]
Definition: cc.hh:58
gem5::loader::SymbolTable::end
const_iterator end() const
Definition: symtab.hh:176
gem5::ArmISA::ArmExtendType
ArmExtendType
Definition: types.hh:215
gem5::ArmISA::miscRegName
const char *const miscRegName[]
Definition: misc.hh:1172
gem5::ArmISA::ReturnAddressReg
const int ReturnAddressReg
Definition: int.hh:546
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:267
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::ArmFault::DebugEvent
@ DebugEvent
Definition: faults.hh:105
gem5::ArmISA::opModeToEL
static ExceptionLevel opModeToEL(OperatingMode mode)
Definition: types.hh:383
gem5::ArmISA::ELIsInHost
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el)
Returns true if the current exception level el is executing a Host OS or an application of a Host OS ...
Definition: utility.cc:297
gem5::ArmISA::ArmStaticInst::disabledFault
Fault disabledFault() const
Definition: static_inst.hh:391
gem5::ArmISA::ArmStaticInst::getCurSveVecLenInBits
static unsigned getCurSveVecLenInBits(ThreadContext *tc)
Definition: static_inst.cc:1219
gem5::ArmISA::ArmStaticInst::printCCReg
void printCCReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:364
gem5::ArmISA::COND_PL
@ COND_PL
Definition: cc.hh:74
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::ArmISA::MISCREG_SCTLR
@ MISCREG_SCTLR
Definition: misc.hh:235
gem5::ArmISA::ArmStaticInst::trapWFx
Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const
WFE/WFI trapping helper function.
Definition: static_inst.cc:902
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISA::ArmStaticInst::shift_rm_rs
int32_t shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:180
gem5::ArmISA::ArmStaticInst::softwareBreakpoint32
Fault softwareBreakpoint32(ExecContext *xc, uint16_t imm) const
Trigger a Software Breakpoint.
Definition: static_inst.cc:635
gem5::ArmISA::ELUsingAArch32K
std::pair< bool, bool > ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
This function checks whether selected EL provided as an argument is using the AArch32 ISA.
Definition: utility.cc:307
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::ArmISA::ArmStaticInst::printTarget
void printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) const
Definition: static_inst.cc:398
gem5::ArmISA::EC_TRAPPED_HCPTR
@ EC_TRAPPED_HCPTR
Definition: types.hh:302
gem5::ArmISA::MISCREG_HCPTR
@ MISCREG_HCPTR
Definition: misc.hh:251
gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32
Fault checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) const
Check if a VFP/SIMD access from aarch32 should be allowed.
Definition: static_inst.cc:726
gem5::ArmISA::ArmStaticInst::printCondition
void printCondition(std::ostream &os, unsigned code, bool noImplicit=false) const
Definition: static_inst.cc:417
gem5::ArmISA::ArmStaticInst::readPC
static Addr readPC(ExecContext *xc)
Definition: static_inst.hh:324
gem5::ArmISA::unknownMode32
static bool unknownMode32(OperatingMode mode)
Definition: types.hh:438
gem5::SparcISA::INTREG_UREG0
@ INTREG_UREG0
Definition: int.hh:57
gem5::ArmISA::ArmStaticInst::printExtendOperand
void printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) const
Definition: static_inst.cc:562
gem5::ArmISA::COND_CS
@ COND_CS
Definition: cc.hh:71
gem5::ArmISA::COND_LT
@ COND_LT
Definition: cc.hh:80
gem5::ArmISA::getRestoredITBits
static uint8_t getRestoredITBits(ThreadContext *tc, CPSR spsr)
Definition: static_inst.cc:1066
gem5::ArmISA::ArmStaticInst::checkSETENDEnabled
Fault checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
Check if SETEND instruction execution in aarch32 should be trapped.
Definition: static_inst.cc:928
gem5::ThreadContext::getIsaPtr
virtual BaseISA * getIsaPtr()=0
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::ArmISA::EC_UNKNOWN
@ EC_UNKNOWN
Definition: types.hh:296
gem5::ArmISA::MISCREG_SCTLR_EL1
@ MISCREG_SCTLR_EL1
Definition: misc.hh:579
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::ArmStaticInst::undefinedFault64
Fault undefinedFault64(ThreadContext *tc, ExceptionLevel el) const
UNDEFINED behaviour in AArch64.
Definition: static_inst.cc:979
gem5::ArmISA::HaveVirtHostExt
bool HaveVirtHostExt(ThreadContext *tc)
Definition: utility.cc:224
gem5::ArmISA::MISCREG_CPTR_EL3
@ MISCREG_CPTR_EL3
Definition: misc.hh:595
gem5::ArmISA::ArmStaticInst::printMemSymbol
void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) const
Definition: static_inst.cc:480
gem5::ArmISA::ArmStaticInst::shiftReg64
int64_t shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const
Definition: static_inst.cc:95
gem5::ArmISA::width
Bitfield< 4 > width
Definition: misc_types.hh:71
gem5::ArmISA::SXTW
@ SXTW
Definition: types.hh:223
gem5::ArmISA::rd
Bitfield< 15, 12 > rd
Definition: types.hh:114
gem5::ArmISA::EC_TRAPPED_WFI_WFE
@ EC_TRAPPED_WFI_WFE
Definition: types.hh:297
gem5::ArmISA::COND_VC
@ COND_VC
Definition: cc.hh:76
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:268
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
gem5::ArmISA::rm
Bitfield< 3, 0 > rm
Definition: types.hh:118
gem5::ArmISA::unknownMode
static bool unknownMode(OperatingMode mode)
Definition: types.hh:412
gem5::ArmISA::ArmStaticInst::checkForWFxTrap64
Fault checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
Check if WFE/WFI instruction execution in aarch64 should be trapped.
Definition: static_inst.cc:870
gem5::ArmISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:1096
isa.hh
gem5::ArmISA::ELIs32
bool ELIs32(ThreadContext *tc, ExceptionLevel el)
Definition: utility.cc:288
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::ArmISA::s
Bitfield< 4 > s
Definition: misc_types.hh:561
gem5::ArmISA::SoftwareStep
Definition: self_debug.hh:195
gem5::ArmISA::ArmStaticInst::isWFxTrapping
bool isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) const
Definition: static_inst.cc:803
gem5::ArmISA::SXTH
@ SXTH
Definition: types.hh:222
gem5::ExecContext::tcBase
virtual ThreadContext * tcBase() const =0
Returns a pointer to the ThreadContext.
gem5::loader::SymbolTable::findNearest
const_iterator findNearest(Addr addr, Addr &next_addr) const
Find the nearest symbol equal to or less than the supplied address (e.g., the label for the enclosing...
Definition: symtab.hh:361
gem5::ArmISA::itd
Bitfield< 7 > itd
Definition: misc_types.hh:382
gem5::ArmISA::EL2Enabled
bool EL2Enabled(ThreadContext *tc)
Definition: utility.cc:274
gem5::ArmISA::SXTB
@ SXTB
Definition: types.hh:221
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
cprintf.hh
gem5::ArmISA::ArmStaticInst::intWidth
uint8_t intWidth
Definition: static_inst.hh:67
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::ArmStaticInst::shift_carry_rs
bool shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:260
gem5::ArmISA::COND_EQ
@ COND_EQ
Definition: cc.hh:69
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:269
gem5::ArmISA::ArmStaticInst::checkForWFxTrap32
Fault checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) const
Check if WFE/WFI instruction execution in aarch32 should be trapped.
Definition: static_inst.cc:830
gem5::ArmISA::ArmStaticInst::printVecPredReg
void printVecPredReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:358
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::ArmISA::COND_VS
@ COND_VS
Definition: cc.hh:75
faults.hh
gem5::ArmISA::COND_AL
@ COND_AL
Definition: cc.hh:83
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::ArmStaticInst::checkSveEnabled
Fault checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.
Definition: static_inst.cc:1016
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:72
gem5::X86ISA::exit
Bitfield< 3 > exit
Definition: misc.hh:854
gem5::ArmISA::COND_MI
@ COND_MI
Definition: cc.hh:73
utility.hh
gem5::ArmISA::COND_LS
@ COND_LS
Definition: cc.hh:78
gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64
bool generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) const
Return true if exceptions normally routed to EL1 are being handled at an Exception level using AArch6...
Definition: static_inst.cc:1206
gem5::ArmISA::UXTB
@ UXTB
Definition: types.hh:217
gem5::ArmISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:545
gem5::ArmISA::ArmStaticInst::extendReg64
int64_t extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const
Definition: static_inst.cc:134
gem5::ArmISA::UXTW
@ UXTW
Definition: types.hh:219
gem5::ArmISA::IsSecureEL2Enabled
bool IsSecureEL2Enabled(ThreadContext *tc)
Definition: utility.cc:260
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:266
gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64
Fault checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
Check an Advaned SIMD access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.
Definition: static_inst.cc:714
gem5::ArmISA::COND_LE
@ COND_LE
Definition: cc.hh:82
gem5::ArmISA::imm
Bitfield< 7, 0 > imm
Definition: types.hh:132
gem5::ArmISA::ArmStaticInst::printDataInst
void printDataInst(std::ostream &os, bool withImm) const
condcodes.hh
gem5::ArmISA::ArmStaticInst::printFloatReg
void printFloatReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:345
gem5::ArmISA::UXTX
@ UXTX
Definition: types.hh:220
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::ArmISA::ss
Bitfield< 21 > ss
Definition: misc_types.hh:59
gem5::ArmISA::ArmStaticInst::shift_rm_imm
int32_t shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const
Definition: static_inst.cc:60
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
static_inst.hh
gem5::ArmISA::ISA::getSelfDebug
SelfDebug * getSelfDebug() const
Definition: isa.hh:524
gem5::ArmSystem::haveSecurity
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:162
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
reg_class.hh
gem5::ArmISA::ArmStaticInst::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: static_inst.cc:626
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::ArmStaticInst::printMiscReg
void printMiscReg(std::ostream &os, RegIndex reg_idx) const
Definition: static_inst.cc:370
gem5::ArmISA::COND_GE
@ COND_GE
Definition: cc.hh:79
gem5::ArmISA::EC_TRAPPED_SIMD_FP
@ EC_TRAPPED_SIMD_FP
Definition: types.hh:303
gem5::ArmISA::sd
Bitfield< 4 > sd
Definition: misc_types.hh:774
gem5::ArmISA::snsBankedIndex
int snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
Definition: misc.cc:1313
symtab.hh
gem5::ArmISA::ArmStaticInst::aarch64
bool aarch64
Definition: static_inst.hh:66
self_debug.hh
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::ArmSystem::haveEL
static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:138
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:586
gem5::ArmISA::itState
static uint8_t itState(CPSR psr)
Definition: utility.hh:197
gem5::ArmISA::ArmStaticInst::printIntReg
void printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) const
Print a register name for disassembly given the unique dependence tag number (FP or int).
Definition: static_inst.cc:299
gem5::StaticInst::mnemonic
const char * mnemonic
Base mnemonic (e.g., "add").
Definition: static_inst.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::COND_GT
@ COND_GT
Definition: cc.hh:81
gem5::ArmISA::EC_TRAPPED_SVE
@ EC_TRAPPED_SVE
Definition: types.hh:318
gem5::ArmISA::rn
Bitfield< 19, 16 > rn
Definition: types.hh:113
gem5::ArmISA::PCReg
const int PCReg
Definition: int.hh:547
gem5::ArmISA::ArmFault::UnknownTran
@ UnknownTran
Definition: faults.hh:154
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:272
gem5::ArmISA::rs
Bitfield< 9, 8 > rs
Definition: misc_types.hh:376
gem5::ArmSystem::haveVirtualization
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:171
gem5::ArmISA::ArmStaticInst::sveAccessTrap
Fault sveAccessTrap(ExceptionLevel el) const
Trap an access to SVE registers due to access control bits.
Definition: static_inst.cc:999
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:264
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::COND_CC
@ COND_CC
Definition: cc.hh:72
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::ArmISA::ArmStaticInst::printPFflags
void printPFflags(std::ostream &os, int flag) const
Definition: static_inst.cc:334
gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64
Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
Check an Advaned SIMD access against CPTR_EL2 and CPTR_EL3.
Definition: static_inst.cc:675

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