gem5
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arch
x86
pseudo_inst_abi.hh
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/*
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* Copyright (c) 2020 The Regents of the University of California.
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
arch/x86/regs/int.hh
"
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#include "
sim/guest_abi.hh
"
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#include "
sim/pseudo_inst.hh
"
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namespace
gem5
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{
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struct
X86PseudoInstABI
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{
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using
State
= int;
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};
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namespace
guest_abi
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{
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template
<
typename
T>
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struct
Result
<
X86PseudoInstABI
, T>
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{
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static
void
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store
(
ThreadContext
*tc,
const
T &ret)
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{
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// This assumes that all pseudo ops have their return value set
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// by the pseudo op instruction. This may need to be revisited if we
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// modify the pseudo op ABI in util/m5/m5op_x86.S
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tc->
setReg
(
X86ISA::int_reg::Rax
, ret);
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}
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};
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template
<>
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struct
Argument
<
X86PseudoInstABI
, uint64_t>
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{
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static
uint64_t
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get
(
ThreadContext
*tc,
X86PseudoInstABI::State
&
state
)
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{
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// The first 6 integer arguments are passed in registers, the rest
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// are passed on the stack.
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panic_if
(
state
>= 6,
"Too many psuedo inst arguments."
);
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using namespace
X86ISA;
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constexpr
RegId
int_reg_map[] = {
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int_reg::Rdi
,
int_reg::Rsi
,
int_reg::Rdx
,
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int_reg::Rcx
,
int_reg::R8
,
int_reg::R9
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};
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return
tc->
getReg
(int_reg_map[
state
++]);
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}
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};
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template
<>
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struct
Argument
<
X86PseudoInstABI
, pseudo_inst::GuestAddr>
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{
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using
Arg
=
pseudo_inst::GuestAddr
;
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static
Arg
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get
(
ThreadContext
*tc,
X86PseudoInstABI::State
&
state
)
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{
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// The first 6 integer arguments are passed in registers, the rest
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// are passed on the stack.
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panic_if
(
state
>= 6,
"Too many psuedo inst arguments."
);
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using namespace
X86ISA;
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constexpr
RegId
int_reg_map[] = {
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int_reg::Rdi
,
int_reg::Rsi
,
int_reg::Rdx
,
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int_reg::Rcx
,
int_reg::R8
,
int_reg::R9
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};
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return
(
Arg
)tc->
getReg
(int_reg_map[
state
++]);
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}
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};
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}
// namespace guest_abi
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}
// namespace gem5
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition
reg_class.hh:94
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId ®) const
Definition
thread_context.cc:180
gem5::ThreadContext::setReg
virtual void setReg(const RegId ®, RegVal val)
Definition
thread_context.cc:188
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition
logging.hh:214
guest_abi.hh
state
atomic_var_t state
Definition
helpers.cc:211
gem5::ArmISA::int_reg::R9
constexpr RegId R9
Definition
int.hh:195
gem5::ArmISA::int_reg::R8
constexpr RegId R8
Definition
int.hh:194
gem5::X86ISA::int_reg::Rsi
constexpr RegId Rsi
Definition
int.hh:138
gem5::X86ISA::int_reg::Rax
constexpr RegId Rax
Definition
int.hh:132
gem5::X86ISA::int_reg::Rdx
constexpr RegId Rdx
Definition
int.hh:134
gem5::X86ISA::int_reg::Rdi
constexpr RegId Rdi
Definition
int.hh:139
gem5::X86ISA::int_reg::Rcx
constexpr RegId Rcx
Definition
int.hh:133
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
pseudo_inst.hh
gem5::X86PseudoInstABI
Definition
pseudo_inst_abi.hh:46
gem5::X86PseudoInstABI::State
int State
Definition
pseudo_inst_abi.hh:47
gem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >::get
static Arg get(ThreadContext *tc, X86PseudoInstABI::State &state)
Definition
pseudo_inst_abi.hh:94
gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get
static uint64_t get(ThreadContext *tc, X86PseudoInstABI::State &state)
Definition
pseudo_inst_abi.hh:70
gem5::guest_abi::Argument
Definition
definition.hh:99
gem5::guest_abi::Result< X86PseudoInstABI, T >::store
static void store(ThreadContext *tc, const T &ret)
Definition
pseudo_inst_abi.hh:57
gem5::guest_abi::Result
Definition
definition.hh:64
gem5::pseudo_inst::GuestAddr
This struct wrapper for Addr enables m5ops for systems with 32 bit pointer, since it allows to distin...
Definition
pseudo_inst.hh:74
int.hh
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