gem5 v24.0.0.0
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pseudo_inst_abi.hh
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1/*
2 * Copyright (c) 2020 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
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9 * licensed hereunder. You may use the software subject to the license
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36 */
37
38#include "arch/x86/regs/int.hh"
39#include "sim/guest_abi.hh"
40#include "sim/pseudo_inst.hh"
41
42namespace gem5
43{
44
46{
47 using State = int;
48};
49
50namespace guest_abi
51{
52
53template <typename T>
55{
56 static void
57 store(ThreadContext *tc, const T &ret)
58 {
59 // This assumes that all pseudo ops have their return value set
60 // by the pseudo op instruction. This may need to be revisited if we
61 // modify the pseudo op ABI in util/m5/m5op_x86.S
63 }
64};
65
66template <>
67struct Argument<X86PseudoInstABI, uint64_t>
68{
69 static uint64_t
71 {
72 // The first 6 integer arguments are passed in registers, the rest
73 // are passed on the stack.
74
75 panic_if(state >= 6, "Too many psuedo inst arguments.");
76
77 using namespace X86ISA;
78
79 constexpr RegId int_reg_map[] = {
82 };
83
84 return tc->getReg(int_reg_map[state++]);
85 }
86};
87
88template <>
89struct Argument<X86PseudoInstABI, pseudo_inst::GuestAddr>
90{
92
93 static Arg
95 {
96 // The first 6 integer arguments are passed in registers, the rest
97 // are passed on the stack.
98
99 panic_if(state >= 6, "Too many psuedo inst arguments.");
100
101 using namespace X86ISA;
102
103 constexpr RegId int_reg_map[] = {
106 };
107
108 return (Arg)tc->getReg(int_reg_map[state++]);
109 }
110};
111
112} // namespace guest_abi
113} // namespace gem5
Register ID: describe an architectural register with its class and index.
Definition reg_class.hh:94
ThreadContext is the external interface to all thread state for anything outside of the CPU.
virtual RegVal getReg(const RegId &reg) const
virtual void setReg(const RegId &reg, RegVal val)
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition logging.hh:214
atomic_var_t state
Definition helpers.cc:211
constexpr RegId R9
Definition int.hh:195
constexpr RegId R8
Definition int.hh:194
constexpr RegId Rsi
Definition int.hh:138
constexpr RegId Rax
Definition int.hh:132
constexpr RegId Rdx
Definition int.hh:134
constexpr RegId Rdi
Definition int.hh:139
constexpr RegId Rcx
Definition int.hh:133
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
static Arg get(ThreadContext *tc, X86PseudoInstABI::State &state)
static uint64_t get(ThreadContext *tc, X86PseudoInstABI::State &state)
static void store(ThreadContext *tc, const T &ret)
This struct wrapper for Addr enables m5ops for systems with 32 bit pointer, since it allows to distin...

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