gem5 v24.0.0.0
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Variables | |
constexpr RegId | Rax = intRegClass[_RaxIdx] |
constexpr RegId | Rcx = intRegClass[_RcxIdx] |
constexpr RegId | Rdx = intRegClass[_RdxIdx] |
constexpr RegId | Rbx = intRegClass[_RbxIdx] |
constexpr RegId | Rsp = intRegClass[_RspIdx] |
constexpr RegId | Rbp = intRegClass[_RbpIdx] |
constexpr RegId | Rsi = intRegClass[_RsiIdx] |
constexpr RegId | Rdi = intRegClass[_RdiIdx] |
constexpr RegId | R8 = intRegClass[_R8Idx] |
constexpr RegId | R9 = intRegClass[_R9Idx] |
constexpr RegId | R10 = intRegClass[_R10Idx] |
constexpr RegId | R11 = intRegClass[_R11Idx] |
constexpr RegId | R12 = intRegClass[_R12Idx] |
constexpr RegId | R13 = intRegClass[_R13Idx] |
constexpr RegId | R14 = intRegClass[_R14Idx] |
constexpr RegId | R15 = intRegClass[_R15Idx] |
constexpr RegId | T0 = intRegClass[_T0Idx] |
constexpr RegId | Prodlow = intRegClass[_ProdlowIdx] |
constexpr RegId | Prodhi = intRegClass[_ProdhiIdx] |
constexpr RegId | Quotient = intRegClass[_QuotientIdx] |
constexpr RegId | Remainder = intRegClass[_RemainderIdx] |
constexpr RegId | Divisor = intRegClass[_DivisorIdx] |
constexpr RegId | Doublebits = intRegClass[_DoublebitsIdx] |
constexpr auto & | Eax = Rax |
constexpr auto & | Ax = Rax |
constexpr auto & | Al = Rax |
constexpr auto & | Ecx = Rcx |
constexpr auto & | Cx = Rcx |
constexpr auto & | Cl = Rcx |
constexpr auto & | Edx = Rdx |
constexpr auto & | Dx = Rdx |
constexpr auto & | Dl = Rdx |
constexpr auto & | Ebx = Rbx |
constexpr auto & | Bx = Rbx |
constexpr auto & | Bl = Rbx |
constexpr auto & | Esp = Rsp |
constexpr auto & | Sp = Rsp |
constexpr auto & | Spl = Rsp |
constexpr auto & | Ah = Rsp |
constexpr auto & | Ebp = Rbp |
constexpr auto & | Bp = Rbp |
constexpr auto & | Bpl = Rbp |
constexpr auto & | Ch = Rbp |
constexpr auto & | Esi = Rsi |
constexpr auto & | Si = Rsi |
constexpr auto & | Sil = Rsi |
constexpr auto & | Dh = Rsi |
constexpr auto & | Edi = Rdi |
constexpr auto & | Di = Rdi |
constexpr auto & | Dil = Rdi |
constexpr auto & | Bh = Rdi |
constexpr auto & | R8d = R8 |
constexpr auto & | R8w = R8 |
constexpr auto & | R8b = R8 |
constexpr auto & | R9d = R9 |
constexpr auto & | R9w = R9 |
constexpr auto & | R9b = R9 |
constexpr auto & | R10d = R10 |
constexpr auto & | R10w = R10 |
constexpr auto & | R10b = R10 |
constexpr auto & | R11d = R11 |
constexpr auto & | R11w = R11 |
constexpr auto & | R11b = R11 |
constexpr auto & | R12d = R12 |
constexpr auto & | R12w = R12 |
constexpr auto & | R12b = R12 |
constexpr auto & | R13d = R13 |
constexpr auto & | R13w = R13 |
constexpr auto & | R13b = R13 |
constexpr auto & | R14d = R14 |
constexpr auto & | R14w = R14 |
constexpr auto & | R14b = R14 |
constexpr auto & | R15d = R15 |
constexpr auto & | R15w = R15 |
constexpr auto & | R15b = R15 |
RegId gem5::X86ISA::int_reg::Divisor = intRegClass[_DivisorIdx] |
RegId gem5::X86ISA::int_reg::Doublebits = intRegClass[_DoublebitsIdx] |
RegId gem5::X86ISA::int_reg::Prodhi = intRegClass[_ProdhiIdx] |
RegId gem5::X86ISA::int_reg::Prodlow = intRegClass[_ProdlowIdx] |
RegId gem5::X86ISA::int_reg::Quotient = intRegClass[_QuotientIdx] |
RegId gem5::X86ISA::int_reg::R10 = intRegClass[_R10Idx] |
Definition at line 142 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::R11 = intRegClass[_R11Idx] |
Definition at line 143 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::R12 = intRegClass[_R12Idx] |
Definition at line 144 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::R13 = intRegClass[_R13Idx] |
Definition at line 145 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::R14 = intRegClass[_R14Idx] |
Definition at line 146 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::R15 = intRegClass[_R15Idx] |
Definition at line 147 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::R8 = intRegClass[_R8Idx] |
Definition at line 140 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::R9 = intRegClass[_R9Idx] |
Definition at line 141 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
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inlineconstexpr |
Definition at line 132 of file int.hh.
Referenced by gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< X86Linux::SyscallABI, ABI > > >::store(), gem5::guest_abi::Result< X86PseudoInstABI, T >::store(), gem5::X86ISA::EmuLinux::syscall(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::Rbp = intRegClass[_RbpIdx] |
Definition at line 137 of file int.hh.
Referenced by gem5::X86ISA::EmulEnv::doModRM(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::Rbx = intRegClass[_RbxIdx] |
Definition at line 135 of file int.hh.
Referenced by gem5::X86ISA::EmulEnv::doModRM(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::Rcx = intRegClass[_RcxIdx] |
Definition at line 133 of file int.hh.
Referenced by gem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >::get(), gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::Rdi = intRegClass[_RdiIdx] |
Definition at line 139 of file int.hh.
Referenced by gem5::X86ISA::EmulEnv::doModRM(), gem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >::get(), gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::Rdx = intRegClass[_RdxIdx] |
Definition at line 134 of file int.hh.
Referenced by gem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >::get(), gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get(), gem5::X86ISA::InitInterrupt::invoke(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::Remainder = intRegClass[_RemainderIdx] |
RegId gem5::X86ISA::int_reg::Rsi = intRegClass[_RsiIdx] |
Definition at line 138 of file int.hh.
Referenced by gem5::X86ISA::EmulEnv::doModRM(), gem5::guest_abi::Argument< X86PseudoInstABI, pseudo_inst::GuestAddr >::get(), gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get(), gem5::X86ISA::FsLinux::initState(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::Rsp = intRegClass[_RspIdx] |
Definition at line 136 of file int.hh.
Referenced by gem5::X86Linux::archClone(), gem5::X86ISA::X86Process::argsInit(), gem5::X86ISA::EmulEnv::doModRM(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::trace::X86NativeTrace::ThreadState::update().
RegId gem5::X86ISA::int_reg::T0 = intRegClass[_T0Idx] |
Definition at line 148 of file int.hh.
Referenced by gem5::X86ISA::EmulEnv::doModRM().