gem5  v22.0.0.2
int.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2007 The Hewlett-Packard Development Company
3  * All rights reserved.
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions are
16  * met: redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer;
18  * redistributions in binary form must reproduce the above copyright
19  * notice, this list of conditions and the following disclaimer in the
20  * documentation and/or other materials provided with the distribution;
21  * neither the name of the copyright holders nor the names of its
22  * contributors may be used to endorse or promote products derived from
23  * this software without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #ifndef __ARCH_X86_INTREGS_HH__
39 #define __ARCH_X86_INTREGS_HH__
40 
41 #include "arch/x86/x86_traits.hh"
42 #include "base/bitunion.hh"
43 #include "base/logging.hh"
44 #include "cpu/reg_class.hh"
45 
46 namespace gem5
47 {
48 
49 namespace X86ISA
50 {
51 
52 BitUnion64(X86IntReg)
53  Bitfield<63,0> R;
54  SignedBitfield<63,0> SR;
55  Bitfield<31,0> E;
56  SignedBitfield<31,0> SE;
57  Bitfield<15,0> X;
58  SignedBitfield<15,0> SX;
59  Bitfield<15,8> H;
60  SignedBitfield<15,8> SH;
61  Bitfield<7, 0> L;
62  SignedBitfield<7, 0> SL;
63 EndBitUnion(X86IntReg)
64 
65 namespace int_reg
66 {
67 
68 enum : RegIndex
69 {
70  _RaxIdx,
71  _RcxIdx,
72  _RdxIdx,
73  _RbxIdx,
74  _RspIdx,
75  _RbpIdx,
76  _RsiIdx,
77  _RdiIdx,
78  _R8Idx,
79  _R9Idx,
80  _R10Idx,
81  _R11Idx,
82  _R12Idx,
83  _R13Idx,
84  _R14Idx,
85  _R15Idx,
86 
88  MicroBegin = NumArchRegs,
89  _T0Idx = MicroBegin,
90  MicroEnd = MicroBegin + NumMicroIntRegs,
91 
92  _ProdlowIdx,
93  _ProdhiIdx,
94  _QuotientIdx,
95  _RemainderIdx,
96  _DivisorIdx,
97  _DoublebitsIdx,
98 
99  NumRegs
100 };
101 
102 inline constexpr RegId
103  Rax(IntRegClass, _RaxIdx),
104  Rcx(IntRegClass, _RcxIdx),
105  Rdx(IntRegClass, _RdxIdx),
106  Rbx(IntRegClass, _RbxIdx),
107  Rsp(IntRegClass, _RspIdx),
108  Rbp(IntRegClass, _RbpIdx),
109  Rsi(IntRegClass, _RsiIdx),
110  Rdi(IntRegClass, _RdiIdx),
119  T0(IntRegClass, _T0Idx),
120  Prodlow(IntRegClass, _ProdlowIdx),
121  Prodhi(IntRegClass, _ProdhiIdx),
122  Quotient(IntRegClass, _QuotientIdx),
123  Remainder(IntRegClass, _RemainderIdx),
124  Divisor(IntRegClass, _DivisorIdx),
125  Doublebits(IntRegClass, _DoublebitsIdx);
126 
127 // Aliases for other register sizes.
128 inline constexpr auto
129  &Eax = Rax, &Ax = Rax, &Al = Rax,
130  &Ecx = Rcx, &Cx = Rcx, &Cl = Rcx,
131  &Edx = Rdx, &Dx = Rdx, &Dl = Rdx,
132  &Ebx = Rbx, &Bx = Rbx, &Bl = Rbx,
133  &Esp = Rsp, &Sp = Rsp, &Spl = Rsp, &Ah = Rsp,
134  &Ebp = Rbp, &Bp = Rbp, &Bpl = Rbp, &Ch = Rbp,
135  &Esi = Rsi, &Si = Rsi, &Sil = Rsi, &Dh = Rsi,
136  &Edi = Rdi, &Di = Rdi, &Dil = Rdi, &Bh = Rdi,
137  &R8d = R8, &R8w = R8, &R8b = R8,
138  &R9d = R9, &R9w = R9, &R9b = R9,
139  &R10d = R10, &R10w = R10, &R10b = R10,
140  &R11d = R11, &R11w = R11, &R11b = R11,
141  &R12d = R12, &R12w = R12, &R12b = R12,
142  &R13d = R13, &R13w = R13, &R13b = R13,
143  &R14d = R14, &R14w = R14, &R14b = R14,
144  &R15d = R15, &R15w = R15, &R15b = R15;
145 
146 } // namespace int_reg
147 
148 // This needs to be large enough to miss all the other bits of an index.
149 inline constexpr RegIndex IntFoldBit = 1 << 6;
150 
151 inline static constexpr RegId
153 {
154  return RegId(IntRegClass, int_reg::MicroBegin + index);
155 }
156 
157 inline static constexpr RegId
159 {
160  if ((index & 0x1C) == 4 && foldBit)
161  index = (index - 4) | foldBit;
162  return RegId(IntRegClass, index);
163 }
164 
165 } // namespace X86ISA
166 } // namespace gem5
167 
168 #endif // __ARCH_X86_INTREGS_HH__
gem5::PowerISA::int_reg::_R10Idx
@ _R10Idx
Definition: int.hh:56
gem5::PowerISA::int_reg::R14
constexpr RegId R14(IntRegClass, _R14Idx)
gem5::PowerISA::int_reg::_R11Idx
@ _R11Idx
Definition: int.hh:57
x86_traits.hh
gem5::PowerISA::int_reg::NumArchRegs
@ NumArchRegs
Definition: int.hh:79
gem5::PowerISA::int_reg::_R8Idx
@ _R8Idx
Definition: int.hh:54
gem5::X86ISA::R
R
Definition: int.hh:53
gem5::X86ISA::L
Bitfield< 7, 0 > L
Definition: int.hh:61
gem5::X86ISA::SL
SignedBitfield< 7, 0 > SL
Definition: int.hh:62
gem5::X86ISA::SE
SignedBitfield< 31, 0 > SE
Definition: int.hh:56
gem5::X86ISA::SR
SignedBitfield< 63, 0 > SR
Definition: int.hh:54
gem5::PowerISA::int_reg::_R9Idx
@ _R9Idx
Definition: int.hh:55
gem5::PowerISA::int_reg::_R12Idx
@ _R12Idx
Definition: int.hh:58
gem5::PowerISA::int_reg::R10
constexpr RegId R10(IntRegClass, _R10Idx)
gem5::PowerISA::int_reg::_R14Idx
@ _R14Idx
Definition: int.hh:60
gem5::PowerISA::int_reg::NumRegs
@ NumRegs
Definition: int.hh:92
gem5::X86ISA::H
Bitfield< 15, 8 > H
Definition: int.hh:59
gem5::X86ISA::SH
SignedBitfield< 15, 8 > SH
Definition: int.hh:60
gem5::PowerISA::int_reg::R8
constexpr RegId R8(IntRegClass, _R8Idx)
bitunion.hh
gem5::PowerISA::int_reg::R11
constexpr RegId R11(IntRegClass, _R11Idx)
gem5::X86ISA::BitUnion64
BitUnion64(VAddr) Bitfield< 20
gem5::PowerISA::int_reg::R9
constexpr RegId R9(IntRegClass, _R9Idx)
gem5::X86ISA::intRegFolded
static constexpr RegId intRegFolded(RegIndex index, RegIndex foldBit)
Definition: int.hh:158
gem5::X86ISA::SX
SignedBitfield< 15, 0 > SX
Definition: int.hh:58
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::PowerISA::int_reg::_R13Idx
@ _R13Idx
Definition: int.hh:59
gem5::PowerISA::int_reg::_R15Idx
@ _R15Idx
Definition: int.hh:61
gem5::PowerISA::int_reg::R15
constexpr RegId R15(IntRegClass, _R15Idx)
gem5::X86ISA::intRegMicro
static constexpr RegId intRegMicro(int index)
Definition: int.hh:152
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
reg_class.hh
gem5::X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:55
logging.hh
gem5::X86ISA::NumMicroIntRegs
const int NumMicroIntRegs
Definition: x86_traits.hh:50
gem5::X86ISA::IntFoldBit
constexpr RegIndex IntFoldBit
Definition: int.hh:149
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
gem5::X86ISA::X
Bitfield< 15, 0 > X
Definition: int.hh:57
gem5::PowerISA::int_reg::R12
constexpr RegId R12(IntRegClass, _R12Idx)
gem5::PowerISA::int_reg::R13
constexpr RegId R13(IntRegClass, _R13Idx)
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126

Generated on Thu Jul 28 2022 13:32:24 for gem5 by doxygen 1.8.17