gem5  v21.1.0.2
int.hh
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37 
38 #ifndef __ARCH_X86_INTREGS_HH__
39 #define __ARCH_X86_INTREGS_HH__
40 
41 #include "arch/x86/x86_traits.hh"
42 #include "base/bitunion.hh"
43 #include "base/logging.hh"
44 
45 namespace gem5
46 {
47 
48 namespace X86ISA
49 {
50  BitUnion64(X86IntReg)
51  Bitfield<63,0> R;
52  SignedBitfield<63,0> SR;
53  Bitfield<31,0> E;
54  SignedBitfield<31,0> SE;
55  Bitfield<15,0> X;
56  SignedBitfield<15,0> SX;
57  Bitfield<15,8> H;
58  SignedBitfield<15,8> SH;
59  Bitfield<7, 0> L;
60  SignedBitfield<7, 0> SL;
61  EndBitUnion(X86IntReg)
62 
63  enum IntRegIndex
64  {
65  INTREG_RAX,
66  INTREG_EAX = INTREG_RAX,
67  INTREG_AX = INTREG_RAX,
68  INTREG_AL = INTREG_RAX,
69 
70  INTREG_RCX,
71  INTREG_ECX = INTREG_RCX,
72  INTREG_CX = INTREG_RCX,
73  INTREG_CL = INTREG_RCX,
74 
75  INTREG_RDX,
76  INTREG_EDX = INTREG_RDX,
77  INTREG_DX = INTREG_RDX,
78  INTREG_DL = INTREG_RDX,
79 
80  INTREG_RBX,
81  INTREG_EBX = INTREG_RBX,
82  INTREG_BX = INTREG_RBX,
83  INTREG_BL = INTREG_RBX,
84 
85  INTREG_RSP,
86  INTREG_ESP = INTREG_RSP,
87  INTREG_SP = INTREG_RSP,
88  INTREG_SPL = INTREG_RSP,
89  INTREG_AH = INTREG_RSP,
90 
91  INTREG_RBP,
92  INTREG_EBP = INTREG_RBP,
93  INTREG_BP = INTREG_RBP,
94  INTREG_BPL = INTREG_RBP,
95  INTREG_CH = INTREG_RBP,
96 
97  INTREG_RSI,
98  INTREG_ESI = INTREG_RSI,
99  INTREG_SI = INTREG_RSI,
100  INTREG_SIL = INTREG_RSI,
101  INTREG_DH = INTREG_RSI,
102 
103  INTREG_RDI,
104  INTREG_EDI = INTREG_RDI,
105  INTREG_DI = INTREG_RDI,
106  INTREG_DIL = INTREG_RDI,
107  INTREG_BH = INTREG_RDI,
108 
109  INTREG_R8,
110  INTREG_R8D = INTREG_R8,
111  INTREG_R8W = INTREG_R8,
112  INTREG_R8B = INTREG_R8,
113 
114  INTREG_R9,
115  INTREG_R9D = INTREG_R9,
116  INTREG_R9W = INTREG_R9,
117  INTREG_R9B = INTREG_R9,
118 
119  INTREG_R10,
120  INTREG_R10D = INTREG_R10,
121  INTREG_R10W = INTREG_R10,
122  INTREG_R10B = INTREG_R10,
123 
124  INTREG_R11,
125  INTREG_R11D = INTREG_R11,
126  INTREG_R11W = INTREG_R11,
127  INTREG_R11B = INTREG_R11,
128 
129  INTREG_R12,
130  INTREG_R12D = INTREG_R12,
131  INTREG_R12W = INTREG_R12,
132  INTREG_R12B = INTREG_R12,
133 
134  INTREG_R13,
135  INTREG_R13D = INTREG_R13,
136  INTREG_R13W = INTREG_R13,
137  INTREG_R13B = INTREG_R13,
138 
139  INTREG_R14,
140  INTREG_R14D = INTREG_R14,
141  INTREG_R14W = INTREG_R14,
142  INTREG_R14B = INTREG_R14,
143 
144  INTREG_R15,
145  INTREG_R15D = INTREG_R15,
146  INTREG_R15W = INTREG_R15,
147  INTREG_R15B = INTREG_R15,
148 
149  NUM_ARCH_INTREGS,
150 
151  INTREG_MICRO_BEGIN = NUM_ARCH_INTREGS,
152  INTREG_T0 = INTREG_MICRO_BEGIN,
153  INTREG_MICRO_END = INTREG_MICRO_BEGIN + NumMicroIntRegs,
154 
155  // The lower part of the result of multiplication.
156  INTREG_PRODLOW,
157  // The upper part of the result of multiplication.
158  INTREG_PRODHI,
159  // The quotient from division.
160  INTREG_QUOTIENT,
161  // The remainder from division.
162  INTREG_REMAINDER,
163  // The divisor for division.
164  INTREG_DIVISOR,
165  // The register to use for shift doubles.
166  INTREG_DOUBLEBITS,
167 
168  NUM_INTREGS,
169  };
170 
171  // This needs to be large enough to miss all the other bits of an index.
172  static const IntRegIndex IntFoldBit = (IntRegIndex)(1 << 6);
173 
174  inline static IntRegIndex
176  {
177  return (IntRegIndex)(INTREG_MICRO_BEGIN + index);
178  }
179 
180  inline static IntRegIndex
181  INTREG_FOLDED(int index, int foldBit)
182  {
183  if ((index & 0x1C) == 4 && foldBit)
184  index = (index - 4) | foldBit;
185  return (IntRegIndex)index;
186  }
187 
188  const int NumIntRegs = NUM_INTREGS;
189 
190 } // namespace X86ISA
191 } // namespace gem5
192 
193 #endif // __ARCH_X86_INTREGS_HH__
x86_traits.hh
gem5::X86ISA::R
R
Definition: int.hh:51
gem5::X86ISA::L
Bitfield< 7, 0 > L
Definition: int.hh:59
gem5::X86ISA::SL
SignedBitfield< 7, 0 > SL
Definition: int.hh:60
gem5::X86ISA::SE
SignedBitfield< 31, 0 > SE
Definition: int.hh:54
gem5::X86ISA::INTREG_FOLDED
static IntRegIndex INTREG_FOLDED(int index, int foldBit)
Definition: int.hh:181
gem5::X86ISA::SR
SignedBitfield< 63, 0 > SR
Definition: int.hh:52
gem5::X86ISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:188
gem5::X86ISA::H
Bitfield< 15, 8 > H
Definition: int.hh:57
gem5::X86ISA::SH
SignedBitfield< 15, 8 > SH
Definition: int.hh:58
bitunion.hh
gem5::X86ISA::BitUnion64
BitUnion64(VAddr) Bitfield< 20
gem5::X86ISA::SX
SignedBitfield< 15, 0 > SX
Definition: int.hh:56
gem5::X86ISA::INTREG_MICRO
static IntRegIndex INTREG_MICRO(int index)
Definition: int.hh:175
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::E
Bitfield< 31, 0 > E
Definition: int.hh:53
logging.hh
gem5::X86ISA::NumMicroIntRegs
const int NumMicroIntRegs
Definition: x86_traits.hh:50
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
gem5::X86ISA::X
Bitfield< 15, 0 > X
Definition: int.hh:55
gem5::X86ISA::IntFoldBit
static const IntRegIndex IntFoldBit
Definition: int.hh:172

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