38 #ifndef __ARCH_X86_REGS_INT_HH__
39 #define __ARCH_X86_REGS_INT_HH__
45 #include "debug/IntRegs.hh"
55 SignedBitfield<63,0>
SR;
57 SignedBitfield<31,0>
SE;
59 SignedBitfield<15,0>
SX;
61 SignedBitfield<15,8>
SH;
63 SignedBitfield<7, 0>
SL;
131 inline constexpr
RegId
157 inline constexpr
auto
180 inline static constexpr
RegId
186 inline static constexpr
RegId
189 if ((
index & 0x1C) == 4 && foldBit)
Register ID: describe an architectural register with its class and index.
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
RegId flatten(const BaseISA &isa, const RegId &id) const override
Flatten register id id using information in the ISA object isa.
constexpr RegId Doublebits
constexpr RegId Remainder
static constexpr RegId intRegMicro(int index)
SignedBitfield< 31, 0 > SE
SignedBitfield< 63, 0 > SR
SignedBitfield< 15, 8 > SH
constexpr RegClass intRegClass
constexpr FlatIntRegClassOps flatIntRegClassOps
BitUnion64(VAddr) Bitfield< 20
const int NumMicroIntRegs
constexpr RegClass flatIntRegClass
static constexpr RegId intRegFolded(RegIndex index, RegIndex foldBit)
SignedBitfield< 7, 0 > SL
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
constexpr RegIndex IntFoldBit
constexpr IntRegClassOps intRegClassOps
SignedBitfield< 15, 0 > SX
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
constexpr char IntRegClassName[]
@ IntRegClass
Integer register.